src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 import functools
   8 import types
   9 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
  10 from soc.regfile.util import fast_reg_to_spr  # HACK!
  11 from soc.regfile.regfiles import XERRegs, FastRegs
  12
  13
  14 # TODO: make this a util routine (somewhere)
  15 def mask_extend(x, nbits, repeat):
  16     res = 0
  17     extended = (1<<repeat)-1
  18     for i in range(nbits):
  19         if x & (1<<i):
  20             res |= extended << (i*repeat)
  21     return res
  22
  23
  24 class SkipCase(Exception):
  25     """Raise this exception to skip a test case.
  26
  27     Usually you'd use one of the skip_case* decorators.
  28
  29     For use with TestAccumulatorBase
  30     """
  31
  32
  33 def _id(obj):
  34     """identity function"""
  35     return obj
  36
  37
  38 def skip_case(reason):
  39     """
  40     Unconditionally skip a test case.
  41
  42     Use like:
  43         @skip_case("my reason for skipping")
  44         def case_abc(self):
  45             ...
  46     or:
  47         @skip_case
  48         def case_def(self):
  49             ...
  50
  51     For use with TestAccumulatorBase
  52     """
  53     def decorator(item):
  54         assert not isinstance(item, type), \
  55             "can't use skip_case to decorate types"
  56
  57         @functools.wraps(item)
  58         def wrapper(*args, **kwargs):
  59             raise SkipCase(reason)
  60         return wrapper
  61     if isinstance(reason, types.FunctionType):
  62         item = reason
  63         reason = ""
  64         return decorator(item)
  65     return decorator
  66
  67
  68 def skip_case_if(condition, reason):
  69     """
  70     Conditionally skip a test case.
  71
  72     Use like:
  73         @skip_case_if(should_i_skip(), "my reason for skipping")
  74         def case_abc(self):
  75             ...
  76
  77     For use with TestAccumulatorBase
  78     """
  79     if condition:
  80         return skip_case(reason)
  81     return _id
  82
  83
  84 class TestAccumulatorBase:
  85
  86     def __init__(self):
  87         self.test_data = []
  88         # automatically identifies anything starting with "case_" and
  89         # runs it.  very similar to unittest auto-identification except
  90         # we need a different system
  91         for n, v in self.__class__.__dict__.items():
  92             if n.startswith("case_") and callable(v):
  93                 try:
  94                     v(self)
  95                 except SkipCase as e:
  96                     # TODO(programmerjake): translate to final test sending
  97                     # skip signal to unittest. for now, just print the skipped
  98                     # reason and ignore
  99                     print(f"SKIPPED({n}):", str(e))
 100
 101     def add_case(self, prog, initial_regs=None, initial_sprs=None,
 102                  initial_cr=0, initial_msr=0,
 103                  initial_mem=None):
 104
 105         test_name = inspect.stack()[1][3]  # name of caller of this function
 106         tc = TestCase(prog, test_name,
 107                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
 108                       msr=initial_msr,
 109                       mem=initial_mem)
 110
 111         self.test_data.append(tc)
 112
 113
 114 class TestCase:
 115     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 116                  msr=0,
 117                  do_sim=True,
 118                  extra_break_addr=None):
 119
 120         self.program = program
 121         self.name = name
 122
 123         if regs is None:
 124             regs = [0] * 32
 125         if sprs is None:
 126             sprs = {}
 127         if mem is None:
 128             mem = {}
 129         self.regs = regs
 130         self.sprs = sprs
 131         self.cr = cr
 132         self.mem = mem
 133         self.msr = msr
 134         self.do_sim = do_sim
 135         self.extra_break_addr = extra_break_addr
 136
 137
 138 class ALUHelpers:
 139
 140     def get_sim_fast_reg(res, sim, dec2, reg, name):
 141         spr_sel = fast_reg_to_spr(reg)
 142         spr_data = sim.spr[spr_sel].value
 143         res[name] = spr_data
 144
 145     def get_sim_cia(res, sim, dec2):
 146         res['cia'] = sim.pc.CIA.value
 147
 148     # use this *after* the simulation has run a step (it returns CIA)
 149     def get_sim_nia(res, sim, dec2):
 150         res['nia'] = sim.pc.CIA.value
 151
 152     def get_sim_msr(res, sim, dec2):
 153         res['msr'] = sim.msr.value
 154
 155     def get_sim_slow_spr1(res, sim, dec2):
 156         spr1_en = yield dec2.e.read_spr1.ok
 157         if spr1_en:
 158             spr1_sel = yield dec2.e.read_spr1.data
 159             spr1_data = sim.spr[spr1_sel].value
 160             res['spr1'] = spr1_data
 161
 162     def get_sim_fast_spr1(res, sim, dec2):
 163         fast1_en = yield dec2.e.read_fast1.ok
 164         if fast1_en:
 165             fast1_sel = yield dec2.e.read_fast1.data
 166             spr1_sel = fast_reg_to_spr(fast1_sel)
 167             spr1_data = sim.spr[spr1_sel].value
 168             res['fast1'] = spr1_data
 169
 170     def get_sim_fast_spr2(res, sim, dec2):
 171         fast2_en = yield dec2.e.read_fast2.ok
 172         if fast2_en:
 173             fast2_sel = yield dec2.e.read_fast2.data
 174             spr2_sel = fast_reg_to_spr(fast2_sel)
 175             spr2_data = sim.spr[spr2_sel].value
 176             res['fast2'] = spr2_data
 177
 178     def get_sim_cr_a(res, sim, dec2):
 179         cridx_ok = yield dec2.e.read_cr1.ok
 180         if cridx_ok:
 181             cridx = yield dec2.e.read_cr1.data
 182             res['cr_a'] = sim.crl[cridx].get_range().value
 183
 184     def get_sim_int_ra(res, sim, dec2):
 185         # TODO: immediate RA zero
 186         reg1_ok = yield dec2.e.read_reg1.ok
 187         if reg1_ok:
 188             data1 = yield dec2.e.read_reg1.data
 189             res['ra'] = sim.gpr(data1).value
 190
 191     def get_sim_int_rb(res, sim, dec2):
 192         reg2_ok = yield dec2.e.read_reg2.ok
 193         if reg2_ok:
 194             data = yield dec2.e.read_reg2.data
 195             res['rb'] = sim.gpr(data).value
 196
 197     def get_sim_int_rc(res, sim, dec2):
 198         reg3_ok = yield dec2.e.read_reg3.ok
 199         if reg3_ok:
 200             data = yield dec2.e.read_reg3.data
 201             res['rc'] = sim.gpr(data).value
 202
 203     def get_rd_sim_xer_ca(res, sim, dec2):
 204         cry_in = yield dec2.e.do.input_carry
 205         xer_in = yield dec2.e.xer_in
 206         if (xer_in & (1<<XERRegs.CA)) or cry_in == CryIn.CA.value:
 207             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 208             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 209             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 210
 211     def set_int_ra(alu, dec2, inp):
 212         # TODO: immediate RA zero.
 213         if 'ra' in inp:
 214             yield alu.p.data_i.ra.eq(inp['ra'])
 215         else:
 216             yield alu.p.data_i.ra.eq(0)
 217
 218     def set_int_rb(alu, dec2, inp):
 219         yield alu.p.data_i.rb.eq(0)
 220         if 'rb' in inp:
 221             yield alu.p.data_i.rb.eq(inp['rb'])
 222         # If there's an immediate, set the B operand to that
 223         imm_ok = yield dec2.e.do.imm_data.imm_ok
 224         if imm_ok:
 225             data2 = yield dec2.e.do.imm_data.imm
 226             yield alu.p.data_i.rb.eq(data2)
 227
 228     def set_int_rc(alu, dec2, inp):
 229         if 'rc' in inp:
 230             yield alu.p.data_i.rc.eq(inp['rc'])
 231         else:
 232             yield alu.p.data_i.rc.eq(0)
 233
 234     def set_xer_ca(alu, dec2, inp):
 235         if 'xer_ca' in inp:
 236             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 237             print("extra inputs: CA/32", bin(inp['xer_ca']))
 238
 239     def set_xer_ov(alu, dec2, inp):
 240         if 'xer_ov' in inp:
 241             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 242             print("extra inputs: OV/32", bin(inp['xer_ov']))
 243
 244     def set_xer_so(alu, dec2, inp):
 245         if 'xer_so' in inp:
 246             so = inp['xer_so']
 247             print("extra inputs: so", so)
 248             yield alu.p.data_i.xer_so.eq(so)
 249
 250     def set_msr(alu, dec2, inp):
 251         print("TODO: deprecate set_msr")
 252         if 'msr' in inp:
 253             yield alu.p.data_i.msr.eq(inp['msr'])
 254
 255     def set_cia(alu, dec2, inp):
 256         print("TODO: deprecate set_cia")
 257         if 'cia' in inp:
 258             yield alu.p.data_i.cia.eq(inp['cia'])
 259
 260     def set_slow_spr1(alu, dec2, inp):
 261         if 'spr1' in inp:
 262             yield alu.p.data_i.spr1.eq(inp['spr1'])
 263
 264     def set_slow_spr2(alu, dec2, inp):
 265         if 'spr2' in inp:
 266             yield alu.p.data_i.spr2.eq(inp['spr2'])
 267
 268     def set_fast_spr1(alu, dec2, inp):
 269         if 'fast1' in inp:
 270             yield alu.p.data_i.fast1.eq(inp['fast1'])
 271
 272     def set_fast_spr2(alu, dec2, inp):
 273         if 'fast2' in inp:
 274             yield alu.p.data_i.fast2.eq(inp['fast2'])
 275
 276     def set_cr_a(alu, dec2, inp):
 277         if 'cr_a' in inp:
 278             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 279
 280     def set_cr_b(alu, dec2, inp):
 281         if 'cr_b' in inp:
 282             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 283
 284     def set_cr_c(alu, dec2, inp):
 285         if 'cr_c' in inp:
 286             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 287
 288     def set_full_cr(alu, dec2, inp):
 289         if 'full_cr' in inp:
 290             full_reg = yield dec2.e.do.read_cr_whole.data
 291             full_reg_ok = yield dec2.e.do.read_cr_whole.ok
 292             full_cr_mask = mask_extend(full_reg, 8, 4)
 293             yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask)
 294         else:
 295             yield alu.p.data_i.full_cr.eq(0)
 296
 297     def get_slow_spr1(res, alu, dec2):
 298         spr1_valid = yield alu.n.data_o.spr1.ok
 299         if spr1_valid:
 300             res['spr1'] = yield alu.n.data_o.spr1.data
 301
 302     def get_slow_spr2(res, alu, dec2):
 303         spr2_valid = yield alu.n.data_o.spr2.ok
 304         if spr2_valid:
 305             res['spr2'] = yield alu.n.data_o.spr2.data
 306
 307     def get_fast_spr1(res, alu, dec2):
 308         spr1_valid = yield alu.n.data_o.fast1.ok
 309         if spr1_valid:
 310             res['fast1'] = yield alu.n.data_o.fast1.data
 311
 312     def get_fast_spr2(res, alu, dec2):
 313         spr2_valid = yield alu.n.data_o.fast2.ok
 314         if spr2_valid:
 315             res['fast2'] = yield alu.n.data_o.fast2.data
 316
 317     def get_cia(res, alu, dec2):
 318         res['cia'] = yield alu.p.data_i.cia
 319
 320     def get_nia(res, alu, dec2):
 321         nia_valid = yield alu.n.data_o.nia.ok
 322         if nia_valid:
 323             res['nia'] = yield alu.n.data_o.nia.data
 324
 325     def get_msr(res, alu, dec2):
 326         msr_valid = yield alu.n.data_o.msr.ok
 327         if msr_valid:
 328             res['msr'] = yield alu.n.data_o.msr.data
 329
 330     def get_int_o1(res, alu, dec2):
 331         out_reg_valid = yield dec2.e.write_ea.ok
 332         if out_reg_valid:
 333             res['o1'] = yield alu.n.data_o.o1.data
 334
 335     def get_int_o(res, alu, dec2):
 336         out_reg_valid = yield dec2.e.write_reg.ok
 337         if out_reg_valid:
 338             res['o'] = yield alu.n.data_o.o.data
 339
 340     def get_cr_a(res, alu, dec2):
 341         cridx_ok = yield dec2.e.write_cr.ok
 342         if cridx_ok:
 343             res['cr_a'] = yield alu.n.data_o.cr0.data
 344
 345     def get_xer_so(res, alu, dec2):
 346         oe = yield dec2.e.do.oe.oe
 347         oe_ok = yield dec2.e.do.oe.ok
 348         xer_out = yield dec2.e.xer_out
 349         if not (yield alu.n.data_o.xer_so.ok):
 350             return
 351         if xer_out or (oe and oe_ok):
 352             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 353
 354     def get_xer_ov(res, alu, dec2):
 355         oe = yield dec2.e.do.oe.oe
 356         oe_ok = yield dec2.e.do.oe.ok
 357         xer_out = yield dec2.e.xer_out
 358         if not (yield alu.n.data_o.xer_ov.ok):
 359             return
 360         if xer_out or (oe and oe_ok):
 361             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 362
 363     def get_xer_ca(res, alu, dec2):
 364         cry_out = yield dec2.e.do.output_carry
 365         xer_out = yield dec2.e.xer_out
 366         if not (yield alu.n.data_o.xer_ca.ok):
 367             return
 368         if xer_out or (cry_out):
 369             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 370
 371     def get_sim_int_o(res, sim, dec2):
 372         out_reg_valid = yield dec2.e.write_reg.ok
 373         if out_reg_valid:
 374             write_reg_idx = yield dec2.e.write_reg.data
 375             res['o'] = sim.gpr(write_reg_idx).value
 376
 377     def get_sim_int_o1(res, sim, dec2):
 378         out_reg_valid = yield dec2.e.write_ea.ok
 379         if out_reg_valid:
 380             write_reg_idx = yield dec2.e.write_ea.data
 381             res['o1'] = sim.gpr(write_reg_idx).value
 382
 383     def get_wr_sim_cr_a(res, sim, dec2):
 384         cridx_ok = yield dec2.e.write_cr.ok
 385         if cridx_ok:
 386             cridx = yield dec2.e.write_cr.data
 387             res['cr_a'] = sim.crl[cridx].get_range().value
 388
 389     def get_wr_fast_spr2(res, sim, dec2):
 390         ok = yield dec2.e.write_fast2.ok
 391         if ok:
 392             spr_num = yield dec2.e.write_fast2.data
 393             spr_num = fast_reg_to_spr(spr_num)
 394             spr_name = spr_dict[spr_num].SPR
 395             res['fast2'] = sim.spr[spr_name].value
 396
 397     def get_wr_fast_spr1(res, sim, dec2):
 398         ok = yield dec2.e.write_fast1.ok
 399         if ok:
 400             spr_num = yield dec2.e.write_fast1.data
 401             spr_num = fast_reg_to_spr(spr_num)
 402             spr_name = spr_dict[spr_num].SPR
 403             res['fast1'] = sim.spr[spr_name].value
 404
 405     def get_wr_slow_spr1(res, sim, dec2):
 406         ok = yield dec2.e.write_spr.ok
 407         if ok:
 408             spr_num = yield dec2.e.write_spr.data
 409             spr_name = spr_dict[spr_num].SPR
 410             res['spr1'] = sim.spr[spr_name].value
 411
 412     def get_wr_sim_xer_ca(res, sim, dec2):
 413         # if not (yield alu.n.data_o.xer_ca.ok):
 414         #    return
 415         cry_out = yield dec2.e.do.output_carry
 416         xer_out = yield dec2.e.xer_out
 417         if cry_out or xer_out:
 418             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 419             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 420             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 421
 422     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 423         oe = yield dec2.e.do.oe.oe
 424         oe_ok = yield dec2.e.do.oe.ok
 425         xer_out = yield dec2.e.xer_out
 426         print("get_wr_sim_xer_ov", xer_out)
 427         if not (yield alu.n.data_o.xer_ov.ok):
 428             return
 429         if xer_out or (oe and oe_ok):
 430             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 431             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 432             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 433
 434     def get_wr_sim_xer_so(res, sim, alu, dec2):
 435         oe = yield dec2.e.do.oe.oe
 436         oe_ok = yield dec2.e.do.oe.ok
 437         xer_out = yield dec2.e.xer_out
 438         if not (yield alu.n.data_o.xer_so.ok):
 439             return
 440         if xer_out or (oe and oe_ok):
 441             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 442
 443     def get_sim_xer_ov(res, sim, dec2):
 444         oe = yield dec2.e.do.oe.oe
 445         oe_ok = yield dec2.e.do.oe.ok
 446         xer_in = yield dec2.e.xer_in
 447         print("get_sim_xer_ov", xer_in)
 448         if (xer_in & (1<<XERRegs.OV)) or (oe and oe_ok):
 449             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 450             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 451             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 452
 453     def get_sim_xer_so(res, sim, dec2):
 454         print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
 455         oe = yield dec2.e.do.oe.oe
 456         oe_ok = yield dec2.e.do.oe.ok
 457         xer_in = yield dec2.e.xer_in
 458         rc = yield dec2.e.do.rc.rc
 459         rc_ok = yield dec2.e.do.rc.ok
 460         if (xer_in & (1<<XERRegs.SO)) or (oe and oe_ok) or (rc and rc_ok):
 461             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 462
 463     def check_slow_spr1(dut, res, sim_o, msg):
 464         if 'spr1' in res:
 465             expected = sim_o['spr1']
 466             alu_out = res['spr1']
 467             print(f"expected {expected:x}, actual: {alu_out:x}")
 468             dut.assertEqual(expected, alu_out, msg)
 469
 470     def check_fast_spr1(dut, res, sim_o, msg):
 471         if 'fast1' in res:
 472             expected = sim_o['fast1']
 473             alu_out = res['fast1']
 474             print(f"expected {expected:x}, actual: {alu_out:x}")
 475             dut.assertEqual(expected, alu_out, msg)
 476
 477     def check_fast_spr2(dut, res, sim_o, msg):
 478         if 'fast2' in res:
 479             expected = sim_o['fast2']
 480             alu_out = res['fast2']
 481             print(f"expected {expected:x}, actual: {alu_out:x}")
 482             dut.assertEqual(expected, alu_out, msg)
 483
 484     def check_int_o1(dut, res, sim_o, msg):
 485         if 'o1' in res:
 486             expected = sim_o['o1']
 487             alu_out = res['o1']
 488             print(f"expected {expected:x}, actual: {alu_out:x}")
 489             dut.assertEqual(expected, alu_out, msg)
 490
 491     def check_int_o(dut, res, sim_o, msg):
 492         if 'o' in res:
 493             expected = sim_o['o']
 494             alu_out = res['o']
 495             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 496             dut.assertEqual(expected, alu_out, msg)
 497
 498     def check_msr(dut, res, sim_o, msg):
 499         if 'msr' in res:
 500             expected = sim_o['msr']
 501             alu_out = res['msr']
 502             print(f"expected {expected:x}, actual: {alu_out:x}")
 503             dut.assertEqual(expected, alu_out, msg)
 504
 505     def check_nia(dut, res, sim_o, msg):
 506         if 'nia' in res:
 507             expected = sim_o['nia']
 508             alu_out = res['nia']
 509             print(f"expected {expected:x}, actual: {alu_out:x}")
 510             dut.assertEqual(expected, alu_out, msg)
 511
 512     def check_cr_a(dut, res, sim_o, msg):
 513         if 'cr_a' in res:
 514             cr_expected = sim_o['cr_a']
 515             cr_actual = res['cr_a']
 516             print("CR", cr_expected, cr_actual)
 517             dut.assertEqual(cr_expected, cr_actual, msg)
 518
 519     def check_xer_ca(dut, res, sim_o, msg):
 520         if 'xer_ca' in res:
 521             ca_expected = sim_o['xer_ca']
 522             ca_actual = res['xer_ca']
 523             print("CA", ca_expected, ca_actual)
 524             dut.assertEqual(ca_expected, ca_actual, msg)
 525
 526     def check_xer_ov(dut, res, sim_o, msg):
 527         if 'xer_ov' in res:
 528             ov_expected = sim_o['xer_ov']
 529             ov_actual = res['xer_ov']
 530             print("OV", ov_expected, ov_actual)
 531             dut.assertEqual(ov_expected, ov_actual, msg)
 532
 533     def check_xer_so(dut, res, sim_o, msg):
 534         if 'xer_so' in res:
 535             so_expected = sim_o['xer_so']
 536             so_actual = res['xer_so']
 537             print("SO", so_expected, so_actual)
 538             dut.assertEqual(so_expected, so_actual, msg)