src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits
   7
   8
   9 class TestCase:
  10     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  11                        msr=0):
  12
  13         self.program = program
  14         self.name = name
  15
  16         if regs is None:
  17             regs = [0] * 32
  18         if sprs is None:
  19             sprs = {}
  20         if mem is None:
  21             mem = {}
  22         self.regs = regs
  23         self.sprs = sprs
  24         self.cr = cr
  25         self.mem = mem
  26         self.msr = msr
  27
  28 class ALUHelpers:
  29
  30     def get_sim_cr_a(res, sim, dec2):
  31         cridx_ok = yield dec2.e.read_cr1.ok
  32         if cridx_ok:
  33             cridx = yield dec2.e.read_cr1.data
  34             res['cr_a'] = sim.crl[cridx].get_range().value
  35
  36     def get_sim_int_ra(res, sim, dec2):
  37         # TODO: immediate RA zero
  38         reg1_ok = yield dec2.e.read_reg1.ok
  39         if reg1_ok:
  40             data1 = yield dec2.e.read_reg1.data
  41             res['ra'] = sim.gpr(data1).value
  42
  43     def get_sim_int_rb(res, sim, dec2):
  44         reg2_ok = yield dec2.e.read_reg2.ok
  45         if reg2_ok:
  46             data = yield dec2.e.read_reg2.data
  47             res['rb'] = sim.gpr(data).value
  48
  49     def set_int_ra(alu, dec2, inp):
  50         # TODO: immediate RA zero.
  51         if 'ra' in inp:
  52             yield alu.p.data_i.ra.eq(inp['ra'])
  53         else:
  54             yield alu.p.data_i.ra.eq(0)
  55
  56     def set_int_rb(alu, dec2, inp):
  57         yield alu.p.data_i.rb.eq(0)
  58         if 'rb' in inp:
  59             yield alu.p.data_i.rb.eq(inp['rb'])
  60         # If there's an immediate, set the B operand to that
  61         imm_ok = yield dec2.e.imm_data.imm_ok
  62         if imm_ok:
  63             data2 = yield dec2.e.imm_data.imm
  64             yield alu.p.data_i.rb.eq(data2)
  65
  66     def set_int_rc(alu, dec2, inp):
  67         if 'rc' in inp:
  68             yield alu.p.data_i.rc.eq(inp['rc'])
  69         else:
  70             yield alu.p.data_i.rc.eq(0)
  71
  72     def set_xer_ca(alu, dec2, inp):
  73         if 'xer_ca' in inp:
  74             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
  75             print ("extra inputs: CA/32", bin(inp['xer_ca']))
  76
  77     def set_xer_so(alu, dec2, inp):
  78         if 'xer_so' in inp:
  79             so = inp['xer_so']
  80             print ("extra inputs: so", so)
  81             yield alu.p.data_i.xer_so.eq(so)
  82
  83     def set_fast_cia(alu, dec2, inp):
  84         if 'cia' in inp:
  85             yield alu.p.data_i.cia.eq(inp['cia'])
  86
  87     def set_fast_spr1(alu, dec2, inp):
  88         if 'spr1' in inp:
  89             yield alu.p.data_i.spr1.eq(inp['spr1'])
  90
  91     def set_fast_spr2(alu, dec2, inp):
  92         if 'spr2' in inp:
  93             yield alu.p.data_i.spr2.eq(inp['spr2'])
  94
  95     def set_cr_a(alu, dec2, inp):
  96         if 'cr_a' in inp:
  97             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
  98
  99     def set_cr_b(alu, dec2, inp):
 100         if 'cr_b' in inp:
 101             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 102
 103     def set_cr_c(alu, dec2, inp):
 104         if 'cr_c' in inp:
 105             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 106
 107     def set_full_cr(alu, dec2, inp):
 108         if 'full_cr' in inp:
 109             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 110         else:
 111             yield alu.p.data_i.full_cr.eq(0)
 112
 113     def get_int_o(res, alu, dec2):
 114         out_reg_valid = yield dec2.e.write_reg.ok
 115         if out_reg_valid:
 116             res['o'] = yield alu.n.data_o.o.data
 117
 118     def get_cr_a(res, alu, dec2):
 119         cridx_ok = yield dec2.e.write_cr.ok
 120         if cridx_ok:
 121             res['cr_a'] = yield alu.n.data_o.cr0.data
 122
 123     def get_xer_so(res, alu, dec2):
 124         oe = yield dec2.e.oe.oe
 125         oe_ok = yield dec2.e.oe.ok
 126         if oe and oe_ok:
 127             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 128
 129     def get_xer_ov(res, alu, dec2):
 130         oe = yield dec2.e.oe.oe
 131         oe_ok = yield dec2.e.oe.ok
 132         if oe and oe_ok:
 133             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 134
 135     def get_xer_ca(res, alu, dec2):
 136         cry_out = yield dec2.e.output_carry
 137         if cry_out:
 138             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 139
 140     def get_sim_int_o(res, sim, dec2):
 141         out_reg_valid = yield dec2.e.write_reg.ok
 142         if out_reg_valid:
 143             write_reg_idx = yield dec2.e.write_reg.data
 144             res['o'] = sim.gpr(write_reg_idx).value
 145
 146     def get_wr_sim_cr_a(res, sim, dec2):
 147         cridx_ok = yield dec2.e.write_cr.ok
 148         if cridx_ok:
 149             cridx = yield dec2.e.write_cr.data
 150             res['cr_a'] = sim.crl[cridx].get_range().value
 151
 152     def get_sim_xer_ca(res, sim, dec2):
 153         cry_out = yield dec2.e.output_carry
 154         if cry_out:
 155             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 156             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 157             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 158
 159     def get_sim_xer_ov(res, sim, dec2):
 160         oe = yield dec2.e.oe.oe
 161         oe_ok = yield dec2.e.oe.ok
 162         if oe and oe_ok:
 163             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 164             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 165             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 166
 167     def get_sim_xer_so(res, sim, dec2):
 168         oe = yield dec2.e.oe.oe
 169         oe_ok = yield dec2.e.oe.ok
 170         if oe and oe_ok:
 171             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 172
 173     def check_int_o(dut, res, sim_o, msg):
 174         if 'o' in res:
 175             expected = sim_o['o']
 176             alu_out = res['o']
 177             print(f"expected {expected:x}, actual: {alu_out:x}")
 178             dut.assertEqual(expected, alu_out, msg)
 179
 180     def check_cr_a(dut, res, sim_o, msg):
 181         if 'cr_a' in res:
 182             cr_expected = sim_o['cr_a']
 183             cr_actual = res['cr_a']
 184             print ("CR", cr_expected, cr_actual)
 185             dut.assertEqual(cr_expected, cr_actual, msg)
 186
 187     def check_xer_ca(dut, res, sim_o, msg):
 188         if 'xer_ca' in res:
 189             ca_expected = sim_o['xer_ca']
 190             ca_actual = res['xer_ca']
 191             print ("CA", ca_expected, ca_actual)
 192             dut.assertEqual(ca_expected, ca_actual, msg)
 193
 194     def check_xer_ov(dut, res, sim_o, msg):
 195         if 'xer_ov' in res:
 196             ov_expected = sim_o['xer_ov']
 197             ov_actual = res['xer_ov']
 198             print ("OV", ov_expected, ov_actual)
 199             dut.assertEqual(ov_expected, ov_actual, msg)
 200
 201     def check_xer_so(dut, res, sim_o, msg):
 202         if 'xer_so' in res:
 203             so_expected = sim_o['xer_so']
 204             so_actual = res['xer_so']
 205             print ("SO", so_expected, so_actual)
 206             dut.assertEqual(so_expected, so_actual, msg)
 207