6 from migen
import (Signal
, FSM
, If
, Display
, Finish
, NextValue
, NextState
)
8 from litex
.build
.generic_platform
import Pins
, Subsignal
9 from litex
.build
.sim
import SimPlatform
10 from litex
.build
.io
import CRG
11 from litex
.build
.sim
.config
import SimConfig
13 from litex
.soc
.integration
.soc
import SoCRegion
14 from litex
.soc
.integration
.soc_core
import SoCCore
15 from litex
.soc
.integration
.builder
import Builder
17 from litex
.tools
.litex_sim
import Platform
19 from libresoc
import LibreSoC
20 from microwatt
import Microwatt
22 # LibreSoCSim -----------------------------------------------------------------
24 class LibreSoCSim(SoCCore
):
25 def __init__(self
, cpu
="libresoc", debug
=False):
26 assert cpu
in ["libresoc", "microwatt"]
28 sys_clk_freq
= int(1e6
)
30 # SoCCore -------------------------------------------------------------
31 SoCCore
.__init
__(self
, platform
, clk_freq
=sys_clk_freq
,
32 cpu_type
= "microwatt",
33 cpu_cls
= LibreSoC
if cpu
== "libresoc" \
36 integrated_rom_size
= 0x10000,
37 integrated_main_ram_size
= 0x10000000) # 256MB
38 self
.platform
.name
= "sim"
40 # CRG -----------------------------------------------------------------
41 self
.submodules
.crg
= CRG(platform
.request("sys_clk"))
43 # Debug ---------------------------------------------------------------
47 # setup running of DMI FSM
55 # increment counter, Stop after 100000 cycles
57 self
.sync
+= uptime
.eq(uptime
+ 1)
58 self
.sync
+= If(uptime
== 100000, Finish())
61 self
.submodules
+= dmifsm
66 (self
.cpu
.dmi_addr
.eq(dmi_addr
), # DMI Addr
67 self
.cpu
.dmi_din
.eq(dmi_din
), # DMI in
68 self
.cpu
.dmi_req
.eq(1), # DMI request
69 self
.cpu
.dmi_wr
.eq(1), # DMI write
79 (NextValue(dmi_req
, 0),
80 NextValue(dmi_addr
, 0),
81 NextValue(dmi_din
, 0),
82 NextValue(dmi_wen
, 0),
83 NextState("START"), # back to start on next cycle
88 self
.sync
+= If(uptime
== 0,
89 (dmi_addr
.eq(0), # CTRL
90 dmi_din
.eq(1<<0), # STOP
96 # loop every 1<<N cycles
100 self
.sync
+= If(uptime
[0:cyclewid
] == 4,
101 (dmi_addr
.eq(0), # CTRL
102 dmi_din
.eq(1<<3), # STEP
109 self
.sync
+= If(self
.cpu
.ibus
.stb
& self
.cpu
.ibus
.ack
&
111 Display("[%06x] iadr: %8x, s %01x w %016x",
119 self
.sync
+= If(self
.cpu
.ibus
.stb
& self
.cpu
.ibus
.ack
&
121 Display("[%06x] iadr: %8x, s %01x r %016x",
129 # monitor bbus read/write
130 self
.sync
+= If(self
.cpu
.dbus
.stb
& self
.cpu
.dbus
.ack
,
131 Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
141 # Build -----------------------------------------------------------------------
144 parser
= argparse
.ArgumentParser(description
="LiteX LibreSoC CPU Sim")
145 parser
.add_argument("--cpu", default
="libresoc",
146 help="CPU to use: libresoc (default) or microwatt")
147 parser
.add_argument("--debug", action
="store_true",
148 help="Enable debug traces")
149 parser
.add_argument("--trace", action
="store_true",
150 help="Enable tracing")
151 parser
.add_argument("--trace-start", default
=0,
152 help="Cycle to start FST tracing")
153 parser
.add_argument("--trace-end", default
=-1,
154 help="Cycle to end FST tracing")
155 args
= parser
.parse_args()
157 sim_config
= SimConfig(default_clk
="sys_clk")
158 sim_config
.add_module("serial2console", "serial")
161 soc
= LibreSoCSim(cpu
=args
.cpu
, debug
=args
.debug
)
162 builder
= Builder(soc
,compile_gateware
= i
!=0)
163 builder
.build(sim_config
=sim_config
,
166 trace_start
= int(args
.trace_start
),
167 trace_end
= int(args
.trace_end
),
171 if __name__
== "__main__":