src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  89                                                     features={'err'}))
  90
  91         # add interrupt controller?
  92         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  93         if self.xics:
  94             self.xics_icp = XICS_ICP()
  95             self.xics_ics = XICS_ICS()
  96             self.int_level_i = self.xics_ics.int_level_i
  97
  98         # add GPIO peripheral?
  99         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 100         if self.gpio:
 101             self.simple_gpio = SimpleGPIO()
 102             self.gpio_o = self.simple_gpio.gpio_o
 103
 104         # main instruction core25
 105         self.core = core = NonProductionCore(pspec)
 106
 107         # instruction decoder.  goes into Trap Record
 108         pdecode = create_pdecode()
 109         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 110         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 111                                      opkls=IssuerDecode2ToOperand)
 112         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 113
 114         # Test Instruction memory
 115         self.imem = ConfigFetchUnit(pspec).fu
 116         # one-row cache of instruction read
 117         self.iline = Signal(64) # one instruction line
 118         self.iprev_adr = Signal(64) # previous address: if different, do read
 119
 120         # DMI interface
 121         self.dbg = CoreDebug()
 122
 123         # instruction go/monitor
 124         self.pc_o = Signal(64, reset_less=True)
 125         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 126         self.svstate_i = Data(32, "svstate_i") # ditto
 127         self.core_bigendian_i = Signal()
 128         self.busy_o = Signal(reset_less=True)
 129         self.memerr_o = Signal(reset_less=True)
 130
 131         # STATE regfile read /write ports for PC, MSR, SVSTATE
 132         staterf = self.core.regs.rf['state']
 133         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 134         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 135         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 136         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 137         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 138
 139         # DMI interface access
 140         intrf = self.core.regs.rf['int']
 141         crrf = self.core.regs.rf['cr']
 142         xerrf = self.core.regs.rf['xer']
 143         self.int_r = intrf.r_ports['dmi'] # INT read
 144         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 145         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 146
 147         # hack method of keeping an eye on whether branch/trap set the PC
 148         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 149         self.state_nia.wen.name = 'state_nia_wen'
 150
 151     def fetch_fsm(self, m, core, pc, svstate, nia,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 165
 166         msr_read = Signal(reset=1)
 167
 168         with m.FSM(name='fetch_fsm'):
 169
 170             # waiting (zzz)
 171             with m.State("IDLE"):
 172                 comb += fetch_pc_ready_o.eq(1)
 173                 with m.If(fetch_pc_valid_i):
 174                     # instruction allowed to go: start by reading the PC
 175                     # capture the PC and also drop it into Insn Memory
 176                     # we have joined a pair of combinatorial memory
 177                     # lookups together.  this is Generally Bad.
 178                     comb += self.imem.a_pc_i.eq(pc)
 179                     comb += self.imem.a_valid_i.eq(1)
 180                     comb += self.imem.f_valid_i.eq(1)
 181                     sync += cur_state.pc.eq(pc)
 182                     sync += cur_state.svstate.eq(svstate) # and svstate
 183
 184                     # initiate read of MSR. arrives one clock later
 185                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 186                     sync += msr_read.eq(0)
 187
 188                     m.next = "INSN_READ"  # move to "wait for bus" phase
 189
 190             # dummy pause to find out why simulation is not keeping up
 191             with m.State("INSN_READ"):
 192                 # one cycle later, msr/sv read arrives.  valid only once.
 193                 with m.If(~msr_read):
 194                     sync += msr_read.eq(1) # yeah don't read it again
 195                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 196                 with m.If(self.imem.f_busy_o): # zzz...
 197                     # busy: stay in wait-read
 198                     comb += self.imem.a_valid_i.eq(1)
 199                     comb += self.imem.f_valid_i.eq(1)
 200                 with m.Else():
 201                     # not busy: instruction fetched
 202                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 203                     # decode the SVP64 prefix, if any
 204                     comb += svp64.raw_opcode_in.eq(insn)
 205                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 206                     # pass the decoded prefix (if any) to PowerDecoder2
 207                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 208                     # calculate the address of the following instruction
 209                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 210                     sync += nia.eq(cur_state.pc + insn_size)
 211                     with m.If(~svp64.is_svp64_mode):
 212                         # with no prefix, store the instruction
 213                         # and hand it directly to the next FSM
 214                         sync += dec_opcode_i.eq(insn)
 215                         m.next = "INSN_READY"
 216                     with m.Else():
 217                         # fetch the rest of the instruction from memory
 218                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 219                         comb += self.imem.a_valid_i.eq(1)
 220                         comb += self.imem.f_valid_i.eq(1)
 221                         m.next = "INSN_READ2"
 222
 223             with m.State("INSN_READ2"):
 224                 with m.If(self.imem.f_busy_o):  # zzz...
 225                     # busy: stay in wait-read
 226                     comb += self.imem.a_valid_i.eq(1)
 227                     comb += self.imem.f_valid_i.eq(1)
 228                 with m.Else():
 229                     # not busy: instruction fetched
 230                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 231                     sync += dec_opcode_i.eq(insn)
 232                     m.next = "INSN_READY"
 233
 234             with m.State("INSN_READY"):
 235                 # hand over the instruction, to be decoded
 236                 comb += fetch_insn_valid_o.eq(1)
 237                 with m.If(fetch_insn_ready_i):
 238                     m.next = "IDLE"
 239
 240     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 241                   dbg, core_rst,
 242                   fetch_pc_ready_o, fetch_pc_valid_i,
 243                   fetch_insn_valid_o, fetch_insn_ready_i,
 244                   exec_insn_valid_i, exec_insn_ready_o,
 245                   exec_pc_valid_o, exec_pc_ready_i):
 246         """issue FSM
 247
 248         decode / issue FSM.  this interacts with the "fetch" FSM
 249         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 250         (outgoing). also interacts with the "execute" FSM
 251         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 252         (incoming).
 253         SVP64 RM prefixes have already been set up by the
 254         "fetch" phase, so execute is fairly straightforward.
 255         """
 256
 257         comb = m.d.comb
 258         sync = m.d.sync
 259         pdecode2 = self.pdecode2
 260         cur_state = self.cur_state
 261
 262         # temporaries
 263         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 264
 265         # for updating svstate (things like srcstep etc.)
 266         update_svstate = Signal() # set this (below) if updating
 267         new_svstate = SVSTATERec("new_svstate")
 268         comb += new_svstate.eq(cur_state.svstate)
 269
 270         with m.FSM(name="issue_fsm"):
 271
 272             # Wait on "core stop" release, at reset
 273             with m.State("WAIT_RESET"):
 274                 with m.If(~dbg.core_stop_o & ~core_rst):
 275                     m.next = "INSN_FETCH"
 276                 with m.Else():
 277                     comb += core.core_stopped_i.eq(1)
 278                     comb += dbg.core_stopped_i.eq(1)
 279
 280             # go fetch the instruction at the current PC
 281             # at this point, there is no instruction running, that
 282             # could inadvertently update the PC.
 283             with m.State("INSN_FETCH"):
 284                 # TODO: update PC here, before fetch
 285                 comb += fetch_pc_valid_i.eq(1)
 286                 with m.If(fetch_pc_ready_o):
 287                     m.next = "INSN_WAIT"
 288
 289             # decode the instruction when it arrives
 290             with m.State("INSN_WAIT"):
 291                 comb += fetch_insn_ready_i.eq(1)
 292                 with m.If(fetch_insn_valid_o):
 293                     # decode the instruction
 294                     sync += core.e.eq(pdecode2.e)
 295                     sync += core.state.eq(cur_state)
 296                     sync += core.raw_insn_i.eq(dec_opcode_i)
 297                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 298                     # TODO: loop into INSN_FETCH if it's a vector instruction
 299                     #       and VL == 0.  this because VL==0 is a for-loop
 300                     #       from 0 to 0 i.e. always, always a NOP.
 301                     m.next = "INSN_EXECUTE"  # move to "execute"
 302
 303             with m.State("INSN_EXECUTE"):
 304                 comb += exec_insn_valid_i.eq(1)
 305                 with m.If(exec_insn_ready_o):
 306                     m.next = "EXECUTE_WAIT"
 307
 308             with m.State("EXECUTE_WAIT"):
 309                 # wait on "core stop" release, at instruction end
 310                 with m.If(~dbg.core_stop_o & ~core_rst):
 311                     comb += exec_pc_ready_i.eq(1)
 312                     with m.If(exec_pc_valid_o):
 313                         # precalculate srcstep+1
 314                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 315                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 316                         # was this the last loop iteration?
 317                         is_last = Signal()
 318                         cur_vl = cur_state.svstate.vl
 319                         comb += is_last.eq(next_srcstep == cur_vl)
 320
 321                         # if either PC or SVSTATE were changed by the previous
 322                         # instruction, go directly back to Fetch, without
 323                         # updating either PC or SVSTATE
 324                         with m.If(pc_changed | sv_changed):
 325                             m.next = "INSN_FETCH"
 326
 327                         # also return to Fetch, when no output was a vector
 328                         # (regardless of SRCSTEP and VL), or when the last
 329                         # instruction was really the last one of the VL loop
 330                         with m.Elif(pdecode2.no_out_vec | is_last):
 331                             # before going back to fetch, update the PC state
 332                             # register with the NIA.
 333                             # ok here we are not reading the branch unit.
 334                             # TODO: this just blithely overwrites whatever
 335                             #       pipeline updated the PC
 336                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 337                             comb += self.state_w_pc.data_i.eq(nia)
 338                             # reset SRCSTEP before returning to Fetch
 339                             with m.If(~pdecode2.no_out_vec):
 340                                 comb += new_svstate.srcstep.eq(0)
 341                                 comb += update_svstate.eq(1)
 342                             m.next = "INSN_FETCH"
 343
 344                         # returning to Execute? then, first update SRCSTEP
 345                         with m.Else():
 346                             comb += new_svstate.srcstep.eq(next_srcstep)
 347                             comb += update_svstate.eq(1)
 348                             m.next = "DECODE_SV"
 349
 350                 with m.Else():
 351                     comb += core.core_stopped_i.eq(1)
 352                     comb += dbg.core_stopped_i.eq(1)
 353
 354             # need to decode the instruction again, after updating SRCSTEP
 355             # in the previous state.
 356             # mostly a copy of INSN_WAIT, but without the actual wait
 357             with m.State("DECODE_SV"):
 358                 # decode the instruction
 359                 sync += core.e.eq(pdecode2.e)
 360                 sync += core.state.eq(cur_state)
 361                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 362                 m.next = "INSN_EXECUTE"  # move to "execute"
 363
 364         # check if svstate needs updating: if so, write it to State Regfile
 365         with m.If(update_svstate):
 366             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 367             comb += self.state_w_sv.data_i.eq(new_svstate)
 368             sync += cur_state.svstate.eq(new_svstate) # for next clock
 369
 370     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 371                     exec_insn_valid_i, exec_insn_ready_o,
 372                     exec_pc_valid_o, exec_pc_ready_i):
 373         """execute FSM
 374
 375         execute FSM. this interacts with the "issue" FSM
 376         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 377         (outgoing). SVP64 RM prefixes have already been set up by the
 378         "issue" phase, so execute is fairly straightforward.
 379         """
 380
 381         comb = m.d.comb
 382         sync = m.d.sync
 383         pdecode2 = self.pdecode2
 384         svp64 = self.svp64
 385
 386         # temporaries
 387         core_busy_o = core.busy_o                 # core is busy
 388         core_ivalid_i = core.ivalid_i             # instruction is valid
 389         core_issue_i = core.issue_i               # instruction is issued
 390         insn_type = core.e.do.insn_type           # instruction MicroOp type
 391
 392         with m.FSM(name="exec_fsm"):
 393
 394             # waiting for instruction bus (stays there until not busy)
 395             with m.State("INSN_START"):
 396                 comb += exec_insn_ready_o.eq(1)
 397                 with m.If(exec_insn_valid_i):
 398                     comb += core_ivalid_i.eq(1)  # instruction is valid
 399                     comb += core_issue_i.eq(1)  # and issued
 400                     sync += sv_changed.eq(0)
 401                     sync += pc_changed.eq(0)
 402                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 403
 404             # instruction started: must wait till it finishes
 405             with m.State("INSN_ACTIVE"):
 406                 with m.If(insn_type != MicrOp.OP_NOP):
 407                     comb += core_ivalid_i.eq(1) # instruction is valid
 408                 # note changes to PC and SVSTATE
 409                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 410                     sync += sv_changed.eq(1)
 411                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 412                     sync += pc_changed.eq(1)
 413                 with m.If(~core_busy_o): # instruction done!
 414                     comb += insn_done.eq(1)
 415                     comb += exec_pc_valid_o.eq(1)
 416                     with m.If(exec_pc_ready_i):
 417                         m.next = "INSN_START"  # back to fetch
 418
 419     def elaborate(self, platform):
 420         m = Module()
 421         comb, sync = m.d.comb, m.d.sync
 422
 423         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 424         m.submodules.imem = imem = self.imem
 425         m.submodules.dbg = dbg = self.dbg
 426         if self.jtag_en:
 427             m.submodules.jtag = jtag = self.jtag
 428             # TODO: UART2GDB mux, here, from external pin
 429             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 430             sync += dbg.dmi.connect_to(jtag.dmi)
 431
 432         cur_state = self.cur_state
 433
 434         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 435         if self.sram4x4k:
 436             for i, sram in enumerate(self.sram4k):
 437                 m.submodules["sram4k_%d" % i] = sram
 438                 comb += sram.enable.eq(self.wb_sram_en)
 439
 440         # XICS interrupt handler
 441         if self.xics:
 442             m.submodules.xics_icp = icp = self.xics_icp
 443             m.submodules.xics_ics = ics = self.xics_ics
 444             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 445             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 446
 447         # GPIO test peripheral
 448         if self.gpio:
 449             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 450
 451         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 452         # XXX causes litex ECP5 test to get wrong idea about input and output
 453         # (but works with verilator sim *sigh*)
 454         #if self.gpio and self.xics:
 455         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 456
 457         # instruction decoder
 458         pdecode = create_pdecode()
 459         m.submodules.dec2 = pdecode2 = self.pdecode2
 460         m.submodules.svp64 = svp64 = self.svp64
 461
 462         # convenience
 463         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 464         intrf = self.core.regs.rf['int']
 465
 466         # clock delay power-on reset
 467         cd_por  = ClockDomain(reset_less=True)
 468         cd_sync = ClockDomain()
 469         core_sync = ClockDomain("coresync")
 470         m.domains += cd_por, cd_sync, core_sync
 471
 472         ti_rst = Signal(reset_less=True)
 473         delay = Signal(range(4), reset=3)
 474         with m.If(delay != 0):
 475             m.d.por += delay.eq(delay - 1)
 476         comb += cd_por.clk.eq(ClockSignal())
 477
 478         # power-on reset delay
 479         core_rst = ResetSignal("coresync")
 480         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 481         comb += core_rst.eq(ti_rst)
 482
 483         # busy/halted signals from core
 484         comb += self.busy_o.eq(core.busy_o)
 485         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 486
 487         # temporary hack: says "go" immediately for both address gen and ST
 488         l0 = core.l0
 489         ldst = core.fus.fus['ldst0']
 490         st_go_edge = rising_edge(m, ldst.st.rel_o)
 491         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 492         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 493
 494         # PC and instruction from I-Memory
 495         comb += self.pc_o.eq(cur_state.pc)
 496         pc_changed = Signal() # note write to PC
 497         sv_changed = Signal() # note write to SVSTATE
 498         insn_done = Signal()  # fires just once
 499
 500         # read the PC
 501         pc = Signal(64, reset_less=True)
 502         pc_ok_delay = Signal()
 503         sync += pc_ok_delay.eq(~self.pc_i.ok)
 504         with m.If(self.pc_i.ok):
 505             # incoming override (start from pc_i)
 506             comb += pc.eq(self.pc_i.data)
 507         with m.Else():
 508             # otherwise read StateRegs regfile for PC...
 509             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 510         # ... but on a 1-clock delay
 511         with m.If(pc_ok_delay):
 512             comb += pc.eq(self.state_r_pc.data_o)
 513
 514         # read svstate
 515         svstate = Signal(64, reset_less=True)
 516         svstate_ok_delay = Signal()
 517         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 518         with m.If(self.svstate_i.ok):
 519             # incoming override (start from svstate__i)
 520             comb += svstate.eq(self.svstate_i.data)
 521         with m.Else():
 522             # otherwise read StateRegs regfile for SVSTATE...
 523             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 524         # ... but on a 1-clock delay
 525         with m.If(svstate_ok_delay):
 526             comb += svstate.eq(self.state_r_sv.data_o)
 527
 528         # don't write pc every cycle
 529         comb += self.state_w_pc.wen.eq(0)
 530         comb += self.state_w_pc.data_i.eq(0)
 531
 532         # don't read msr every cycle
 533         comb += self.state_r_msr.ren.eq(0)
 534
 535         # address of the next instruction, in the absence of a branch
 536         # depends on the instruction size
 537         nia = Signal(64, reset_less=True)
 538
 539         # connect up debug signals
 540         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 541         comb += dbg.terminate_i.eq(core.core_terminate_o)
 542         comb += dbg.state.pc.eq(pc)
 543         comb += dbg.state.svstate.eq(svstate)
 544         comb += dbg.state.msr.eq(cur_state.msr)
 545
 546         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 547         # these are the handshake signals between fetch and decode/execute
 548
 549         # fetch FSM can run as soon as the PC is valid
 550         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 551         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 552
 553         # fetch FSM hands over the instruction to be decoded / issued
 554         fetch_insn_valid_o = Signal()
 555         fetch_insn_ready_i = Signal()
 556
 557         # issue FSM delivers the instruction to the be executed
 558         exec_insn_valid_i = Signal()
 559         exec_insn_ready_o = Signal()
 560
 561         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 562         exec_pc_valid_o = Signal()
 563         exec_pc_ready_i = Signal()
 564
 565         # actually use a nmigen FSM for the first time (w00t)
 566         # this FSM is perhaps unusual in that it detects conditions
 567         # then "holds" information, combinatorially, for the core
 568         # (as opposed to using sync - which would be on a clock's delay)
 569         # this includes the actual opcode, valid flags and so on.
 570
 571         self.fetch_fsm(m, core, pc, svstate, nia,
 572                        fetch_pc_ready_o, fetch_pc_valid_i,
 573                        fetch_insn_valid_o, fetch_insn_ready_i)
 574
 575         # TODO: an SVSTATE-based for-loop FSM that goes in between
 576         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 577         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 578         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 579                        dbg, core_rst,
 580                        fetch_pc_ready_o, fetch_pc_valid_i,
 581                        fetch_insn_valid_o, fetch_insn_ready_i,
 582                        exec_insn_valid_i, exec_insn_ready_o,
 583                        exec_pc_ready_i, exec_pc_valid_o)
 584
 585         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 586                          exec_insn_valid_i, exec_insn_ready_o,
 587                          exec_pc_ready_i, exec_pc_valid_o)
 588
 589         # this bit doesn't have to be in the FSM: connect up to read
 590         # regfiles on demand from DMI
 591         with m.If(d_reg.req): # request for regfile access being made
 592             # TODO: error-check this
 593             # XXX should this be combinatorial?  sync better?
 594             if intrf.unary:
 595                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 596             else:
 597                 comb += self.int_r.addr.eq(d_reg.addr)
 598                 comb += self.int_r.ren.eq(1)
 599         d_reg_delay  = Signal()
 600         sync += d_reg_delay.eq(d_reg.req)
 601         with m.If(d_reg_delay):
 602             # data arrives one clock later
 603             comb += d_reg.data.eq(self.int_r.data_o)
 604             comb += d_reg.ack.eq(1)
 605
 606         # sigh same thing for CR debug
 607         with m.If(d_cr.req): # request for regfile access being made
 608             comb += self.cr_r.ren.eq(0b11111111) # enable all
 609         d_cr_delay  = Signal()
 610         sync += d_cr_delay.eq(d_cr.req)
 611         with m.If(d_cr_delay):
 612             # data arrives one clock later
 613             comb += d_cr.data.eq(self.cr_r.data_o)
 614             comb += d_cr.ack.eq(1)
 615
 616         # aaand XER...
 617         with m.If(d_xer.req): # request for regfile access being made
 618             comb += self.xer_r.ren.eq(0b111111) # enable all
 619         d_xer_delay  = Signal()
 620         sync += d_xer_delay.eq(d_xer.req)
 621         with m.If(d_xer_delay):
 622             # data arrives one clock later
 623             comb += d_xer.data.eq(self.xer_r.data_o)
 624             comb += d_xer.ack.eq(1)
 625
 626         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 627         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 628         self.tb_dec_fsm(m, cur_state.dec)
 629
 630         return m
 631
 632     def tb_dec_fsm(self, m, spr_dec):
 633         """tb_dec_fsm
 634
 635         this is a FSM for updating either dec or tb.  it runs alternately
 636         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 637         value to DEC, however the regfile has "passthrough" on it so this
 638         *should* be ok.
 639
 640         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 641         """
 642
 643         comb, sync = m.d.comb, m.d.sync
 644         fast_rf = self.core.regs.rf['fast']
 645         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 646         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 647
 648         with m.FSM() as fsm:
 649
 650             # initiates read of current DEC
 651             with m.State("DEC_READ"):
 652                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 653                 comb += fast_r_dectb.ren.eq(1)
 654                 m.next = "DEC_WRITE"
 655
 656             # waits for DEC read to arrive (1 cycle), updates with new value
 657             with m.State("DEC_WRITE"):
 658                 new_dec = Signal(64)
 659                 # TODO: MSR.LPCR 32-bit decrement mode
 660                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 661                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 662                 comb += fast_w_dectb.wen.eq(1)
 663                 comb += fast_w_dectb.data_i.eq(new_dec)
 664                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 665                 m.next = "TB_READ"
 666
 667             # initiates read of current TB
 668             with m.State("TB_READ"):
 669                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 670                 comb += fast_r_dectb.ren.eq(1)
 671                 m.next = "TB_WRITE"
 672
 673             # waits for read TB to arrive, initiates write of current TB
 674             with m.State("TB_WRITE"):
 675                 new_tb = Signal(64)
 676                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 677                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 678                 comb += fast_w_dectb.wen.eq(1)
 679                 comb += fast_w_dectb.data_i.eq(new_tb)
 680                 m.next = "DEC_READ"
 681
 682         return m
 683
 684     def __iter__(self):
 685         yield from self.pc_i.ports()
 686         yield self.pc_o
 687         yield self.memerr_o
 688         yield from self.core.ports()
 689         yield from self.imem.ports()
 690         yield self.core_bigendian_i
 691         yield self.busy_o
 692
 693     def ports(self):
 694         return list(self)
 695
 696     def external_ports(self):
 697         ports = self.pc_i.ports()
 698         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 699                 ]
 700
 701         if self.jtag_en:
 702             ports += list(self.jtag.external_ports())
 703         else:
 704             # don't add DMI if JTAG is enabled
 705             ports += list(self.dbg.dmi.ports())
 706
 707         ports += list(self.imem.ibus.fields.values())
 708         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 709
 710         if self.sram4x4k:
 711             for sram in self.sram4k:
 712                 ports += list(sram.bus.fields.values())
 713
 714         if self.xics:
 715             ports += list(self.xics_icp.bus.fields.values())
 716             ports += list(self.xics_ics.bus.fields.values())
 717             ports.append(self.int_level_i)
 718
 719         if self.gpio:
 720             ports += list(self.simple_gpio.bus.fields.values())
 721             ports.append(self.gpio_o)
 722
 723         return ports
 724
 725     def ports(self):
 726         return list(self)
 727
 728
 729 class TestIssuer(Elaboratable):
 730     def __init__(self, pspec):
 731         self.ti = TestIssuerInternal(pspec)
 732
 733         self.pll = DummyPLL()
 734
 735         # PLL direct clock or not
 736         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 737         if self.pll_en:
 738             self.pll_18_o = Signal(reset_less=True)
 739
 740     def elaborate(self, platform):
 741         m = Module()
 742         comb = m.d.comb
 743
 744         # TestIssuer runs at direct clock
 745         m.submodules.ti = ti = self.ti
 746         cd_int = ClockDomain("coresync")
 747
 748         if self.pll_en:
 749             # ClockSelect runs at PLL output internal clock rate
 750             m.submodules.pll = pll = self.pll
 751
 752             # add clock domains from PLL
 753             cd_pll = ClockDomain("pllclk")
 754             m.domains += cd_pll
 755
 756             # PLL clock established.  has the side-effect of running clklsel
 757             # at the PLL's speed (see DomainRenamer("pllclk") above)
 758             pllclk = ClockSignal("pllclk")
 759             comb += pllclk.eq(pll.clk_pll_o)
 760
 761             # wire up external 24mhz to PLL
 762             comb += pll.clk_24_i.eq(ClockSignal())
 763
 764             # output 18 mhz PLL test signal
 765             comb += self.pll_18_o.eq(pll.pll_18_o)
 766
 767             # now wire up ResetSignals.  don't mind them being in this domain
 768             pll_rst = ResetSignal("pllclk")
 769             comb += pll_rst.eq(ResetSignal())
 770
 771         # internal clock is set to selector clock-out.  has the side-effect of
 772         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 773         intclk = ClockSignal("coresync")
 774         if self.pll_en:
 775             comb += intclk.eq(pll.clk_pll_o)
 776         else:
 777             comb += intclk.eq(ClockSignal())
 778
 779         return m
 780
 781     def ports(self):
 782         return list(self.ti.ports()) + list(self.pll.ports()) + \
 783                [ClockSignal(), ResetSignal()]
 784
 785     def external_ports(self):
 786         ports = self.ti.external_ports()
 787         ports.append(ClockSignal())
 788         ports.append(ResetSignal())
 789         if self.pll_en:
 790             ports.append(self.pll.clk_sel_i)
 791             ports.append(self.pll_18_o)
 792             ports.append(self.pll.pll_lck_o)
 793         return ports
 794
 795
 796 if __name__ == '__main__':
 797     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 798              'spr': 1,
 799              'div': 1,
 800              'mul': 1,
 801              'shiftrot': 1
 802             }
 803     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 804                          imem_ifacetype='bare_wb',
 805                          addr_wid=48,
 806                          mask_wid=8,
 807                          reg_wid=64,
 808                          units=units)
 809     dut = TestIssuer(pspec)
 810     vl = main(dut, ports=dut.ports(), name="test_issuer")
 811
 812     if len(sys.argv) == 1:
 813         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 814         with open("test_issuer.il", "w") as f:
 815             f.write(vl)