b5799ecf1bc7af30f8f41b8a155f4138fa5bd1ef
1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc
.simple
.test
.test_runner
import TestRunner
21 # test with ALU data and Logical data
22 from openpower
.test
.alu
.alu_cases
import ALUTestCase
23 from openpower
.test
.general
.overlap_hazards
import HazardTestCase
24 from openpower
.test
.div
.div_cases
import DivTestCases
25 from openpower
.test
.mul
.mul_cases
import MulTestCases2Arg
26 from openpower
.test
.logical
.logical_cases
import LogicalTestCase
27 from openpower
.test
.shift_rot
.shift_rot_cases
import ShiftRotTestCase
28 from openpower
.test
.shift_rot
.shift_rot_cases2
import ShiftRotTestCase2
29 from openpower
.test
.cr
.cr_cases
import CRTestCase
30 from openpower
.test
.branch
.branch_cases
import BranchTestCase
31 from soc
.fu
.spr
.test
.test_pipe_caller
import SPRTestCase
32 from openpower
.test
.ldst
.ldst_cases
import LDSTTestCase
33 from openpower
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
34 from openpower
.simulator
.test_helloworld_sim
import HelloTestCases
37 if __name__
== "__main__":
39 if len(sys
.argv
) > 1 and sys
.argv
[1] == 'nosvp64':
45 if len(sys
.argv
) >= 2 and sys
.argv
[1] == '--allow-overlap':
49 # use in-order issuer, instead of the original FSM based one
51 if len(sys
.argv
) >= 2 and sys
.argv
[1] == '--inorder':
55 # allow list of testing to be selected by command-line
57 for i
in reversed(range(1, len(sys
.argv
))):
58 if not sys
.argv
[i
].startswith('-'):
59 testing
.append(sys
.argv
.pop(i
))
62 testing
= ['general', 'ldst', 'cr', 'shiftrot', 'shiftrot2',
64 'branch', 'div', 'mul', 'hazard']
66 print("SVP64 test mode enabled", svp64
, "overlap",
67 allow_overlap
, "in-order", inorder
, "testing", testing
)
69 unittest
.main(exit
=False)
70 suite
= unittest
.TestSuite()
72 # dictionary of data for tests
73 tests
= {'hello': HelloTestCases
.test_data
,
74 'div': DivTestCases().test_data
,
75 'mul': MulTestCases2Arg().test_data
,
76 'attn': AttnTestCase
.test_data
,
77 'general': GeneralTestCases
.test_data
,
78 'ldst': LDSTTestCase().test_data
,
79 'cr': CRTestCase().test_data
,
80 'shiftrot': ShiftRotTestCase().test_data
,
81 'shiftrot2': ShiftRotTestCase2().test_data
,
82 'logical': LogicalTestCase().test_data
,
83 'hazard': HazardTestCase().test_data
,
84 'alu': ALUTestCase().test_data
,
85 'branch': BranchTestCase().test_data
,
86 'spr': SPRTestCase().test_data
89 # walk through all tests, those requested get added
90 for tname
, data
in tests
.items():
92 suite
.addTest(TestRunner(data
, svp64
=svp64
, inorder
=inorder
,
93 allow_overlap
=allow_overlap
))
95 runner
= unittest
.TextTestRunner()