1 from openpower
.simulator
.program
import Program
2 from openpower
.test
.common
import TestCase
6 from nmigen
import Module
, Signal
7 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
8 from nmutil
.formaltest
import FHDLTestCase
10 from soc
.simple
.issuer
import TestIssuer
11 from openpower
.endian
import bigendian
14 from soc
.config
.test
.test_loadstore
import TestMemPspec
15 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
18 from soc
.fu
.compunits
.test
.test_compunit
import (check_sim_memory
,
21 from soc
.simple
.test
.test_runner
import setup_i_memory
24 sys
.setrecursionlimit(10**6)
27 class BinaryTestCase(FHDLTestCase
):
30 def __init__(self
, name
="general"):
31 super().__init
__(name
)
34 @unittest.skip("a bit big")
35 def test_binary(self
):
36 with
Program("1.bin", bigendian
) as program
:
37 self
.run_tst_program(program
)
39 def test_binary(self
):
40 with
Program("hello_world.bin", bigendian
) as program
:
41 self
.run_tst_program(program
)
43 def run_tst_program(self
, prog
):
44 initial_regs
= [0] * 32
45 tc
= TestCase(prog
, self
.test_name
, initial_regs
, None, 0,
48 self
.test_data
.append(tc
)
51 class TestRunner(FHDLTestCase
):
52 def __init__(self
, tst_data
):
53 super().__init
__("binary_runner")
54 self
.test_data
= tst_data
56 def binary_runner(self
):
63 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
64 imem_ifacetype
='test_bare_wb',
68 imem_test_depth
=32768,
69 dmem_test_depth
=32768)
70 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
71 imem
= issuer
.imem
._get
_memory
()
73 pdecode2
= core
.pdecode2
76 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
77 comb
+= issuer
.pc_i
.ok
.eq(pc_i_ok
)
78 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
86 for test
in self
.test_data
:
89 yield core
.bigendian_i
.eq(bigendian
)
90 yield core
.core_start_i
.eq(1)
92 yield core
.core_start_i
.eq(0)
96 program
= test
.program
97 self
.subTest(test
.name
)
98 print("regs", test
.regs
)
99 print("sprs", test
.sprs
)
101 print("mem", test
.mem
)
102 print("msr", test
.msr
)
103 print("assem", program
.assembly
)
104 instructions
= list(program
.generate_instructions())
106 print("instructions", len(instructions
))
108 pc
= 0 # start of memory
110 yield from setup_i_memory(imem
, pc
, instructions
)
111 # blech! put the same listing into the data memory
112 data_mem
= get_l0_mem(l0
)
113 yield from setup_i_memory(data_mem
, pc
, instructions
)
114 yield from setup_regs(core
, test
)
121 # start the instruction
122 yield go_insn_i
.eq(1)
124 yield pc_i_ok
.eq(0) # don't change PC from now on
125 yield go_insn_i
.eq(0) # and don't issue a new insn
126 yield from wait_for_busy_hi(core
)
129 # wait until executed
130 ins
= yield core
.raw_opcode_i
131 pc
= yield issuer
.pc_o
132 print("instruction: 0x%x @ %x" % (ins
& 0xffffffff, pc
))
133 yield from wait_for_busy_clear(core
)
135 terminated
= yield core
.core_terminated_o
136 print("terminated", terminated
)
138 terminated
= yield core
.core_terminated_o
143 # yield from check_regs(self, sim, core, test, code)
146 # yield from check_sim_memory(self, l0, sim, code)
148 sim
.add_sync_process(process
)
149 with sim
.write_vcd("binary_issuer_simulator.vcd",
154 if __name__
== "__main__":
155 unittest
.main(exit
=False)
156 suite
= unittest
.TestSuite()
157 suite
.addTest(TestRunner(BinaryTestCase
.test_data
))
159 runner
= unittest
.TextTestRunner()