95650babfa8817f0e6f7e78060c62bf7674d4701
3 This module implements the creation, inspection and comparison
4 of test states for TestIssuer HDL
8 from openpower
.decoder
.power_enums
import XER_bits
9 from openpower
.util
import log
10 from openpower
.test
.state
import (State
, state_add
, state_factory
,
12 from soc
.fu
.compunits
.test
.test_compunit
import get_l0_mem
14 class HDLState(State
):
15 """HDLState: Obtains registers and memory from an nmigen simulator
16 object by implementing State class methods.
18 def __init__(self
, core
):
22 def get_intregs(self
):
25 if self
.core
.regs
.int.unary
:
26 rval
= yield self
.core
.regs
.int.regs
[i
].reg
28 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
29 self
.intregs
.append(rval
)
30 log("class hdl int regs", list(map(hex, self
.intregs
)))
35 rval
= yield self
.core
.regs
.cr
.regs
[7-i
].reg
36 self
.crregs
.append(rval
)
37 log("class hdl cr regs", list(map(hex, self
.crregs
)))
41 self
.xr
= self
.core
.regs
.xer
42 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
43 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
44 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
45 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
46 log("class hdl xregs", list(map(hex, self
.xregs
)))
50 self
.state
= self
.core
.regs
.state
51 # relies on the state.r_port being permanently held as PC
52 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
53 self
.pcl
.append(self
.pc
)
54 log("class hdl pc", hex(self
.pc
))
58 # get the underlying HDL-simulated memory from the L0CacheBuffer
59 if hasattr(self
.core
, "icache"):
60 # err temporarily ignore memory
61 return # XXX have to work out how to deal with wb_get
62 hdlmem
= get_l0_mem(self
.core
.l0
)
63 for i
in range(hdlmem
.depth
):
64 value
= yield hdlmem
._array
[i
] # should not really do this
68 # add to State Factory
69 state_add('hdl', HDLState
)