1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4 """SVP64 RM (Remap) Record.
6 https://libre-soc.org/openpower/sv/svp64/
8 | Field Name | Field bits | Description |
9 |-------------|------------|----------------------------------------|
10 | MASKMODE | `0` | Execution (predication) Mask Kind |
11 | MASK | `1:3` | Execution Mask |
12 | ELWIDTH | `4:5` | Element Width |
13 | ELWIDTH_SRC | `6:7` | Element Width for Source |
14 | SUBVL | `8:9` | Sub-vector length |
15 | EXTRA | `10:18` | context-dependent extra |
16 | MODE | `19:23` | changes Vector behaviour |
19 from nmigen
import Record
21 # in nMigen, Record begins at the LSB and fills upwards
22 class SVP64Rec(Record
):
23 def __init__(self
, name
=None):
24 Record
.__init
__(self
, layout
=[("mode" , 5),
30 ("mmode" , 1)], name
=name
)
33 return [self
.mmode
, self
.mask
, self
.elwidth
, self
.ewsrc
,
34 self
.extra
, self
.mode
]