1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 """SVP64 OpenPOWER v3.0B assembly translator
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
18 from collections
import OrderedDict
20 from soc
.decoder
.pseudo
.pagereader
import ISA
21 from soc
.decoder
.power_enums
import get_csv
, find_wiki_dir
24 # identifies register by type
25 def is_CR_3bit(regname
):
26 return regname
in ['BF', 'BFA']
28 def is_CR_5bit(regname
):
29 return regname
in ['BA', 'BB', 'BC', 'BI', 'BT']
32 return regname
in ['RA', 'RB', 'RC', 'RS', 'RT']
34 def get_regtype(regname
):
35 if is_CR_3bit(regname
):
37 if is_CR_5bit(regname
):
42 # decode GPR into sv extra
43 def get_extra_gpr(etype
, regmode
, field
):
44 if regmode
== 'scalar':
45 # cut into 2-bits 5-bits SS FFFFF
47 field
= field
& 0b11111
49 # cut into 5-bits 2-bits FFFFF SS
50 sv_extra
= field
& 0b11
52 return sv_extra
, field
55 # decode 3-bit CR into sv extra
56 def get_extra_cr_3bit(etype
, regmode
, field
):
57 if regmode
== 'scalar':
58 # cut into 2-bits 3-bits SS FFF
62 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
63 sv_extra
= field
& 0b1111
65 return sv_extra
, field
69 def decode_subvl(encoding
):
70 pmap
= {'2': 0b01, '3': 0b10, '4': 0b11}
71 assert encoding
in pmap
, \
72 "encoding %s for SUBVL not recognised" % encoding
77 def decode_elwidth(encoding
):
78 pmap
= {'8': 0b11, '16': 0b10, '32': 0b01}
79 assert encoding
in pmap
, \
80 "encoding %s for elwidth not recognised" % encoding
84 # decodes predicate register encoding
85 def decode_predicate(encoding
):
96 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
98 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
101 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
102 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
104 assert encoding
in pmap
, \
105 "encoding %s for predicate not recognised" % encoding
106 return pmap
[encoding
]
109 # decodes "Mode" in similar way to BO field (supposed to, anyway)
110 def decode_bo(encoding
):
111 pmap
= { # TODO: double-check that these are the same as Branch BO
113 'nl' : 0b001, 'ge' : 0b001, # same value
115 'ng' : 0b011, 'le' : 0b011, # same value
118 'so' : 0b110, 'un' : 0b110, # same value
119 'ns' : 0b111, 'nu' : 0b111, # same value
121 assert encoding
in pmap
, \
122 "encoding %s for BO Mode not recognised" % encoding
123 return pmap
[encoding
]
125 # partial-decode fail-first mode
126 def decode_ffirst(encoding
):
127 if encoding
in ['RC1', '~RC1']:
129 return decode_bo(encoding
)
132 # gets SVP64 ReMap information
136 pth
= find_wiki_dir()
137 for fname
in os
.listdir(pth
):
138 if fname
.startswith("RM"):
139 for entry
in get_csv(fname
):
140 self
.instrs
[entry
['insn']] = entry
143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
145 def __init__(self
, lst
):
147 self
.trans
= self
.translate(lst
)
150 for insn
in self
.trans
:
153 def translate(self
, lst
):
154 isa
= ISA() # reads the v3.0B pseudo-code markdown files
155 svp64
= SVP64RM() # reads the svp64 Remap entries for registers
158 # find first space, to get opcode
161 # now find opcode fields
162 fields
= ''.join(ls
[1:]).split(',')
163 fields
= list(map(str.strip
, fields
))
164 print ("opcode, fields", ls
, opcode
, fields
)
166 # identify if is a svp64 mnemonic
167 if not opcode
.startswith('sv.'):
168 res
.append(insn
) # unaltered
170 opcode
= opcode
[3:] # strip leading "sv."
172 # start working on decoding the svp64 op: sv.baseop/vec2.mode
173 opcode
= opcode
.split("/") # split at "/"
174 v30b_op
= opcode
[0] # first is the v3.0B
176 opmodes
= [] # no sv modes
178 opmodes
= opcode
[1].split(".") # second splits by dots
180 # check instruction ends with dot
181 rc_mode
= v30b_op
.endswith('.')
183 v30b_op
= v30b_op
[:-1]
185 if v30b_op
not in isa
.instr
:
186 raise Exception("opcode %s of '%s' not supported" % \
188 if v30b_op
not in svp64
.instrs
:
189 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
191 isa
.instr
[v30b_op
].regs
[0]
192 v30b_regs
= isa
.instr
[v30b_op
].regs
[0]
193 rm
= svp64
.instrs
[v30b_op
]
194 print ("v3.0B op", v30b_op
, "Rc=1" if rc_mode
else '')
195 print ("v3.0B regs", opcode
, v30b_regs
)
198 # right. the first thing to do is identify the ordering of
199 # the registers, by name. the EXTRA2/3 ordering is in
200 # rm['0']..rm['3'] but those fields contain the names RA, BB
201 # etc. we have to read the pseudocode to understand which
202 # reg is which in our instruction. sigh.
204 # first turn the svp64 rm into a "by name" dict, recording
205 # which position in the RM EXTRA it goes into
206 # also: record if the src or dest was a CR, for sanity-checking
207 # (elwidth overrides on CRs are banned)
208 dest_reg_cr
, src_reg_cr
= False, False
209 svp64_reg_byname
= {}
212 if not rfield
or rfield
== '0':
214 print ("EXTRA field", i
, rfield
)
215 rfield
= rfield
.split(";") # s:RA;d:CR1 etc.
218 r
= r
[2:] # ignore s: and d:
219 svp64_reg_byname
[r
] = i
# this reg in EXTRA position 0-3
220 # check the regtype (if CR, record that)
221 regtype
= get_regtype(r
)
222 if regtype
in ['CR_3bit', 'CR_5bit']:
228 print ("EXTRA field index, by regname", svp64_reg_byname
)
230 # okaaay now we identify the field value (opcode N,N,N) with
231 # the pseudo-code info (opcode RT, RA, RB)
232 opregfields
= zip(fields
, v30b_regs
) # err that was easy
234 # now for each of those find its place in the EXTRA encoding
235 extras
= OrderedDict()
236 for idx
, (field
, regname
) in enumerate(opregfields
):
237 extra
= svp64_reg_byname
.get(regname
, None)
238 regtype
= get_regtype(regname
)
239 extras
[extra
] = (idx
, field
, regname
, regtype
)
240 print (" ", extra
, extras
[extra
])
242 # great! got the extra fields in their associated positions:
243 # also we know the register type. now to create the EXTRA encodings
244 etype
= rm
['Etype'] # Extra type: EXTRA3/EXTRA2
245 ptype
= rm
['Ptype'] # Predication type: Twin / Single
248 for extra_idx
, (idx
, field
, regname
, regtype
) in extras
.items():
249 # is it a field we don't alter/examine? if so just put it
252 v30b_newfields
.append(field
)
254 # first, decode the field number. "5.v" or "3.s" or "9"
255 field
= field
.split(".")
256 regmode
= 'scalar' # default
260 elif field
[1] == 'v':
262 field
= int(field
[0]) # actual register number
263 print (" ", regmode
, field
, end
=" ")
265 # XXX TODO: the following is a bit of a laborious repeated
266 # mess, which could (and should) easily be parameterised.
268 # encode SV-GPR field into extra, v3.0field
270 sv_extra
, field
= get_extra_gpr(etype
, regmode
, field
)
271 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
272 # (and shrink to a single bit if ok)
273 if etype
== 'EXTRA2':
274 if regmode
== 'scalar':
275 # range is r0-r63 in increments of 1
276 assert (sv_extra
>> 1) == 0, \
277 "scalar GPR %s cannot fit into EXTRA2 %s" % \
278 (regname
, str(extras
[extra_idx
]))
279 # all good: encode as scalar
280 sv_extra
= sv_extra
& 0b01
282 # range is r0-r127 in increments of 4
283 assert sv_extra
& 0b01 == 0, \
284 "vector field %s cannot fit into EXTRA2 %s" % \
285 (regname
, str(extras
[extra_idx
]))
286 # all good: encode as vector (bit 2 set)
287 sv_extra
= 0b10 |
(sv_extra
>> 1)
288 elif regmode
== 'vector':
289 # EXTRA3 vector bit needs marking
292 # encode SV-CR 3-bit field into extra, v3.0field
293 elif regtype
== 'CR_3bit':
294 sv_extra
, field
= get_extra_cr_3bit(etype
, regmode
, field
)
295 # now sanity-check (and shrink afterwards)
296 if etype
== 'EXTRA2':
297 if regmode
== 'scalar':
298 # range is CR0-CR15 in increments of 1
299 assert (sv_extra
>> 1) == 0, \
300 "scalar CR %s cannot fit into EXTRA2 %s" % \
301 (regname
, str(extras
[extra_idx
]))
302 # all good: encode as scalar
303 sv_extra
= sv_extra
& 0b01
305 # range is CR0-CR127 in increments of 16
306 assert sv_extra
& 0b111 == 0, \
307 "vector CR %s cannot fit into EXTRA2 %s" % \
308 (regname
, str(extras
[extra_idx
]))
309 # all good: encode as vector (bit 2 set)
310 sv_extra
= 0b10 |
(sv_extra
>> 3)
312 if regmode
== 'scalar':
313 # range is CR0-CR31 in increments of 1
314 assert (sv_extra
>> 2) == 0, \
315 "scalar CR %s cannot fit into EXTRA2 %s" % \
316 (regname
, str(extras
[extra_idx
]))
317 # all good: encode as scalar
318 sv_extra
= sv_extra
& 0b11
320 # range is CR0-CR127 in increments of 8
321 assert sv_extra
& 0b11 == 0, \
322 "vector CR %s cannot fit into EXTRA2 %s" % \
323 (regname
, str(extras
[extra_idx
]))
324 # all good: encode as vector (bit 3 set)
325 sv_extra
= 0b100 |
(sv_extra
>> 2)
327 # encode SV-CR 5-bit field into extra, v3.0field
328 # *sigh* this is the same as 3-bit except the 2 LSBs are
330 elif regtype
== 'CR_5bit':
331 cr_subfield
= field
& 0b11
332 field
= field
>> 2 # strip bottom 2 bits
333 sv_extra
, field
= get_extra_cr_3bit(etype
, regmode
, field
)
334 # now sanity-check (and shrink afterwards)
335 if etype
== 'EXTRA2':
336 if regmode
== 'scalar':
337 # range is CR0-CR15 in increments of 1
338 assert (sv_extra
>> 1) == 0, \
339 "scalar CR %s cannot fit into EXTRA2 %s" % \
340 (regname
, str(extras
[extra_idx
]))
341 # all good: encode as scalar
342 sv_extra
= sv_extra
& 0b01
344 # range is CR0-CR127 in increments of 16
345 assert sv_extra
& 0b111 == 0, \
346 "vector CR %s cannot fit into EXTRA2 %s" % \
347 (regname
, str(extras
[extra_idx
]))
348 # all good: encode as vector (bit 2 set)
349 sv_extra
= 0b10 |
(sv_extra
>> 3)
351 if regmode
== 'scalar':
352 # range is CR0-CR31 in increments of 1
353 assert (sv_extra
>> 2) == 0, \
354 "scalar CR %s cannot fit into EXTRA2 %s" % \
355 (regname
, str(extras
[extra_idx
]))
356 # all good: encode as scalar
357 sv_extra
= sv_extra
& 0b11
359 # range is CR0-CR127 in increments of 8
360 assert sv_extra
& 0b11 == 0, \
361 "vector CR %s cannot fit into EXTRA2 %s" % \
362 (regname
, str(extras
[extra_idx
]))
363 # all good: encode as vector (bit 3 set)
364 sv_extra
= 0b100 |
(sv_extra
>> 2)
366 # reconstruct the actual 5-bit CR field
367 field
= (field
<< 2) | cr_subfield
369 # capture the extra field info
370 print ("=>", "%5s" % bin(sv_extra
), field
)
371 extras
[extra_idx
] = sv_extra
373 # append altered field value to v3.0b
374 v30b_newfields
.append(str(field
))
376 print ("new v3.0B fields", v30b_op
, v30b_newfields
)
377 print ("extras", extras
)
379 # rright. now we have all the info. start creating SVP64 RM
382 # begin with EXTRA fields
383 for idx
, sv_extra
in extras
.items():
384 if idx
is None: continue
385 # start at bit 10, work up 2/3 times EXTRA idx
386 offs
= 2 if etype
== 'EXTRA2' else 3 # 2 or 3 bits
387 svp64_rm |
= sv_extra
<< (10+idx
*offs
)
392 destwid
= 0 # bits 4-5
393 srcwid
= 0 # bits 6-7
395 smask
= 0 # bits 16-18 but only for twin-predication
396 mode
= 0 # bits 19-23
407 mapreduce_crm
= False
408 mapreduce_svm
= False
413 # ok let's start identifying opcode augmentation fields
414 for encmode
in opmodes
:
415 # predicate mask (dest)
416 if encmode
.startswith("m="):
418 pmmode
, pmask
= decode_predicate(encmode
[2:])
421 # predicate mask (src, twin-pred)
422 elif encmode
.startswith("sm="):
424 smmode
, smask
= decode_predicate(encmode
[3:])
428 elif encmode
.startswith("vec"):
429 subvl
= decode_subvl(encmode
[3:])
431 elif encmode
.startswith("ew="):
432 destwid
= decode_elwidth(encmode
[3:])
433 elif encmode
.startswith("sw="):
434 srcwid
= decode_elwidth(encmode
[3:])
436 elif encmode
== 'sats':
437 assert sv_mode
is None
440 elif encmode
== 'satu':
441 assert sv_mode
is None
445 elif encmode
== 'sz':
447 elif encmode
== 'dz':
450 elif encmode
.startswith("ff="):
451 assert sv_mode
is None
453 failfirst
= decode_ffirst(encmode
[3:])
454 # predicate-result, interestingly same as fail-first
455 elif encmode
.startswith("pr="):
456 assert sv_mode
is None
458 predresult
= decode_ffirst(encmode
[3:])
460 elif encmode
== 'mr':
461 assert sv_mode
is None
464 elif encmode
== 'crm': # CR on map-reduce
465 assert sv_mode
is None
468 elif encmode
== 'svm': # sub-vector mode
471 # construct the mode field, doing sanity-checking along the way
474 assert sv_mode
== 0b00, "sub-vector mode in mapreduce only"
475 assert subvl
!= 0, "sub-vector mode not possible on SUBVL=1"
479 mode |
= (src_zero
<< 3) |
(dst_zero
<< 4) # predicate zeroing
482 elif sv_mode
== 0b00:
483 mode |
= (0b1<<2) # sets mapreduce
484 assert dst_zero
== 0, "dest-zero not allowed in mapreduce mode"
486 mode |
= (0b1<<4) # sets CRM mode
487 assert rc_mode
, "CRM only allowed when Rc=1"
488 # bit of weird encoding to jam zero-pred or SVM mode in.
489 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
491 mode |
= (src_zero
<< 3) # predicate src-zeroing
493 mode |
= (1 << 3) # SVM mode
496 elif sv_mode
== 0b01:
497 assert dst_zero
== 0, "dest-zero not allowed in failfirst mode"
498 mode |
= 0b01 # sets failfirst
499 if failfirst
== 'RC1':
500 mode |
= (0b1<<4) # sets RC1 mode
501 mode |
= (src_zero
<< 3) # predicate src-zeroing
502 assert rc_mode
==False, "ffirst RC1 only possible when Rc=0"
503 elif failfirst
== '~RC1':
504 mode |
= (0b1<<4) # sets RC1 mode...
505 mode |
= (src_zero
<< 3) # predicate src-zeroing
506 mode |
= (0b1<<2) # ... with inversion
507 assert rc_mode
==False, "ffirst RC1 only possible when Rc=0"
509 assert src_zero
== 0, "src-zero not allowed in ffirst BO"
510 assert rc_mode
, "ffirst BO only possible when Rc=1"
511 mode |
= (failfirst
<< 2) # set BO
514 elif sv_mode
== 0b10:
515 mode |
= 0b10 # sets saturation mode
516 mode |
= (src_zero
<< 3) |
(dst_zero
<< 4) # predicate zeroing
517 mode |
= (saturation
<<2) # sets signed/unsigned saturation
519 # sanity-check that 2Pred mask is same mode
520 if has_pmask
and has_smask
:
521 assert smmode
== pmmode
, \
522 "predicate masks %s and %s must be same reg type" % \
525 # sanity-check that twin-predication mask only specified in 2P mode
527 assert has_smask
== False, \
528 "source-mask can only be specified on Twin-predicate ops"
530 # put in predicate masks into svp64_rm
532 svp64_rm |
= (smask
<< 16) # source pred: bits 16-18
533 svp64_rm |
= (mmode
) # mask mode: bit 0
534 svp64_rm |
= (pmask
<< 1) # 1-pred: bits 1-3
537 svp64_rm
+= (subvl
<< 8) # subvl: bits 8-9
540 svp64_rm
+= (srcwid
<< 6) # srcwid: bits 6-7
541 svp64_rm
+= (destwid
<< 4) # destwid: bits 4-5
543 # nice debug printout. (and now for something completely different)
544 # https://youtu.be/u0WOIwlXE9g?t=146
545 print ("svp64_rm", hex(svp64_rm
), bin(svp64_rm
))
546 print (" mmode 0 :", bin(mmode
))
547 print (" pmask 1-3 :", bin(pmask
))
548 print (" dstwid 4-5 :", bin(destwid
))
549 print (" srcwid 6-7 :", bin(srcwid
))
550 print (" subvl 8-9 :", bin(subvl
))
551 print (" mode 19-23:", bin(mode
))
552 offs
= 2 if etype
== 'EXTRA2' else 3 # 2 or 3 bits
553 for idx
, sv_extra
in extras
.items():
554 if idx
is None: continue
555 start
= (10+idx
*offs
)
557 print (" extra%d %2d-%2d:" % (idx
, start
, end
),
560 print (" smask 16-17:", bin(smask
))
565 if __name__
== '__main__':
566 isa
= SVP64(['slw 3, 1, 4',
569 'sv.cmpi 5, 1, 3, 2',
571 'sv.isel 64.v, 3, 2, 65.v',
572 'sv.setb/m=r3.sm=1<<r3 5, 31',
573 'sv.setb/vec2 5, 31',
574 'sv.setb/sw=8.ew=16 5, 31',
575 'sv.extsw./ff=eq 5, 31',
576 'sv.extsw./satu.sz.dz 5, 31',