3 from copy
import deepcopy
11 def __contains__(self
, k
):
17 def add_spec(self
, k
, v
):
20 def update(self
, pinidx
, v
):
21 if pinidx
not in self
.pins
:
24 self
.pins
[pinidx
].update(v
)
27 return self
.pins
.keys()
30 return self
.pins
.items()
38 def __delitem__(self
, k
):
41 def __getitem__(self
, k
):
47 def __init__(self
, fname
, pingroup
, bankspec
, suffix
, offs
, bank
, mux
,
48 spec
=None, limit
=None, origsuffix
=None):
50 # function type can be in, out or inout, represented by - + *
51 # strip function type out of each pin name
53 for i
in range(len(pingroup
)):
58 if fntype
not in '+-*':
61 fntype
= {'-': 'in', '+': 'out', '*': 'inout'}[fntype
]
62 self
.fntype
[pname
] = fntype
66 self
.pingroup
= pingroup
67 self
.bankspec
= bankspec
69 self
.origsuffix
= origsuffix
or suffix
73 # create consistent name suffixes
74 pingroup
= namesuffix(fname
, suffix
, pingroup
)
80 for name
in pingroup
[:limit
]:
82 name_
= "%s_%s" % (name
, suffix
)
85 if spec
and name
in spec
:
87 pin
= {mux
: (name_
, bank
)}
88 offs_bank
, offs_
= offs
91 idx_
+= bankspec
[bank
]
96 name_
= "%s_%s" % (name
, suffix
)
103 idx_
, mux_
, bank_
= spec
[name
]
105 pin
= {mux_
: (name_
, bank_
)}
107 res
[idx_
].update(pin
)
114 def i2s(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
115 i2spins
= ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
117 # i2spins.append("DO%d+" % i)
118 return Pins('IIS', i2spins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
122 def emmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
123 emmcpins
= ['CMD+', 'CLK+']
125 emmcpins
.append("D%d*" % i
)
126 return Pins('MMC', emmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
130 def sdmmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None,
131 start
=None, limit
=None):
132 sdmmcpins
= ['CMD+', 'CLK+']
134 sdmmcpins
.append("D%d*" % i
)
135 sdmmcpins
= sdmmcpins
[start
:limit
]
136 return Pins('SD', sdmmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
140 def spi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
141 spipins
= ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
142 return Pins('SPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
146 def quadspi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
147 spipins
= ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
161 def i2c(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
162 spipins
= ['SDA*', 'SCL*']
163 return Pins('TWI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
167 def jtag(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
168 jtagpins
= ['MS+', 'DI-', 'DO+', 'CK+']
169 return Pins('JTAG', jtagpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
173 def uart(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
174 uartpins
= ['TX+', 'RX-']
175 return Pins('UART', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
179 def namesuffix(name
, suffix
, namelist
):
183 names
.append("%s%s_%s" % (name
, suffix
, n
))
185 names
.append("%s_%s" % (name
, suffix
))
189 def ulpi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
190 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
192 ulpipins
.append('D%d*' % i
)
193 return Pins('ULPI', ulpipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
197 def uartfull(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
198 uartpins
= ['TX+', 'RX-', 'CTS-', 'RTS+']
199 return Pins('UARTQ', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
203 def rgbttl(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
204 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
206 ttlpins
.append("D%d+" % i
)
207 return Pins('LCD', ttlpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
211 def rgmii(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
214 buspins
.append("ERXD%d-" % i
)
216 buspins
.append("ETXD%d+" % i
)
217 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
219 'ETXEN+', 'ETXCK+', 'ECRS-',
221 return Pins('RG', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
225 def flexbus1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
228 buspins
.append("AD%d*" % i
)
230 buspins
.append("CS%d+" % i
)
231 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
232 'A0', 'A1', 'TS', 'TBST',
235 buspins
.append("BWE%d" % i
)
236 for i
in range(2, 6):
237 buspins
.append("CS%d+" % i
)
238 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
242 def flexbus2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
244 for i
in range(8, 32):
245 buspins
.append("AD%d*" % i
)
246 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
250 def sdram1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
253 buspins
.append("SDRDQM%d*" % i
)
255 buspins
.append("SDRAD%d+" % i
)
257 buspins
.append("SDRDQ%d+" % i
)
259 buspins
.append("SDRCS%d#+" % i
)
261 buspins
.append("SDRDQ%d+" % i
)
263 buspins
.append("SDRBA%d+" % i
)
264 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
266 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
270 def sdram2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
272 for i
in range(3, 6):
273 buspins
.append("SDRCS%d#+" % i
)
274 for i
in range(8, 32):
275 buspins
.append("SDRDQ%d*" % i
)
276 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
280 def mcu8080(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
283 buspins
.append("MCUD%d*" % i
)
285 buspins
.append("MCUAD%d+" % (i
+ 8))
287 buspins
.append("MCUCS%d+" % i
)
289 buspins
.append("MCUNRB%d+" % i
)
290 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
292 return Pins('MCU', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
296 def _pinbank(bankspec
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1,
299 for i
in range(gpiooffs
, gpiooffs
+ gpionum
):
300 gpiopins
.append("%s%d*" % (bank
, i
))
301 return Pins(prefix
, gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
305 def eint(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
307 for i
in range(gpiooffs
, gpiooffs
+ gpionum
):
308 gpiopins
.append("%d*" % (i
))
309 return Pins('EINT', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
313 def pwm(bankspec
, suffix
, offs
, bank
, pwmoffs
, pwmnum
=1, mux
=1, spec
=None):
315 for i
in range(pwmoffs
, pwmoffs
+ pwmnum
):
316 pwmpins
.append("%d+" % (i
))
317 return Pins('PWM', pwmpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
321 def gpio(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
322 return _pinbank(bankspec
, "GPIO%s" % bank
, suffix
, offs
, bank
, gpiooffs
,
323 gpionum
, mux
=0, spec
=None)
326 def pinmerge(pins
, fn
):
327 # hack, store the function specs in the pins dict
329 suffix
= fn
.origsuffix
332 if not hasattr(pins
, 'fnspec'):
336 assert 'EINT' not in pins
337 if fname
not in pins
.fnspec
:
338 pins
.add_spec(fname
, {})
339 print "fname bank suffix", fname
, bank
, suffix
340 if suffix
or fname
== 'EINT' or fname
== 'PWM':
341 specname
= fname
+ suffix
343 specname
= fname
+ bank
344 if specname
in pins
.fnspec
[fname
]:
345 # ok so some declarations may bring in different
346 # names at different stages (EINT, PWM, flexbus1/2)
347 # so we have to merge the names in. main thing is
349 tomerge
= pins
.fnspec
[fname
][specname
]
350 for p
in fn
.pingroup
:
351 if p
not in tomerge
.pingroup
:
352 tomerge
.pingroup
.append(p
)
353 tomerge
.pins
.update(fn
.pins
)
354 tomerge
.fntype
.update(fn
.fntype
)
356 pins
.fnspec
[fname
][specname
] = deepcopy(fn
)
359 for (pinidx
, v
) in fn
.pins
.items():
360 pins
.update(pinidx
, v
)