1 from UserDict
import UserDict
5 """ a wire which can be hi, lo or tri-state
8 def __init__(self
, wires
, name
):
10 self
.wires
[name
] = self
15 class TestPin(object):
16 """ a test pin can be an output, input or in-out
17 and it stores the state in an associated wire
21 class Wires(UserDict
):
26 UserDict
.__init
__(self
)
29 def dummytest(ps
, output_dir
, output_type
):
30 print ps
, output_dir
, output_type
34 # basically we need to replicate the entirety of the
35 # verilog module's inputs and outputs, so that we can
36 # set inputs hi/lo and then test expected outputs hi/lo.
37 # so, set up some wires by going through the interfaces