1 # Simple tests for an pinmux module
3 from cocotb
.triggers
import Timer
4 from cocotb
.result
import TestFailure
5 #from pinmux_model import pinmux_model
9 """ dut is design under test """
12 for gpio2, there are three ports at peripheral side:
13 peripheral_side_gpioa_a2_out_in
14 peripheral_side_gpioa_a2_outen_in
15 peripheral_side_gpioa_a2_in
18 def pinmux_gpio2(dut
):
21 # mux selection lines, each input two bit wide
22 dut
.mux_lines_cell2_mux_in
= 0
24 # enable input for mux
25 dut
.EN_mux_lines_cell0_mux
= 0
26 dut
.EN_mux_lines_cell1_mux
= 0
27 dut
.EN_mux_lines_cell2_mux
= 1
32 # GPIO is inout peripheral
33 dut
.peripheral_side_gpioa_a2_out_in
= 0
34 dut
.peripheral_side_gpioa_a2_outen_in
= 1
38 if dut
.iocell_side_io2_cell_out
!= 0: # output of iopad
40 "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
41 str(dut
.iocell_side_io2_cell_out
))
43 dut
.peripheral_side_gpioa_a2_out_in
= 1
47 if dut
.iocell_side_io2_cell_out
!= 1:
49 "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
50 str(dut
.iocell_side_io2_cell_out
))
52 # GPIO2-in test (first see if it's tri-state)
54 if str(dut
.peripheral_side_gpioa_a2_in
) != "x":
56 "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
57 str(dut
.peripheral_side_gpioa_a2_in
))
59 dut
.peripheral_side_gpioa_a2_outen_in
= 0
60 dut
.iocell_side_io2_cell_in_in
= 0
63 if dut
.peripheral_side_gpioa_a2_in
!= 0:
65 "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
66 str(dut
.peripheral_side_gpioa_a2_in
))
68 dut
.iocell_side_io2_cell_in_in
= 1
71 if dut
.peripheral_side_gpioa_a2_in
!= 1:
73 "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
74 str(dut
.peripheral_side_gpioa_a2_in
))
76 dut
.peripheral_side_gpioa_a2_outen_in
= 1
77 dut
.iocell_side_io2_cell_in_in
= 0
79 dut
._log
.info("gpioa_a2_in %s" % dut
.peripheral_side_gpioa_a2_in
)
81 if dut
.iocell_side_io2_cell_out
!= 1:
83 "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
84 str(dut
.iocell_side_io2_cell_out
))
86 dut
._log
.info("Ok!, gpio2 passed")
92 # mux selection lines, each input two bit wide
93 dut
.mux_lines_cell0_mux_in
= 1
95 # enable input for mux
96 dut
.EN_mux_lines_cell0_mux
= 1
97 dut
.EN_mux_lines_cell1_mux
= 0
98 dut
.EN_mux_lines_cell2_mux
= 0
104 dut
.peripheral_side_uart_tx_in
= 1
105 dut
.peripheral_side_gpioa_a0_outen_in
= 1
109 if dut
.iocell_side_io0_cell_out
!= 1:
111 "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
112 str(dut
.iocell_side_io0_cell_out
))
114 dut
.peripheral_side_uart_tx_in
= 0
118 if dut
.iocell_side_io0_cell_out
!= 0:
120 "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
121 str(dut
.iocell_side_io0_cell_out
))
123 dut
._log
.info("Ok!, uart passed")
126 def pinmux_twi_scl(dut
):
127 """Test for I2C SCL"""
129 # mux selection lines, each input two bit wide
130 dut
.mux_lines_cell2_mux_in
= 2
132 # enable input for mux
133 dut
.EN_mux_lines_cell0_mux
= 0
134 dut
.EN_mux_lines_cell1_mux
= 0
135 dut
.EN_mux_lines_cell2_mux
= 1
139 # Test for out for twi_scl
140 dut
.peripheral_side_twi_scl_out_in
= 0
141 dut
.peripheral_side_twi_scl_outen_in
= 1
144 if dut
.iocell_side_io2_cell_out
!= 0:
146 "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
147 str(dut
.iocell_side_io2_cell_out
))
149 dut
.peripheral_side_twi_scl_out_in
= 1
152 if dut
.iocell_side_io2_cell_out
!= 1:
154 "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
155 str(dut
.iocell_side_io2_cell_out
))
157 dut
._log
.info("twi_scl_in %s" % dut
.peripheral_side_twi_scl_in
)
160 dut
.peripheral_side_twi_scl_outen_in
= 0
161 dut
.iocell_side_io2_cell_in_in
= 0
164 if dut
.peripheral_side_twi_scl_in
!= 0:
166 "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
167 str(dut
.peripheral_side_twi_scl_in
))
169 dut
.iocell_side_io2_cell_in_in
= 1
172 if dut
.peripheral_side_twi_scl_in
!= 1:
174 "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
175 str(dut
.peripheral_side_twi_scl_in
))
177 dut
.peripheral_side_twi_scl_outen_in
= 1
178 dut
.iocell_side_io2_cell_in_in
= 0
180 dut
._log
.info("twi_scl_in %s" % dut
.peripheral_side_twi_scl_in
)
182 if dut
.iocell_side_io2_cell_out
!= 1:
184 "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
185 str(dut
.iocell_side_io2_cell_out
))
189 dut
._log
.info("Ok!, twi_scl passed")
192 def pinmux_twi_sda(dut
):
195 # mux selection lines, each input two bit wide
196 dut
.mux_lines_cell1_mux_in
= 2
198 # enable input for mux
199 dut
.EN_mux_lines_cell0_mux
= 0
200 dut
.EN_mux_lines_cell1_mux
= 1
201 dut
.EN_mux_lines_cell2_mux
= 0
205 # define input variables
206 dut
.peripheral_side_twi_sda_out_in
= 0
207 dut
.peripheral_side_twi_sda_outen_in
= 1
211 dut
._log
.info("io1_out %s" % dut
.iocell_side_io1_cell_out
)
212 # Test for out for twi_sda
213 if dut
.iocell_side_io1_cell_out
!= 0:
215 "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
216 str(dut
.iocell_side_io1_cell_out
))
218 dut
.peripheral_side_twi_sda_out_in
= 1
221 if dut
.iocell_side_io1_cell_out
!= 1:
223 "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
224 str(dut
.iocell_side_io1_cell_out
))
226 dut
._log
.info("twi_sda_in %s" % dut
.peripheral_side_twi_sda_in
)
229 dut
.peripheral_side_twi_sda_outen_in
= 0
230 dut
.iocell_side_io1_cell_in_in
= 0
233 if dut
.peripheral_side_twi_sda_in
!= 0:
235 "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
236 str(dut
.peripheral_side_twi_sda_in
))
238 dut
.iocell_side_io1_cell_in_in
= 1
241 if dut
.peripheral_side_twi_sda_in
!= 1:
243 "iocell_io1=1/mux=0/out=0 %s twi_sda != 1" %
244 str(dut
.peripheral_side_twi_sda_in
))
246 dut
.peripheral_side_twi_sda_outen_in
= 1
247 dut
.iocell_side_io1_cell_in_in
= 0
249 dut
._log
.info("twi_sda_in %s" % dut
.peripheral_side_twi_sda_in
)
251 if dut
.iocell_side_io1_cell_out
!= 1:
253 "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
254 str(dut
.iocell_side_io1_cell_out
))
258 dut
._log
.info("Ok!, twi_sda passed")