Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 /** \file anv_cmd_buffer.c
33 *
34 * This file contains all of the stuff for emitting commands into a command
35 * buffer. This includes implementations of most of the vkCmd*
36 * entrypoints. This file is concerned entirely with state emission and
37 * not with the command buffer data structure itself. As far as this file
38 * is concerned, most of anv_cmd_buffer is magic.
39 */
40
41 /* TODO: These are taken from GLES. We should check the Vulkan spec */
42 const struct anv_dynamic_state default_dynamic_state = {
43 .viewport = {
44 .count = 0,
45 },
46 .scissor = {
47 .count = 0,
48 },
49 .line_width = 1.0f,
50 .depth_bias = {
51 .bias = 0.0f,
52 .clamp = 0.0f,
53 .slope_scaled = 0.0f,
54 },
55 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
56 .depth_bounds = {
57 .min = 0.0f,
58 .max = 1.0f,
59 },
60 .stencil_compare_mask = {
61 .front = ~0u,
62 .back = ~0u,
63 },
64 .stencil_write_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_reference = {
69 .front = 0u,
70 .back = 0u,
71 },
72 };
73
74 void
75 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
76 const struct anv_dynamic_state *src,
77 uint32_t copy_mask)
78 {
79 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
80 dest->viewport.count = src->viewport.count;
81 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
82 src->viewport.count);
83 }
84
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
86 dest->scissor.count = src->scissor.count;
87 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
88 src->scissor.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
92 dest->line_width = src->line_width;
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
95 dest->depth_bias = src->depth_bias;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
98 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
101 dest->depth_bounds = src->depth_bounds;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
104 dest->stencil_compare_mask = src->stencil_compare_mask;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
107 dest->stencil_write_mask = src->stencil_write_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
110 dest->stencil_reference = src->stencil_reference;
111 }
112
113 static void
114 anv_cmd_state_init(struct anv_cmd_state *state)
115 {
116 memset(&state->state_vf, 0, sizeof(state->state_vf));
117 memset(&state->descriptors, 0, sizeof(state->descriptors));
118 memset(&state->push_constants, 0, sizeof(state->push_constants));
119
120 state->dirty = ~0;
121 state->vb_dirty = 0;
122 state->descriptors_dirty = 0;
123 state->push_constants_dirty = 0;
124 state->pipeline = NULL;
125 state->dynamic = default_dynamic_state;
126
127 state->gen7.index_buffer = NULL;
128 }
129
130 static VkResult
131 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
132 VkShaderStage stage, uint32_t size)
133 {
134 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
135
136 if (*ptr == NULL) {
137 *ptr = anv_device_alloc(cmd_buffer->device, size, 8,
138 VK_SYSTEM_ALLOC_TYPE_INTERNAL);
139 if (*ptr == NULL)
140 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
141 (*ptr)->size = size;
142 } else if ((*ptr)->size < size) {
143 void *new_data = anv_device_alloc(cmd_buffer->device, size, 8,
144 VK_SYSTEM_ALLOC_TYPE_INTERNAL);
145 if (new_data == NULL)
146 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
147
148 memcpy(new_data, *ptr, (*ptr)->size);
149 anv_device_free(cmd_buffer->device, *ptr);
150
151 *ptr = new_data;
152 (*ptr)->size = size;
153 }
154
155 return VK_SUCCESS;
156 }
157
158 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
159 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
160 (offsetof(struct anv_push_constants, field) + \
161 sizeof(cmd_buffer->state.push_constants[0]->field)))
162
163 VkResult anv_CreateCommandBuffer(
164 VkDevice _device,
165 const VkCmdBufferCreateInfo* pCreateInfo,
166 VkCmdBuffer* pCmdBuffer)
167 {
168 ANV_FROM_HANDLE(anv_device, device, _device);
169 ANV_FROM_HANDLE(anv_cmd_pool, pool, pCreateInfo->cmdPool);
170 struct anv_cmd_buffer *cmd_buffer;
171 VkResult result;
172
173 cmd_buffer = anv_device_alloc(device, sizeof(*cmd_buffer), 8,
174 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
175 if (cmd_buffer == NULL)
176 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
179 cmd_buffer->device = device;
180
181 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
182 if (result != VK_SUCCESS)
183 goto fail;
184
185 anv_state_stream_init(&cmd_buffer->surface_state_stream,
186 &device->surface_state_block_pool);
187 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
188 &device->dynamic_state_block_pool);
189
190 cmd_buffer->level = pCreateInfo->level;
191 cmd_buffer->opt_flags = 0;
192
193 anv_cmd_state_init(&cmd_buffer->state);
194
195 if (pool) {
196 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
197 } else {
198 /* Init the pool_link so we can safefly call list_del when we destroy
199 * the command buffer
200 */
201 list_inithead(&cmd_buffer->pool_link);
202 }
203
204 *pCmdBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
205
206 return VK_SUCCESS;
207
208 fail: anv_device_free(device, cmd_buffer);
209
210 return result;
211 }
212
213 void anv_DestroyCommandBuffer(
214 VkDevice _device,
215 VkCmdBuffer _cmd_buffer)
216 {
217 ANV_FROM_HANDLE(anv_device, device, _device);
218 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, _cmd_buffer);
219
220 list_del(&cmd_buffer->pool_link);
221
222 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
223
224 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
225 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
226 anv_device_free(device, cmd_buffer);
227 }
228
229 VkResult anv_ResetCommandBuffer(
230 VkCmdBuffer cmdBuffer,
231 VkCmdBufferResetFlags flags)
232 {
233 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
234
235 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
236
237 anv_cmd_state_init(&cmd_buffer->state);
238
239 return VK_SUCCESS;
240 }
241
242 void
243 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
244 {
245 switch (cmd_buffer->device->info.gen) {
246 case 7:
247 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
248 case 8:
249 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
250 default:
251 unreachable("unsupported gen\n");
252 }
253 }
254
255 VkResult anv_BeginCommandBuffer(
256 VkCmdBuffer cmdBuffer,
257 const VkCmdBufferBeginInfo* pBeginInfo)
258 {
259 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
260
261 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
262
263 cmd_buffer->opt_flags = pBeginInfo->flags;
264
265 if (cmd_buffer->level == VK_CMD_BUFFER_LEVEL_SECONDARY) {
266 cmd_buffer->state.framebuffer =
267 anv_framebuffer_from_handle(pBeginInfo->framebuffer);
268 cmd_buffer->state.pass =
269 anv_render_pass_from_handle(pBeginInfo->renderPass);
270
271 struct anv_subpass *subpass =
272 &cmd_buffer->state.pass->subpasses[pBeginInfo->subpass];
273
274 anv_cmd_buffer_begin_subpass(cmd_buffer, subpass);
275 }
276
277 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
278 cmd_buffer->state.current_pipeline = UINT32_MAX;
279
280 return VK_SUCCESS;
281 }
282
283 VkResult anv_EndCommandBuffer(
284 VkCmdBuffer cmdBuffer)
285 {
286 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
287 struct anv_device *device = cmd_buffer->device;
288
289 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
290
291 if (cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY) {
292 /* The algorithm used to compute the validate list is not threadsafe as
293 * it uses the bo->index field. We have to lock the device around it.
294 * Fortunately, the chances for contention here are probably very low.
295 */
296 pthread_mutex_lock(&device->mutex);
297 anv_cmd_buffer_prepare_execbuf(cmd_buffer);
298 pthread_mutex_unlock(&device->mutex);
299 }
300
301 return VK_SUCCESS;
302 }
303
304 void anv_CmdBindPipeline(
305 VkCmdBuffer cmdBuffer,
306 VkPipelineBindPoint pipelineBindPoint,
307 VkPipeline _pipeline)
308 {
309 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
310 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
311
312 switch (pipelineBindPoint) {
313 case VK_PIPELINE_BIND_POINT_COMPUTE:
314 cmd_buffer->state.compute_pipeline = pipeline;
315 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
316 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
317 break;
318
319 case VK_PIPELINE_BIND_POINT_GRAPHICS:
320 cmd_buffer->state.pipeline = pipeline;
321 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
322 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
323 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
324
325 /* Apply the dynamic state from the pipeline */
326 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
327 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
328 &pipeline->dynamic_state,
329 pipeline->dynamic_state_mask);
330 break;
331
332 default:
333 assert(!"invalid bind point");
334 break;
335 }
336 }
337
338 void anv_CmdSetViewport(
339 VkCmdBuffer cmdBuffer,
340 uint32_t viewportCount,
341 const VkViewport* pViewports)
342 {
343 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
344
345 cmd_buffer->state.dynamic.viewport.count = viewportCount;
346 memcpy(cmd_buffer->state.dynamic.viewport.viewports,
347 pViewports, viewportCount * sizeof(*pViewports));
348
349 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
350 }
351
352 void anv_CmdSetScissor(
353 VkCmdBuffer cmdBuffer,
354 uint32_t scissorCount,
355 const VkRect2D* pScissors)
356 {
357 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
358
359 cmd_buffer->state.dynamic.scissor.count = scissorCount;
360 memcpy(cmd_buffer->state.dynamic.scissor.scissors,
361 pScissors, scissorCount * sizeof(*pScissors));
362
363 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
364 }
365
366 void anv_CmdSetLineWidth(
367 VkCmdBuffer cmdBuffer,
368 float lineWidth)
369 {
370 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
371
372 cmd_buffer->state.dynamic.line_width = lineWidth;
373 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
374 }
375
376 void anv_CmdSetDepthBias(
377 VkCmdBuffer cmdBuffer,
378 float depthBias,
379 float depthBiasClamp,
380 float slopeScaledDepthBias)
381 {
382 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
383
384 cmd_buffer->state.dynamic.depth_bias.bias = depthBias;
385 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
386 cmd_buffer->state.dynamic.depth_bias.slope_scaled = slopeScaledDepthBias;
387
388 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
389 }
390
391 void anv_CmdSetBlendConstants(
392 VkCmdBuffer cmdBuffer,
393 const float blendConst[4])
394 {
395 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
396
397 memcpy(cmd_buffer->state.dynamic.blend_constants,
398 blendConst, sizeof(float) * 4);
399
400 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
401 }
402
403 void anv_CmdSetDepthBounds(
404 VkCmdBuffer cmdBuffer,
405 float minDepthBounds,
406 float maxDepthBounds)
407 {
408 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
409
410 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
411 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
412
413 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
414 }
415
416 void anv_CmdSetStencilCompareMask(
417 VkCmdBuffer cmdBuffer,
418 VkStencilFaceFlags faceMask,
419 uint32_t stencilCompareMask)
420 {
421 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
422
423 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
424 cmd_buffer->state.dynamic.stencil_compare_mask.front = stencilCompareMask;
425 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
426 cmd_buffer->state.dynamic.stencil_compare_mask.back = stencilCompareMask;
427
428 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
429 }
430
431 void anv_CmdSetStencilWriteMask(
432 VkCmdBuffer cmdBuffer,
433 VkStencilFaceFlags faceMask,
434 uint32_t stencilWriteMask)
435 {
436 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
437
438 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
439 cmd_buffer->state.dynamic.stencil_write_mask.front = stencilWriteMask;
440 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
441 cmd_buffer->state.dynamic.stencil_write_mask.back = stencilWriteMask;
442
443 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
444 }
445
446 void anv_CmdSetStencilReference(
447 VkCmdBuffer cmdBuffer,
448 VkStencilFaceFlags faceMask,
449 uint32_t stencilReference)
450 {
451 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
452
453 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
454 cmd_buffer->state.dynamic.stencil_reference.front = stencilReference;
455 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
456 cmd_buffer->state.dynamic.stencil_reference.back = stencilReference;
457
458 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
459 }
460
461 void anv_CmdBindDescriptorSets(
462 VkCmdBuffer cmdBuffer,
463 VkPipelineBindPoint pipelineBindPoint,
464 VkPipelineLayout _layout,
465 uint32_t firstSet,
466 uint32_t setCount,
467 const VkDescriptorSet* pDescriptorSets,
468 uint32_t dynamicOffsetCount,
469 const uint32_t* pDynamicOffsets)
470 {
471 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
472 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
473 struct anv_descriptor_set_layout *set_layout;
474
475 assert(firstSet + setCount < MAX_SETS);
476
477 uint32_t dynamic_slot = 0;
478 for (uint32_t i = 0; i < setCount; i++) {
479 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
480 set_layout = layout->set[firstSet + i].layout;
481
482 if (cmd_buffer->state.descriptors[firstSet + i] != set) {
483 cmd_buffer->state.descriptors[firstSet + i] = set;
484 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
485 }
486
487 if (set_layout->dynamic_offset_count > 0) {
488 VkShaderStage s;
489 for_each_bit(s, set_layout->shader_stages) {
490 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, s, dynamic);
491
492 struct anv_push_constants *push =
493 cmd_buffer->state.push_constants[s];
494
495 unsigned d = layout->set[firstSet + i].dynamic_offset_start;
496 const uint32_t *offsets = pDynamicOffsets + dynamic_slot;
497 struct anv_descriptor *desc = set->descriptors;
498
499 for (unsigned b = 0; b < set_layout->binding_count; b++) {
500 if (set_layout->binding[b].dynamic_offset_index < 0)
501 continue;
502
503 unsigned array_size = set_layout->binding[b].array_size;
504 for (unsigned j = 0; j < array_size; j++) {
505 push->dynamic[d].offset = *(offsets++);
506 push->dynamic[d].range = (desc++)->range;
507 d++;
508 }
509 }
510 }
511 cmd_buffer->state.push_constants_dirty |= set_layout->shader_stages;
512 }
513 }
514 }
515
516 void anv_CmdBindVertexBuffers(
517 VkCmdBuffer cmdBuffer,
518 uint32_t startBinding,
519 uint32_t bindingCount,
520 const VkBuffer* pBuffers,
521 const VkDeviceSize* pOffsets)
522 {
523 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
524 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
525
526 /* We have to defer setting up vertex buffer since we need the buffer
527 * stride from the pipeline. */
528
529 assert(startBinding + bindingCount < MAX_VBS);
530 for (uint32_t i = 0; i < bindingCount; i++) {
531 vb[startBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
532 vb[startBinding + i].offset = pOffsets[i];
533 cmd_buffer->state.vb_dirty |= 1 << (startBinding + i);
534 }
535 }
536
537 static void
538 add_surface_state_reloc(struct anv_cmd_buffer *cmd_buffer,
539 struct anv_state state, struct anv_bo *bo, uint32_t offset)
540 {
541 /* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and
542 * 9 for gen8+. We only write the first dword for gen8+ here and rely on
543 * the initial state to set the high bits to 0. */
544
545 const uint32_t dword = cmd_buffer->device->info.gen < 8 ? 1 : 8;
546
547 anv_reloc_list_add(&cmd_buffer->surface_relocs, cmd_buffer->device,
548 state.offset + dword * 4, bo, offset);
549 }
550
551 static void
552 fill_descriptor_buffer_surface_state(struct anv_device *device, void *state,
553 VkShaderStage stage, VkDescriptorType type,
554 uint32_t offset, uint32_t range)
555 {
556 VkFormat format;
557 uint32_t stride;
558
559 switch (type) {
560 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
561 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
562 if (anv_is_scalar_shader_stage(device->instance->physicalDevice.compiler,
563 stage)) {
564 stride = 4;
565 } else {
566 stride = 16;
567 }
568 format = VK_FORMAT_R32G32B32A32_SFLOAT;
569 break;
570
571 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
572 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
573 stride = 1;
574 format = VK_FORMAT_UNDEFINED;
575 break;
576
577 default:
578 unreachable("Invalid descriptor type");
579 }
580
581 anv_fill_buffer_surface_state(device, state,
582 anv_format_for_vk_format(format),
583 offset, range, stride);
584 }
585
586 VkResult
587 anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
588 VkShaderStage stage, struct anv_state *bt_state)
589 {
590 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
591 struct anv_subpass *subpass = cmd_buffer->state.subpass;
592 struct anv_pipeline_layout *layout;
593 uint32_t color_count, bias, state_offset;
594
595 if (stage == VK_SHADER_STAGE_COMPUTE)
596 layout = cmd_buffer->state.compute_pipeline->layout;
597 else
598 layout = cmd_buffer->state.pipeline->layout;
599
600 if (stage == VK_SHADER_STAGE_FRAGMENT) {
601 bias = MAX_RTS;
602 color_count = subpass->color_count;
603 } else {
604 bias = 0;
605 color_count = 0;
606 }
607
608 /* This is a little awkward: layout can be NULL but we still have to
609 * allocate and set a binding table for the PS stage for render
610 * targets. */
611 uint32_t surface_count = layout ? layout->stage[stage].surface_count : 0;
612
613 if (color_count + surface_count == 0)
614 return VK_SUCCESS;
615
616 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
617 bias + surface_count,
618 &state_offset);
619 uint32_t *bt_map = bt_state->map;
620
621 if (bt_state->map == NULL)
622 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
623
624 for (uint32_t a = 0; a < color_count; a++) {
625 const struct anv_image_view *iview =
626 fb->attachments[subpass->color_attachments[a]];
627
628 bt_map[a] = iview->color_rt_surface_state.offset + state_offset;
629 add_surface_state_reloc(cmd_buffer, iview->color_rt_surface_state,
630 iview->bo, iview->offset);
631 }
632
633 if (layout == NULL)
634 return VK_SUCCESS;
635
636 for (uint32_t s = 0; s < layout->stage[stage].surface_count; s++) {
637 struct anv_pipeline_binding *binding =
638 &layout->stage[stage].surface_to_descriptor[s];
639 struct anv_descriptor_set *set =
640 cmd_buffer->state.descriptors[binding->set];
641 struct anv_descriptor *desc = &set->descriptors[binding->offset];
642
643 struct anv_state surface_state;
644 struct anv_bo *bo;
645 uint32_t bo_offset;
646
647 switch (desc->type) {
648 case VK_DESCRIPTOR_TYPE_SAMPLER:
649 /* Nothing for us to do here */
650 continue;
651
652 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
653 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
654 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
655 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
656 bo = desc->buffer->bo;
657 bo_offset = desc->buffer->offset + desc->offset;
658
659 surface_state =
660 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
661
662 fill_descriptor_buffer_surface_state(cmd_buffer->device,
663 surface_state.map,
664 stage, desc->type,
665 bo_offset, desc->range);
666 break;
667 }
668
669 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
670 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
671 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
672 surface_state = desc->image_view->nonrt_surface_state;
673 bo = desc->image_view->bo;
674 bo_offset = desc->image_view->offset;
675 break;
676
677 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
678 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
679 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
680 assert(!"Unsupported descriptor type");
681 break;
682 }
683
684 bt_map[bias + s] = surface_state.offset + state_offset;
685 add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset);
686 }
687
688 return VK_SUCCESS;
689 }
690
691 VkResult
692 anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
693 VkShaderStage stage, struct anv_state *state)
694 {
695 struct anv_pipeline_layout *layout;
696 uint32_t sampler_count;
697
698 if (stage == VK_SHADER_STAGE_COMPUTE)
699 layout = cmd_buffer->state.compute_pipeline->layout;
700 else
701 layout = cmd_buffer->state.pipeline->layout;
702
703 sampler_count = layout ? layout->stage[stage].sampler_count : 0;
704 if (sampler_count == 0)
705 return VK_SUCCESS;
706
707 uint32_t size = sampler_count * 16;
708 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
709
710 if (state->map == NULL)
711 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
712
713 for (uint32_t s = 0; s < layout->stage[stage].sampler_count; s++) {
714 struct anv_pipeline_binding *binding =
715 &layout->stage[stage].sampler_to_descriptor[s];
716 struct anv_descriptor_set *set =
717 cmd_buffer->state.descriptors[binding->set];
718 struct anv_descriptor *desc = &set->descriptors[binding->offset];
719
720 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
721 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
722 continue;
723
724 struct anv_sampler *sampler = desc->sampler;
725
726 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
727 * happens to be zero.
728 */
729 if (sampler == NULL)
730 continue;
731
732 memcpy(state->map + (s * 16),
733 sampler->state, sizeof(sampler->state));
734 }
735
736 return VK_SUCCESS;
737 }
738
739 static VkResult
740 flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, VkShaderStage stage)
741 {
742 struct anv_state surfaces = { 0, }, samplers = { 0, };
743 VkResult result;
744
745 result = anv_cmd_buffer_emit_samplers(cmd_buffer, stage, &samplers);
746 if (result != VK_SUCCESS)
747 return result;
748 result = anv_cmd_buffer_emit_binding_table(cmd_buffer, stage, &surfaces);
749 if (result != VK_SUCCESS)
750 return result;
751
752 static const uint32_t sampler_state_opcodes[] = {
753 [VK_SHADER_STAGE_VERTEX] = 43,
754 [VK_SHADER_STAGE_TESS_CONTROL] = 44, /* HS */
755 [VK_SHADER_STAGE_TESS_EVALUATION] = 45, /* DS */
756 [VK_SHADER_STAGE_GEOMETRY] = 46,
757 [VK_SHADER_STAGE_FRAGMENT] = 47,
758 [VK_SHADER_STAGE_COMPUTE] = 0,
759 };
760
761 static const uint32_t binding_table_opcodes[] = {
762 [VK_SHADER_STAGE_VERTEX] = 38,
763 [VK_SHADER_STAGE_TESS_CONTROL] = 39,
764 [VK_SHADER_STAGE_TESS_EVALUATION] = 40,
765 [VK_SHADER_STAGE_GEOMETRY] = 41,
766 [VK_SHADER_STAGE_FRAGMENT] = 42,
767 [VK_SHADER_STAGE_COMPUTE] = 0,
768 };
769
770 if (samplers.alloc_size > 0) {
771 anv_batch_emit(&cmd_buffer->batch,
772 GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
773 ._3DCommandSubOpcode = sampler_state_opcodes[stage],
774 .PointertoVSSamplerState = samplers.offset);
775 }
776
777 if (surfaces.alloc_size > 0) {
778 anv_batch_emit(&cmd_buffer->batch,
779 GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
780 ._3DCommandSubOpcode = binding_table_opcodes[stage],
781 .PointertoVSBindingTable = surfaces.offset);
782 }
783
784 return VK_SUCCESS;
785 }
786
787 void
788 anv_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
789 {
790 VkShaderStage s;
791 VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
792 cmd_buffer->state.pipeline->active_stages;
793
794 VkResult result = VK_SUCCESS;
795 for_each_bit(s, dirty) {
796 result = flush_descriptor_set(cmd_buffer, s);
797 if (result != VK_SUCCESS)
798 break;
799 }
800
801 if (result != VK_SUCCESS) {
802 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
803
804 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
805 assert(result == VK_SUCCESS);
806
807 /* Re-emit state base addresses so we get the new surface state base
808 * address before we start emitting binding tables etc.
809 */
810 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
811
812 /* Re-emit all active binding tables */
813 for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
814 result = flush_descriptor_set(cmd_buffer, s);
815
816 /* It had better succeed this time */
817 assert(result == VK_SUCCESS);
818 }
819 }
820
821 cmd_buffer->state.descriptors_dirty &= ~cmd_buffer->state.pipeline->active_stages;
822 }
823
824 struct anv_state
825 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
826 uint32_t *a, uint32_t dwords, uint32_t alignment)
827 {
828 struct anv_state state;
829
830 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
831 dwords * 4, alignment);
832 memcpy(state.map, a, dwords * 4);
833
834 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, dwords * 4));
835
836 return state;
837 }
838
839 struct anv_state
840 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
841 uint32_t *a, uint32_t *b,
842 uint32_t dwords, uint32_t alignment)
843 {
844 struct anv_state state;
845 uint32_t *p;
846
847 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
848 dwords * 4, alignment);
849 p = state.map;
850 for (uint32_t i = 0; i < dwords; i++)
851 p[i] = a[i] | b[i];
852
853 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
854
855 return state;
856 }
857
858 void
859 anv_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
860 struct anv_subpass *subpass)
861 {
862 switch (cmd_buffer->device->info.gen) {
863 case 7:
864 gen7_cmd_buffer_begin_subpass(cmd_buffer, subpass);
865 break;
866 case 8:
867 gen8_cmd_buffer_begin_subpass(cmd_buffer, subpass);
868 break;
869 default:
870 unreachable("unsupported gen\n");
871 }
872 }
873
874 static void
875 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
876 uint32_t count, const VkViewport *viewports)
877 {
878 struct anv_state sf_clip_state =
879 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
880 struct anv_state cc_state =
881 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
882
883 for (uint32_t i = 0; i < count; i++) {
884 const VkViewport *vp = &viewports[i];
885
886 /* The gen7 state struct has just the matrix and guardband fields, the
887 * gen8 struct adds the min/max viewport fields. */
888 struct GEN8_SF_CLIP_VIEWPORT sf_clip_viewport = {
889 .ViewportMatrixElementm00 = vp->width / 2,
890 .ViewportMatrixElementm11 = vp->height / 2,
891 .ViewportMatrixElementm22 = (vp->maxDepth - vp->minDepth) / 2,
892 .ViewportMatrixElementm30 = vp->originX + vp->width / 2,
893 .ViewportMatrixElementm31 = vp->originY + vp->height / 2,
894 .ViewportMatrixElementm32 = (vp->maxDepth + vp->minDepth) / 2,
895 .XMinClipGuardband = -1.0f,
896 .XMaxClipGuardband = 1.0f,
897 .YMinClipGuardband = -1.0f,
898 .YMaxClipGuardband = 1.0f,
899 .XMinViewPort = vp->originX,
900 .XMaxViewPort = vp->originX + vp->width - 1,
901 .YMinViewPort = vp->originY,
902 .YMaxViewPort = vp->originY + vp->height - 1,
903 };
904
905 struct GEN7_CC_VIEWPORT cc_viewport = {
906 .MinimumDepth = vp->minDepth,
907 .MaximumDepth = vp->maxDepth
908 };
909
910 GEN8_SF_CLIP_VIEWPORT_pack(NULL, sf_clip_state.map + i * 64,
911 &sf_clip_viewport);
912 GEN7_CC_VIEWPORT_pack(NULL, cc_state.map + i * 32, &cc_viewport);
913 }
914
915 anv_batch_emit(&cmd_buffer->batch,
916 GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
917 .CCViewportPointer = cc_state.offset);
918 anv_batch_emit(&cmd_buffer->batch,
919 GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
920 .SFClipViewportPointer = sf_clip_state.offset);
921 }
922
923 void
924 anv_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
925 {
926 if (cmd_buffer->state.dynamic.viewport.count > 0) {
927 emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
928 cmd_buffer->state.dynamic.viewport.viewports);
929 } else {
930 /* If viewport count is 0, this is taken to mean "use the default" */
931 emit_viewport_state(cmd_buffer, 1,
932 &(VkViewport) {
933 .originX = 0.0f,
934 .originY = 0.0f,
935 .width = cmd_buffer->state.framebuffer->width,
936 .height = cmd_buffer->state.framebuffer->height,
937 .minDepth = 0.0f,
938 .maxDepth = 1.0f,
939 });
940 }
941 }
942
943 static inline int64_t
944 clamp_int64(int64_t x, int64_t min, int64_t max)
945 {
946 if (x < min)
947 return min;
948 else if (x < max)
949 return x;
950 else
951 return max;
952 }
953
954 static void
955 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
956 uint32_t count, const VkRect2D *scissors)
957 {
958 struct anv_state scissor_state =
959 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 32, 32);
960
961 for (uint32_t i = 0; i < count; i++) {
962 const VkRect2D *s = &scissors[i];
963
964 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
965 * ymax < ymin for empty clips. In case clip x, y, width height are all
966 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
967 * what we want. Just special case empty clips and produce a canonical
968 * empty clip. */
969 static const struct GEN7_SCISSOR_RECT empty_scissor = {
970 .ScissorRectangleYMin = 1,
971 .ScissorRectangleXMin = 1,
972 .ScissorRectangleYMax = 0,
973 .ScissorRectangleXMax = 0
974 };
975
976 const int max = 0xffff;
977 struct GEN7_SCISSOR_RECT scissor = {
978 /* Do this math using int64_t so overflow gets clamped correctly. */
979 .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
980 .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
981 .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
982 .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
983 };
984
985 if (s->extent.width <= 0 || s->extent.height <= 0) {
986 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32,
987 &empty_scissor);
988 } else {
989 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32, &scissor);
990 }
991 }
992
993 anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_SCISSOR_STATE_POINTERS,
994 .ScissorRectPointer = scissor_state.offset);
995 }
996
997 void
998 anv_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
999 {
1000 if (cmd_buffer->state.dynamic.scissor.count > 0) {
1001 emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
1002 cmd_buffer->state.dynamic.scissor.scissors);
1003 } else {
1004 /* Emit a default scissor based on the currently bound framebuffer */
1005 emit_scissor_state(cmd_buffer, 1,
1006 &(VkRect2D) {
1007 .offset = { .x = 0, .y = 0, },
1008 .extent = {
1009 .width = cmd_buffer->state.framebuffer->width,
1010 .height = cmd_buffer->state.framebuffer->height,
1011 },
1012 });
1013 }
1014 }
1015
1016 void anv_CmdSetEvent(
1017 VkCmdBuffer cmdBuffer,
1018 VkEvent event,
1019 VkPipelineStageFlags stageMask)
1020 {
1021 stub();
1022 }
1023
1024 void anv_CmdResetEvent(
1025 VkCmdBuffer cmdBuffer,
1026 VkEvent event,
1027 VkPipelineStageFlags stageMask)
1028 {
1029 stub();
1030 }
1031
1032 void anv_CmdWaitEvents(
1033 VkCmdBuffer cmdBuffer,
1034 uint32_t eventCount,
1035 const VkEvent* pEvents,
1036 VkPipelineStageFlags srcStageMask,
1037 VkPipelineStageFlags destStageMask,
1038 uint32_t memBarrierCount,
1039 const void* const* ppMemBarriers)
1040 {
1041 stub();
1042 }
1043
1044 struct anv_state
1045 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1046 VkShaderStage stage)
1047 {
1048 struct anv_push_constants *data =
1049 cmd_buffer->state.push_constants[stage];
1050 struct brw_stage_prog_data *prog_data =
1051 cmd_buffer->state.pipeline->prog_data[stage];
1052
1053 /* If we don't actually have any push constants, bail. */
1054 if (data == NULL || prog_data->nr_params == 0)
1055 return (struct anv_state) { .offset = 0 };
1056
1057 struct anv_state state =
1058 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
1059 prog_data->nr_params * sizeof(float),
1060 32 /* bottom 5 bits MBZ */);
1061
1062 /* Walk through the param array and fill the buffer with data */
1063 uint32_t *u32_map = state.map;
1064 for (unsigned i = 0; i < prog_data->nr_params; i++) {
1065 uint32_t offset = (uintptr_t)prog_data->param[i];
1066 u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
1067 }
1068
1069 return state;
1070 }
1071
1072 void anv_CmdPushConstants(
1073 VkCmdBuffer cmdBuffer,
1074 VkPipelineLayout layout,
1075 VkShaderStageFlags stageFlags,
1076 uint32_t start,
1077 uint32_t length,
1078 const void* values)
1079 {
1080 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
1081 VkShaderStage stage;
1082
1083 for_each_bit(stage, stageFlags) {
1084 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, client_data);
1085
1086 memcpy(cmd_buffer->state.push_constants[stage]->client_data + start,
1087 values, length);
1088 }
1089
1090 cmd_buffer->state.push_constants_dirty |= stageFlags;
1091 }
1092
1093 void anv_CmdExecuteCommands(
1094 VkCmdBuffer cmdBuffer,
1095 uint32_t cmdBuffersCount,
1096 const VkCmdBuffer* pCmdBuffers)
1097 {
1098 ANV_FROM_HANDLE(anv_cmd_buffer, primary, cmdBuffer);
1099
1100 assert(primary->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
1101
1102 anv_assert(primary->state.subpass == &primary->state.pass->subpasses[0]);
1103
1104 for (uint32_t i = 0; i < cmdBuffersCount; i++) {
1105 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
1106
1107 assert(secondary->level == VK_CMD_BUFFER_LEVEL_SECONDARY);
1108
1109 anv_cmd_buffer_add_secondary(primary, secondary);
1110 }
1111 }
1112
1113 VkResult anv_CreateCommandPool(
1114 VkDevice _device,
1115 const VkCmdPoolCreateInfo* pCreateInfo,
1116 VkCmdPool* pCmdPool)
1117 {
1118 ANV_FROM_HANDLE(anv_device, device, _device);
1119 struct anv_cmd_pool *pool;
1120
1121 pool = anv_device_alloc(device, sizeof(*pool), 8,
1122 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
1123 if (pool == NULL)
1124 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1125
1126 list_inithead(&pool->cmd_buffers);
1127
1128 *pCmdPool = anv_cmd_pool_to_handle(pool);
1129
1130 return VK_SUCCESS;
1131 }
1132
1133 void anv_DestroyCommandPool(
1134 VkDevice _device,
1135 VkCmdPool cmdPool)
1136 {
1137 ANV_FROM_HANDLE(anv_device, device, _device);
1138 ANV_FROM_HANDLE(anv_cmd_pool, pool, cmdPool);
1139
1140 anv_ResetCommandPool(_device, cmdPool, 0);
1141
1142 anv_device_free(device, pool);
1143 }
1144
1145 VkResult anv_ResetCommandPool(
1146 VkDevice device,
1147 VkCmdPool cmdPool,
1148 VkCmdPoolResetFlags flags)
1149 {
1150 ANV_FROM_HANDLE(anv_cmd_pool, pool, cmdPool);
1151
1152 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
1153 &pool->cmd_buffers, pool_link) {
1154 anv_DestroyCommandBuffer(device, anv_cmd_buffer_to_handle(cmd_buffer));
1155 }
1156
1157 return VK_SUCCESS;
1158 }
1159
1160 /**
1161 * Return NULL if the current subpass has no depthstencil attachment.
1162 */
1163 const struct anv_image_view *
1164 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
1165 {
1166 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1167 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1168
1169 if (subpass->depth_stencil_attachment == VK_ATTACHMENT_UNUSED)
1170 return NULL;
1171
1172 const struct anv_image_view *iview =
1173 fb->attachments[subpass->depth_stencil_attachment];
1174
1175 assert(anv_format_is_depth_or_stencil(iview->format));
1176
1177 return iview;
1178 }