2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 /** \file anv_cmd_buffer.c
34 * This file contains all of the stuff for emitting commands into a command
35 * buffer. This includes implementations of most of the vkCmd*
36 * entrypoints. This file is concerned entirely with state emission and
37 * not with the command buffer data structure itself. As far as this file
38 * is concerned, most of anv_cmd_buffer is magic.
41 /* TODO: These are taken from GLES. We should check the Vulkan spec */
42 const struct anv_dynamic_state default_dynamic_state
= {
55 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
60 .stencil_compare_mask
= {
64 .stencil_write_mask
= {
68 .stencil_reference
= {
75 anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
76 const struct anv_dynamic_state
*src
,
79 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
80 dest
->viewport
.count
= src
->viewport
.count
;
81 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
85 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
86 dest
->scissor
.count
= src
->scissor
.count
;
87 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
91 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
92 dest
->line_width
= src
->line_width
;
94 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
95 dest
->depth_bias
= src
->depth_bias
;
97 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
98 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
100 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
101 dest
->depth_bounds
= src
->depth_bounds
;
103 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
104 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
106 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
107 dest
->stencil_write_mask
= src
->stencil_write_mask
;
109 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
110 dest
->stencil_reference
= src
->stencil_reference
;
114 anv_cmd_state_init(struct anv_cmd_state
*state
)
116 memset(&state
->descriptors
, 0, sizeof(state
->descriptors
));
117 memset(&state
->push_constants
, 0, sizeof(state
->push_constants
));
121 state
->descriptors_dirty
= 0;
122 state
->push_constants_dirty
= 0;
123 state
->pipeline
= NULL
;
124 state
->restart_index
= UINT32_MAX
;
125 state
->dynamic
= default_dynamic_state
;
127 state
->gen7
.index_buffer
= NULL
;
131 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
132 gl_shader_stage stage
, uint32_t size
)
134 struct anv_push_constants
**ptr
= &cmd_buffer
->state
.push_constants
[stage
];
137 *ptr
= anv_alloc(&cmd_buffer
->pool
->alloc
, size
, 8,
138 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
140 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
141 } else if ((*ptr
)->size
< size
) {
142 *ptr
= anv_realloc(&cmd_buffer
->pool
->alloc
, *ptr
, size
, 8,
143 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
145 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
152 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
153 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
154 (offsetof(struct anv_push_constants, field) + \
155 sizeof(cmd_buffer->state.push_constants[0]->field)))
157 static VkResult
anv_create_cmd_buffer(
158 struct anv_device
* device
,
159 struct anv_cmd_pool
* pool
,
160 VkCommandBufferLevel level
,
161 VkCommandBuffer
* pCommandBuffer
)
163 struct anv_cmd_buffer
*cmd_buffer
;
166 cmd_buffer
= anv_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
168 if (cmd_buffer
== NULL
)
169 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
171 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
172 cmd_buffer
->device
= device
;
173 cmd_buffer
->pool
= pool
;
175 result
= anv_cmd_buffer_init_batch_bo_chain(cmd_buffer
);
176 if (result
!= VK_SUCCESS
)
179 anv_state_stream_init(&cmd_buffer
->surface_state_stream
,
180 &device
->surface_state_block_pool
);
181 anv_state_stream_init(&cmd_buffer
->dynamic_state_stream
,
182 &device
->dynamic_state_block_pool
);
184 cmd_buffer
->level
= level
;
185 cmd_buffer
->usage_flags
= 0;
187 anv_cmd_state_init(&cmd_buffer
->state
);
190 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
192 /* Init the pool_link so we can safefly call list_del when we destroy
195 list_inithead(&cmd_buffer
->pool_link
);
198 *pCommandBuffer
= anv_cmd_buffer_to_handle(cmd_buffer
);
203 anv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
208 VkResult
anv_AllocateCommandBuffers(
210 const VkCommandBufferAllocateInfo
* pAllocateInfo
,
211 VkCommandBuffer
* pCommandBuffers
)
213 ANV_FROM_HANDLE(anv_device
, device
, _device
);
214 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
216 VkResult result
= VK_SUCCESS
;
219 for (i
= 0; i
< pAllocateInfo
->bufferCount
; i
++) {
220 result
= anv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
221 &pCommandBuffers
[i
]);
222 if (result
!= VK_SUCCESS
)
226 if (result
!= VK_SUCCESS
)
227 anv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
234 anv_cmd_buffer_destroy(struct anv_cmd_buffer
*cmd_buffer
)
236 list_del(&cmd_buffer
->pool_link
);
238 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer
);
240 anv_state_stream_finish(&cmd_buffer
->surface_state_stream
);
241 anv_state_stream_finish(&cmd_buffer
->dynamic_state_stream
);
243 anv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
246 void anv_FreeCommandBuffers(
248 VkCommandPool commandPool
,
249 uint32_t commandBufferCount
,
250 const VkCommandBuffer
* pCommandBuffers
)
252 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
253 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
255 anv_cmd_buffer_destroy(cmd_buffer
);
259 VkResult
anv_ResetCommandBuffer(
260 VkCommandBuffer commandBuffer
,
261 VkCommandBufferResetFlags flags
)
263 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
265 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer
);
267 anv_cmd_state_init(&cmd_buffer
->state
);
273 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
)
275 switch (cmd_buffer
->device
->info
.gen
) {
277 if (cmd_buffer
->device
->info
.is_haswell
)
278 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer
);
280 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer
);
282 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer
);
284 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer
);
286 unreachable("unsupported gen\n");
290 VkResult
anv_BeginCommandBuffer(
291 VkCommandBuffer commandBuffer
,
292 const VkCommandBufferBeginInfo
* pBeginInfo
)
294 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer
);
298 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
300 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
301 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
303 if (cmd_buffer
->usage_flags
&
304 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
305 cmd_buffer
->state
.framebuffer
=
306 anv_framebuffer_from_handle(pBeginInfo
->framebuffer
);
307 cmd_buffer
->state
.pass
=
308 anv_render_pass_from_handle(pBeginInfo
->renderPass
);
310 struct anv_subpass
*subpass
=
311 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->subpass
];
313 anv_cmd_buffer_begin_subpass(cmd_buffer
, subpass
);
316 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
317 cmd_buffer
->state
.current_pipeline
= UINT32_MAX
;
322 VkResult
anv_EndCommandBuffer(
323 VkCommandBuffer commandBuffer
)
325 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
326 struct anv_device
*device
= cmd_buffer
->device
;
328 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
330 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
331 /* The algorithm used to compute the validate list is not threadsafe as
332 * it uses the bo->index field. We have to lock the device around it.
333 * Fortunately, the chances for contention here are probably very low.
335 pthread_mutex_lock(&device
->mutex
);
336 anv_cmd_buffer_prepare_execbuf(cmd_buffer
);
337 pthread_mutex_unlock(&device
->mutex
);
343 void anv_CmdBindPipeline(
344 VkCommandBuffer commandBuffer
,
345 VkPipelineBindPoint pipelineBindPoint
,
346 VkPipeline _pipeline
)
348 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
349 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
351 switch (pipelineBindPoint
) {
352 case VK_PIPELINE_BIND_POINT_COMPUTE
:
353 cmd_buffer
->state
.compute_pipeline
= pipeline
;
354 cmd_buffer
->state
.compute_dirty
|= ANV_CMD_DIRTY_PIPELINE
;
355 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
358 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
359 cmd_buffer
->state
.pipeline
= pipeline
;
360 cmd_buffer
->state
.vb_dirty
|= pipeline
->vb_used
;
361 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
362 cmd_buffer
->state
.push_constants_dirty
|= pipeline
->active_stages
;
364 /* Apply the dynamic state from the pipeline */
365 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
366 anv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
367 &pipeline
->dynamic_state
,
368 pipeline
->dynamic_state_mask
);
372 assert(!"invalid bind point");
377 void anv_CmdSetViewport(
378 VkCommandBuffer commandBuffer
,
379 uint32_t viewportCount
,
380 const VkViewport
* pViewports
)
382 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
384 cmd_buffer
->state
.dynamic
.viewport
.count
= viewportCount
;
385 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
,
386 pViewports
, viewportCount
* sizeof(*pViewports
));
388 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
391 void anv_CmdSetScissor(
392 VkCommandBuffer commandBuffer
,
393 uint32_t scissorCount
,
394 const VkRect2D
* pScissors
)
396 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
398 cmd_buffer
->state
.dynamic
.scissor
.count
= scissorCount
;
399 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
,
400 pScissors
, scissorCount
* sizeof(*pScissors
));
402 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
405 void anv_CmdSetLineWidth(
406 VkCommandBuffer commandBuffer
,
409 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
411 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
412 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
415 void anv_CmdSetDepthBias(
416 VkCommandBuffer commandBuffer
,
417 float depthBiasConstantFactor
,
418 float depthBiasClamp
,
419 float depthBiasSlopeFactor
)
421 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
423 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
424 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
425 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
427 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
430 void anv_CmdSetBlendConstants(
431 VkCommandBuffer commandBuffer
,
432 const float blendConstants
[4])
434 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
436 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
437 blendConstants
, sizeof(float) * 4);
439 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
442 void anv_CmdSetDepthBounds(
443 VkCommandBuffer commandBuffer
,
444 float minDepthBounds
,
445 float maxDepthBounds
)
447 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
449 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
450 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
452 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
455 void anv_CmdSetStencilCompareMask(
456 VkCommandBuffer commandBuffer
,
457 VkStencilFaceFlags faceMask
,
458 uint32_t compareMask
)
460 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
462 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
463 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
464 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
465 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
467 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
470 void anv_CmdSetStencilWriteMask(
471 VkCommandBuffer commandBuffer
,
472 VkStencilFaceFlags faceMask
,
475 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
477 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
478 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
479 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
480 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
482 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
485 void anv_CmdSetStencilReference(
486 VkCommandBuffer commandBuffer
,
487 VkStencilFaceFlags faceMask
,
490 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
492 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
493 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
494 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
495 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
497 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
500 void anv_CmdBindDescriptorSets(
501 VkCommandBuffer commandBuffer
,
502 VkPipelineBindPoint pipelineBindPoint
,
503 VkPipelineLayout _layout
,
505 uint32_t descriptorSetCount
,
506 const VkDescriptorSet
* pDescriptorSets
,
507 uint32_t dynamicOffsetCount
,
508 const uint32_t* pDynamicOffsets
)
510 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
511 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, _layout
);
512 struct anv_descriptor_set_layout
*set_layout
;
514 assert(firstSet
+ descriptorSetCount
< MAX_SETS
);
516 uint32_t dynamic_slot
= 0;
517 for (uint32_t i
= 0; i
< descriptorSetCount
; i
++) {
518 ANV_FROM_HANDLE(anv_descriptor_set
, set
, pDescriptorSets
[i
]);
519 set_layout
= layout
->set
[firstSet
+ i
].layout
;
521 if (cmd_buffer
->state
.descriptors
[firstSet
+ i
] != set
) {
522 cmd_buffer
->state
.descriptors
[firstSet
+ i
] = set
;
523 cmd_buffer
->state
.descriptors_dirty
|= set_layout
->shader_stages
;
526 if (set_layout
->dynamic_offset_count
> 0) {
527 anv_foreach_stage(s
, set_layout
->shader_stages
) {
528 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, s
, dynamic
);
530 struct anv_push_constants
*push
=
531 cmd_buffer
->state
.push_constants
[s
];
533 unsigned d
= layout
->set
[firstSet
+ i
].dynamic_offset_start
;
534 const uint32_t *offsets
= pDynamicOffsets
+ dynamic_slot
;
535 struct anv_descriptor
*desc
= set
->descriptors
;
537 for (unsigned b
= 0; b
< set_layout
->binding_count
; b
++) {
538 if (set_layout
->binding
[b
].dynamic_offset_index
< 0)
541 unsigned array_size
= set_layout
->binding
[b
].array_size
;
542 for (unsigned j
= 0; j
< array_size
; j
++) {
544 if (desc
->buffer_view
)
545 range
= desc
->buffer_view
->range
;
546 push
->dynamic
[d
].offset
= *(offsets
++);
547 push
->dynamic
[d
].range
= range
;
553 cmd_buffer
->state
.push_constants_dirty
|= set_layout
->shader_stages
;
558 void anv_CmdBindVertexBuffers(
559 VkCommandBuffer commandBuffer
,
560 uint32_t startBinding
,
561 uint32_t bindingCount
,
562 const VkBuffer
* pBuffers
,
563 const VkDeviceSize
* pOffsets
)
565 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
566 struct anv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
568 /* We have to defer setting up vertex buffer since we need the buffer
569 * stride from the pipeline. */
571 assert(startBinding
+ bindingCount
< MAX_VBS
);
572 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
573 vb
[startBinding
+ i
].buffer
= anv_buffer_from_handle(pBuffers
[i
]);
574 vb
[startBinding
+ i
].offset
= pOffsets
[i
];
575 cmd_buffer
->state
.vb_dirty
|= 1 << (startBinding
+ i
);
580 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
581 struct anv_state state
, struct anv_bo
*bo
, uint32_t offset
)
583 /* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and
584 * 9 for gen8+. We only write the first dword for gen8+ here and rely on
585 * the initial state to set the high bits to 0. */
587 const uint32_t dword
= cmd_buffer
->device
->info
.gen
< 8 ? 1 : 8;
589 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
590 state
.offset
+ dword
* 4, bo
, offset
);
593 const struct anv_format
*
594 anv_format_for_descriptor_type(VkDescriptorType type
)
597 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
598 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
599 return anv_format_for_vk_format(VK_FORMAT_R32G32B32A32_SFLOAT
);
601 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
602 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
603 return anv_format_for_vk_format(VK_FORMAT_UNDEFINED
);
606 unreachable("Invalid descriptor type");
611 anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
612 gl_shader_stage stage
,
613 struct anv_state
*bt_state
)
615 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
616 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
617 struct anv_pipeline_layout
*layout
;
618 uint32_t color_count
, bias
, state_offset
;
621 case MESA_SHADER_FRAGMENT
:
622 layout
= cmd_buffer
->state
.pipeline
->layout
;
624 color_count
= subpass
->color_count
;
626 case MESA_SHADER_COMPUTE
:
627 layout
= cmd_buffer
->state
.compute_pipeline
->layout
;
632 layout
= cmd_buffer
->state
.pipeline
->layout
;
638 /* This is a little awkward: layout can be NULL but we still have to
639 * allocate and set a binding table for the PS stage for render
641 uint32_t surface_count
= layout
? layout
->stage
[stage
].surface_count
: 0;
643 if (color_count
+ surface_count
== 0) {
644 *bt_state
= (struct anv_state
) { 0, };
648 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
649 bias
+ surface_count
,
651 uint32_t *bt_map
= bt_state
->map
;
653 if (bt_state
->map
== NULL
)
654 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
656 for (uint32_t a
= 0; a
< color_count
; a
++) {
657 const struct anv_image_view
*iview
=
658 fb
->attachments
[subpass
->color_attachments
[a
]];
660 assert(iview
->color_rt_surface_state
.alloc_size
);
661 bt_map
[a
] = iview
->color_rt_surface_state
.offset
+ state_offset
;
662 add_surface_state_reloc(cmd_buffer
, iview
->color_rt_surface_state
,
663 iview
->bo
, iview
->offset
);
666 if (stage
== MESA_SHADER_COMPUTE
&&
667 cmd_buffer
->state
.compute_pipeline
->cs_prog_data
.uses_num_work_groups
) {
668 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
669 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
671 struct anv_state surface_state
;
673 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
675 const struct anv_format
*format
=
676 anv_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
677 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
.map
,
678 format
->surface_format
, bo_offset
, 12, 1);
680 if (!cmd_buffer
->device
->info
.has_llc
)
681 anv_state_clflush(surface_state
);
683 bt_map
[0] = surface_state
.offset
+ state_offset
;
684 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
690 if (layout
->stage
[stage
].image_count
> 0) {
692 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
693 if (result
!= VK_SUCCESS
)
696 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
700 for (uint32_t s
= 0; s
< layout
->stage
[stage
].surface_count
; s
++) {
701 struct anv_pipeline_binding
*binding
=
702 &layout
->stage
[stage
].surface_to_descriptor
[s
];
703 struct anv_descriptor_set
*set
=
704 cmd_buffer
->state
.descriptors
[binding
->set
];
705 struct anv_descriptor
*desc
= &set
->descriptors
[binding
->offset
];
707 struct anv_state surface_state
;
711 switch (desc
->type
) {
712 case VK_DESCRIPTOR_TYPE_SAMPLER
:
713 /* Nothing for us to do here */
716 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
717 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
718 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
719 surface_state
= desc
->image_view
->nonrt_surface_state
;
720 assert(surface_state
.alloc_size
);
721 bo
= desc
->image_view
->bo
;
722 bo_offset
= desc
->image_view
->offset
;
725 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
726 surface_state
= desc
->image_view
->storage_surface_state
;
727 assert(surface_state
.alloc_size
);
728 bo
= desc
->image_view
->bo
;
729 bo_offset
= desc
->image_view
->offset
;
731 struct brw_image_param
*image_param
=
732 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
734 anv_image_view_fill_image_param(cmd_buffer
->device
, desc
->image_view
,
736 image_param
->surface_idx
= bias
+ s
;
740 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
741 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
742 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
743 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
744 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
745 surface_state
= desc
->buffer_view
->surface_state
;
746 assert(surface_state
.alloc_size
);
747 bo
= desc
->buffer_view
->bo
;
748 bo_offset
= desc
->buffer_view
->offset
;
751 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
752 surface_state
= desc
->buffer_view
->storage_surface_state
;
753 assert(surface_state
.alloc_size
);
754 bo
= desc
->buffer_view
->bo
;
755 bo_offset
= desc
->buffer_view
->offset
;
757 struct brw_image_param
*image_param
=
758 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
760 anv_buffer_view_fill_image_param(cmd_buffer
->device
, desc
->buffer_view
,
762 image_param
->surface_idx
= bias
+ s
;
766 assert(!"Invalid descriptor type");
770 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
771 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
773 assert(image
== layout
->stage
[stage
].image_count
);
776 if (!cmd_buffer
->device
->info
.has_llc
)
777 anv_state_clflush(*bt_state
);
783 anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
784 gl_shader_stage stage
, struct anv_state
*state
)
786 struct anv_pipeline_layout
*layout
;
787 uint32_t sampler_count
;
789 if (stage
== MESA_SHADER_COMPUTE
)
790 layout
= cmd_buffer
->state
.compute_pipeline
->layout
;
792 layout
= cmd_buffer
->state
.pipeline
->layout
;
794 sampler_count
= layout
? layout
->stage
[stage
].sampler_count
: 0;
795 if (sampler_count
== 0) {
796 *state
= (struct anv_state
) { 0, };
800 uint32_t size
= sampler_count
* 16;
801 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
803 if (state
->map
== NULL
)
804 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
806 for (uint32_t s
= 0; s
< layout
->stage
[stage
].sampler_count
; s
++) {
807 struct anv_pipeline_binding
*binding
=
808 &layout
->stage
[stage
].sampler_to_descriptor
[s
];
809 struct anv_descriptor_set
*set
=
810 cmd_buffer
->state
.descriptors
[binding
->set
];
811 struct anv_descriptor
*desc
= &set
->descriptors
[binding
->offset
];
813 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
814 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
817 struct anv_sampler
*sampler
= desc
->sampler
;
819 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
820 * happens to be zero.
825 memcpy(state
->map
+ (s
* 16),
826 sampler
->state
, sizeof(sampler
->state
));
829 if (!cmd_buffer
->device
->info
.has_llc
)
830 anv_state_clflush(*state
);
836 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
837 const void *data
, uint32_t size
, uint32_t alignment
)
839 struct anv_state state
;
841 state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, alignment
);
842 memcpy(state
.map
, data
, size
);
844 if (!cmd_buffer
->device
->info
.has_llc
)
845 anv_state_clflush(state
);
847 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state
.map
, size
));
853 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
854 uint32_t *a
, uint32_t *b
,
855 uint32_t dwords
, uint32_t alignment
)
857 struct anv_state state
;
860 state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
861 dwords
* 4, alignment
);
863 for (uint32_t i
= 0; i
< dwords
; i
++)
866 if (!cmd_buffer
->device
->info
.has_llc
)
867 anv_state_clflush(state
);
869 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p
, dwords
* 4));
875 anv_cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
876 struct anv_subpass
*subpass
)
878 switch (cmd_buffer
->device
->info
.gen
) {
880 gen7_cmd_buffer_begin_subpass(cmd_buffer
, subpass
);
883 gen8_cmd_buffer_begin_subpass(cmd_buffer
, subpass
);
886 gen9_cmd_buffer_begin_subpass(cmd_buffer
, subpass
);
889 unreachable("unsupported gen\n");
894 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
895 gl_shader_stage stage
)
897 struct anv_push_constants
*data
=
898 cmd_buffer
->state
.push_constants
[stage
];
899 struct brw_stage_prog_data
*prog_data
=
900 cmd_buffer
->state
.pipeline
->prog_data
[stage
];
902 /* If we don't actually have any push constants, bail. */
903 if (data
== NULL
|| prog_data
->nr_params
== 0)
904 return (struct anv_state
) { .offset
= 0 };
906 struct anv_state state
=
907 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
908 prog_data
->nr_params
* sizeof(float),
909 32 /* bottom 5 bits MBZ */);
911 /* Walk through the param array and fill the buffer with data */
912 uint32_t *u32_map
= state
.map
;
913 for (unsigned i
= 0; i
< prog_data
->nr_params
; i
++) {
914 uint32_t offset
= (uintptr_t)prog_data
->param
[i
];
915 u32_map
[i
] = *(uint32_t *)((uint8_t *)data
+ offset
);
918 if (!cmd_buffer
->device
->info
.has_llc
)
919 anv_state_clflush(state
);
925 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
927 struct anv_push_constants
*data
=
928 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
929 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
930 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
931 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
933 const unsigned local_id_dwords
= cs_prog_data
->local_invocation_id_regs
* 8;
934 const unsigned push_constant_data_size
=
935 (local_id_dwords
+ prog_data
->nr_params
) * 4;
936 const unsigned reg_aligned_constant_size
= ALIGN(push_constant_data_size
, 32);
937 const unsigned param_aligned_count
=
938 reg_aligned_constant_size
/ sizeof(uint32_t);
940 /* If we don't actually have any push constants, bail. */
941 if (reg_aligned_constant_size
== 0)
942 return (struct anv_state
) { .offset
= 0 };
944 const unsigned threads
= pipeline
->cs_thread_width_max
;
945 const unsigned total_push_constants_size
=
946 reg_aligned_constant_size
* threads
;
947 const unsigned push_constant_alignment
=
948 cmd_buffer
->device
->info
.gen
< 8 ? 32 : 64;
949 const unsigned aligned_total_push_constants_size
=
950 ALIGN(total_push_constants_size
, push_constant_alignment
);
951 struct anv_state state
=
952 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
953 aligned_total_push_constants_size
,
954 push_constant_alignment
);
956 /* Walk through the param array and fill the buffer with data */
957 uint32_t *u32_map
= state
.map
;
959 brw_cs_fill_local_id_payload(cs_prog_data
, u32_map
, threads
,
960 reg_aligned_constant_size
);
962 /* Setup uniform data for the first thread */
963 for (unsigned i
= 0; i
< prog_data
->nr_params
; i
++) {
964 uint32_t offset
= (uintptr_t)prog_data
->param
[i
];
965 u32_map
[local_id_dwords
+ i
] = *(uint32_t *)((uint8_t *)data
+ offset
);
968 /* Copy uniform data from the first thread to every other thread */
969 const size_t uniform_data_size
= prog_data
->nr_params
* sizeof(uint32_t);
970 for (unsigned t
= 1; t
< threads
; t
++) {
971 memcpy(&u32_map
[t
* param_aligned_count
+ local_id_dwords
],
972 &u32_map
[local_id_dwords
],
976 if (!cmd_buffer
->device
->info
.has_llc
)
977 anv_state_clflush(state
);
982 void anv_CmdPushConstants(
983 VkCommandBuffer commandBuffer
,
984 VkPipelineLayout layout
,
985 VkShaderStageFlags stageFlags
,
990 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
992 anv_foreach_stage(stage
, stageFlags
) {
993 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, client_data
);
995 memcpy(cmd_buffer
->state
.push_constants
[stage
]->client_data
+ offset
,
999 cmd_buffer
->state
.push_constants_dirty
|= stageFlags
;
1002 void anv_CmdExecuteCommands(
1003 VkCommandBuffer commandBuffer
,
1004 uint32_t commandBuffersCount
,
1005 const VkCommandBuffer
* pCmdBuffers
)
1007 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1009 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1011 anv_assert(primary
->state
.subpass
== &primary
->state
.pass
->subpasses
[0]);
1013 for (uint32_t i
= 0; i
< commandBuffersCount
; i
++) {
1014 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1016 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1018 anv_cmd_buffer_add_secondary(primary
, secondary
);
1022 VkResult
anv_CreateCommandPool(
1024 const VkCommandPoolCreateInfo
* pCreateInfo
,
1025 const VkAllocationCallbacks
* pAllocator
,
1026 VkCommandPool
* pCmdPool
)
1028 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1029 struct anv_cmd_pool
*pool
;
1031 pool
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
1032 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1034 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1037 pool
->alloc
= *pAllocator
;
1039 pool
->alloc
= device
->alloc
;
1041 list_inithead(&pool
->cmd_buffers
);
1043 *pCmdPool
= anv_cmd_pool_to_handle(pool
);
1048 void anv_DestroyCommandPool(
1050 VkCommandPool commandPool
,
1051 const VkAllocationCallbacks
* pAllocator
)
1053 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1054 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, commandPool
);
1056 anv_ResetCommandPool(_device
, commandPool
, 0);
1058 anv_free2(&device
->alloc
, pAllocator
, pool
);
1061 VkResult
anv_ResetCommandPool(
1063 VkCommandPool commandPool
,
1064 VkCommandPoolResetFlags flags
)
1066 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, commandPool
);
1068 list_for_each_entry_safe(struct anv_cmd_buffer
, cmd_buffer
,
1069 &pool
->cmd_buffers
, pool_link
) {
1070 anv_cmd_buffer_destroy(cmd_buffer
);
1077 * Return NULL if the current subpass has no depthstencil attachment.
1079 const struct anv_image_view
*
1080 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
)
1082 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1083 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1085 if (subpass
->depth_stencil_attachment
== VK_ATTACHMENT_UNUSED
)
1088 const struct anv_image_view
*iview
=
1089 fb
->attachments
[subpass
->depth_stencil_attachment
];
1091 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1092 VK_IMAGE_ASPECT_STENCIL_BIT
));