anv/pipeline: Handle output lowering in anv_pipeline instead of spirv_to_nir
[mesa.git] / src / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 /** \file anv_cmd_buffer.c
33 *
34 * This file contains all of the stuff for emitting commands into a command
35 * buffer. This includes implementations of most of the vkCmd*
36 * entrypoints. This file is concerned entirely with state emission and
37 * not with the command buffer data structure itself. As far as this file
38 * is concerned, most of anv_cmd_buffer is magic.
39 */
40
41 /* TODO: These are taken from GLES. We should check the Vulkan spec */
42 const struct anv_dynamic_state default_dynamic_state = {
43 .viewport = {
44 .count = 0,
45 },
46 .scissor = {
47 .count = 0,
48 },
49 .line_width = 1.0f,
50 .depth_bias = {
51 .bias = 0.0f,
52 .clamp = 0.0f,
53 .slope = 0.0f,
54 },
55 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
56 .depth_bounds = {
57 .min = 0.0f,
58 .max = 1.0f,
59 },
60 .stencil_compare_mask = {
61 .front = ~0u,
62 .back = ~0u,
63 },
64 .stencil_write_mask = {
65 .front = ~0u,
66 .back = ~0u,
67 },
68 .stencil_reference = {
69 .front = 0u,
70 .back = 0u,
71 },
72 };
73
74 void
75 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
76 const struct anv_dynamic_state *src,
77 uint32_t copy_mask)
78 {
79 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
80 dest->viewport.count = src->viewport.count;
81 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
82 src->viewport.count);
83 }
84
85 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
86 dest->scissor.count = src->scissor.count;
87 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
88 src->scissor.count);
89 }
90
91 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
92 dest->line_width = src->line_width;
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
95 dest->depth_bias = src->depth_bias;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
98 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
101 dest->depth_bounds = src->depth_bounds;
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
104 dest->stencil_compare_mask = src->stencil_compare_mask;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
107 dest->stencil_write_mask = src->stencil_write_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
110 dest->stencil_reference = src->stencil_reference;
111 }
112
113 static void
114 anv_cmd_state_init(struct anv_cmd_state *state)
115 {
116 memset(&state->descriptors, 0, sizeof(state->descriptors));
117 memset(&state->push_constants, 0, sizeof(state->push_constants));
118
119 state->dirty = ~0;
120 state->vb_dirty = 0;
121 state->descriptors_dirty = 0;
122 state->push_constants_dirty = 0;
123 state->pipeline = NULL;
124 state->restart_index = UINT32_MAX;
125 state->dynamic = default_dynamic_state;
126
127 state->gen7.index_buffer = NULL;
128 }
129
130 static VkResult
131 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
132 gl_shader_stage stage, uint32_t size)
133 {
134 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
135
136 if (*ptr == NULL) {
137 *ptr = anv_alloc(&cmd_buffer->pool->alloc, size, 8,
138 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
139 if (*ptr == NULL)
140 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
141 } else if ((*ptr)->size < size) {
142 *ptr = anv_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
143 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
144 if (*ptr == NULL)
145 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
146 }
147 (*ptr)->size = size;
148
149 return VK_SUCCESS;
150 }
151
152 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
153 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
154 (offsetof(struct anv_push_constants, field) + \
155 sizeof(cmd_buffer->state.push_constants[0]->field)))
156
157 static VkResult anv_create_cmd_buffer(
158 struct anv_device * device,
159 struct anv_cmd_pool * pool,
160 VkCommandBufferLevel level,
161 VkCommandBuffer* pCommandBuffer)
162 {
163 struct anv_cmd_buffer *cmd_buffer;
164 VkResult result;
165
166 cmd_buffer = anv_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
168 if (cmd_buffer == NULL)
169 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
170
171 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
172 cmd_buffer->device = device;
173 cmd_buffer->pool = pool;
174
175 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
176 if (result != VK_SUCCESS)
177 goto fail;
178
179 anv_state_stream_init(&cmd_buffer->surface_state_stream,
180 &device->surface_state_block_pool);
181 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
182 &device->dynamic_state_block_pool);
183
184 cmd_buffer->level = level;
185 cmd_buffer->usage_flags = 0;
186
187 anv_cmd_state_init(&cmd_buffer->state);
188
189 if (pool) {
190 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
191 } else {
192 /* Init the pool_link so we can safefly call list_del when we destroy
193 * the command buffer
194 */
195 list_inithead(&cmd_buffer->pool_link);
196 }
197
198 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
199
200 return VK_SUCCESS;
201
202 fail:
203 anv_free(&cmd_buffer->pool->alloc, cmd_buffer);
204
205 return result;
206 }
207
208 VkResult anv_AllocateCommandBuffers(
209 VkDevice _device,
210 const VkCommandBufferAllocateInfo* pAllocateInfo,
211 VkCommandBuffer* pCommandBuffers)
212 {
213 ANV_FROM_HANDLE(anv_device, device, _device);
214 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
215
216 VkResult result = VK_SUCCESS;
217 uint32_t i;
218
219 for (i = 0; i < pAllocateInfo->bufferCount; i++) {
220 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
221 &pCommandBuffers[i]);
222 if (result != VK_SUCCESS)
223 break;
224 }
225
226 if (result != VK_SUCCESS)
227 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
228 i, pCommandBuffers);
229
230 return result;
231 }
232
233 static void
234 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
235 {
236 list_del(&cmd_buffer->pool_link);
237
238 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
239
240 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
241 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
242
243 anv_free(&cmd_buffer->pool->alloc, cmd_buffer);
244 }
245
246 void anv_FreeCommandBuffers(
247 VkDevice device,
248 VkCommandPool commandPool,
249 uint32_t commandBufferCount,
250 const VkCommandBuffer* pCommandBuffers)
251 {
252 for (uint32_t i = 0; i < commandBufferCount; i++) {
253 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
254
255 anv_cmd_buffer_destroy(cmd_buffer);
256 }
257 }
258
259 VkResult anv_ResetCommandBuffer(
260 VkCommandBuffer commandBuffer,
261 VkCommandBufferResetFlags flags)
262 {
263 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
264
265 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
266
267 anv_cmd_state_init(&cmd_buffer->state);
268
269 return VK_SUCCESS;
270 }
271
272 void
273 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
274 {
275 switch (cmd_buffer->device->info.gen) {
276 case 7:
277 if (cmd_buffer->device->info.is_haswell)
278 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
279 else
280 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
281 case 8:
282 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
283 case 9:
284 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
285 default:
286 unreachable("unsupported gen\n");
287 }
288 }
289
290 VkResult anv_BeginCommandBuffer(
291 VkCommandBuffer commandBuffer,
292 const VkCommandBufferBeginInfo* pBeginInfo)
293 {
294 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
295
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
297
298 cmd_buffer->usage_flags = pBeginInfo->flags;
299
300 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
301 !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
302
303 if (cmd_buffer->usage_flags &
304 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
305 cmd_buffer->state.framebuffer =
306 anv_framebuffer_from_handle(pBeginInfo->framebuffer);
307 cmd_buffer->state.pass =
308 anv_render_pass_from_handle(pBeginInfo->renderPass);
309
310 struct anv_subpass *subpass =
311 &cmd_buffer->state.pass->subpasses[pBeginInfo->subpass];
312
313 anv_cmd_buffer_begin_subpass(cmd_buffer, subpass);
314 }
315
316 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
317 cmd_buffer->state.current_pipeline = UINT32_MAX;
318
319 return VK_SUCCESS;
320 }
321
322 VkResult anv_EndCommandBuffer(
323 VkCommandBuffer commandBuffer)
324 {
325 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
326 struct anv_device *device = cmd_buffer->device;
327
328 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
329
330 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
331 /* The algorithm used to compute the validate list is not threadsafe as
332 * it uses the bo->index field. We have to lock the device around it.
333 * Fortunately, the chances for contention here are probably very low.
334 */
335 pthread_mutex_lock(&device->mutex);
336 anv_cmd_buffer_prepare_execbuf(cmd_buffer);
337 pthread_mutex_unlock(&device->mutex);
338 }
339
340 return VK_SUCCESS;
341 }
342
343 void anv_CmdBindPipeline(
344 VkCommandBuffer commandBuffer,
345 VkPipelineBindPoint pipelineBindPoint,
346 VkPipeline _pipeline)
347 {
348 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
349 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
350
351 switch (pipelineBindPoint) {
352 case VK_PIPELINE_BIND_POINT_COMPUTE:
353 cmd_buffer->state.compute_pipeline = pipeline;
354 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
355 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
356 break;
357
358 case VK_PIPELINE_BIND_POINT_GRAPHICS:
359 cmd_buffer->state.pipeline = pipeline;
360 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
361 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
362 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
363
364 /* Apply the dynamic state from the pipeline */
365 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
366 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
367 &pipeline->dynamic_state,
368 pipeline->dynamic_state_mask);
369 break;
370
371 default:
372 assert(!"invalid bind point");
373 break;
374 }
375 }
376
377 void anv_CmdSetViewport(
378 VkCommandBuffer commandBuffer,
379 uint32_t viewportCount,
380 const VkViewport* pViewports)
381 {
382 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
383
384 cmd_buffer->state.dynamic.viewport.count = viewportCount;
385 memcpy(cmd_buffer->state.dynamic.viewport.viewports,
386 pViewports, viewportCount * sizeof(*pViewports));
387
388 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
389 }
390
391 void anv_CmdSetScissor(
392 VkCommandBuffer commandBuffer,
393 uint32_t scissorCount,
394 const VkRect2D* pScissors)
395 {
396 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
397
398 cmd_buffer->state.dynamic.scissor.count = scissorCount;
399 memcpy(cmd_buffer->state.dynamic.scissor.scissors,
400 pScissors, scissorCount * sizeof(*pScissors));
401
402 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
403 }
404
405 void anv_CmdSetLineWidth(
406 VkCommandBuffer commandBuffer,
407 float lineWidth)
408 {
409 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
410
411 cmd_buffer->state.dynamic.line_width = lineWidth;
412 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
413 }
414
415 void anv_CmdSetDepthBias(
416 VkCommandBuffer commandBuffer,
417 float depthBiasConstantFactor,
418 float depthBiasClamp,
419 float depthBiasSlopeFactor)
420 {
421 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
422
423 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
424 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
425 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
426
427 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
428 }
429
430 void anv_CmdSetBlendConstants(
431 VkCommandBuffer commandBuffer,
432 const float blendConstants[4])
433 {
434 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
435
436 memcpy(cmd_buffer->state.dynamic.blend_constants,
437 blendConstants, sizeof(float) * 4);
438
439 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
440 }
441
442 void anv_CmdSetDepthBounds(
443 VkCommandBuffer commandBuffer,
444 float minDepthBounds,
445 float maxDepthBounds)
446 {
447 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
448
449 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
450 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
451
452 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
453 }
454
455 void anv_CmdSetStencilCompareMask(
456 VkCommandBuffer commandBuffer,
457 VkStencilFaceFlags faceMask,
458 uint32_t compareMask)
459 {
460 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
461
462 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
463 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
464 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
465 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
466
467 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
468 }
469
470 void anv_CmdSetStencilWriteMask(
471 VkCommandBuffer commandBuffer,
472 VkStencilFaceFlags faceMask,
473 uint32_t writeMask)
474 {
475 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
476
477 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
478 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
479 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
480 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
481
482 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
483 }
484
485 void anv_CmdSetStencilReference(
486 VkCommandBuffer commandBuffer,
487 VkStencilFaceFlags faceMask,
488 uint32_t reference)
489 {
490 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
491
492 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
493 cmd_buffer->state.dynamic.stencil_reference.front = reference;
494 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
495 cmd_buffer->state.dynamic.stencil_reference.back = reference;
496
497 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
498 }
499
500 void anv_CmdBindDescriptorSets(
501 VkCommandBuffer commandBuffer,
502 VkPipelineBindPoint pipelineBindPoint,
503 VkPipelineLayout _layout,
504 uint32_t firstSet,
505 uint32_t descriptorSetCount,
506 const VkDescriptorSet* pDescriptorSets,
507 uint32_t dynamicOffsetCount,
508 const uint32_t* pDynamicOffsets)
509 {
510 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
511 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
512 struct anv_descriptor_set_layout *set_layout;
513
514 assert(firstSet + descriptorSetCount < MAX_SETS);
515
516 uint32_t dynamic_slot = 0;
517 for (uint32_t i = 0; i < descriptorSetCount; i++) {
518 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
519 set_layout = layout->set[firstSet + i].layout;
520
521 if (cmd_buffer->state.descriptors[firstSet + i] != set) {
522 cmd_buffer->state.descriptors[firstSet + i] = set;
523 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
524 }
525
526 if (set_layout->dynamic_offset_count > 0) {
527 anv_foreach_stage(s, set_layout->shader_stages) {
528 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, s, dynamic);
529
530 struct anv_push_constants *push =
531 cmd_buffer->state.push_constants[s];
532
533 unsigned d = layout->set[firstSet + i].dynamic_offset_start;
534 const uint32_t *offsets = pDynamicOffsets + dynamic_slot;
535 struct anv_descriptor *desc = set->descriptors;
536
537 for (unsigned b = 0; b < set_layout->binding_count; b++) {
538 if (set_layout->binding[b].dynamic_offset_index < 0)
539 continue;
540
541 unsigned array_size = set_layout->binding[b].array_size;
542 for (unsigned j = 0; j < array_size; j++) {
543 uint32_t range = 0;
544 if (desc->buffer_view)
545 range = desc->buffer_view->range;
546 push->dynamic[d].offset = *(offsets++);
547 push->dynamic[d].range = range;
548 desc++;
549 d++;
550 }
551 }
552 }
553 cmd_buffer->state.push_constants_dirty |= set_layout->shader_stages;
554 }
555 }
556 }
557
558 void anv_CmdBindVertexBuffers(
559 VkCommandBuffer commandBuffer,
560 uint32_t startBinding,
561 uint32_t bindingCount,
562 const VkBuffer* pBuffers,
563 const VkDeviceSize* pOffsets)
564 {
565 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
566 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
567
568 /* We have to defer setting up vertex buffer since we need the buffer
569 * stride from the pipeline. */
570
571 assert(startBinding + bindingCount < MAX_VBS);
572 for (uint32_t i = 0; i < bindingCount; i++) {
573 vb[startBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
574 vb[startBinding + i].offset = pOffsets[i];
575 cmd_buffer->state.vb_dirty |= 1 << (startBinding + i);
576 }
577 }
578
579 static void
580 add_surface_state_reloc(struct anv_cmd_buffer *cmd_buffer,
581 struct anv_state state, struct anv_bo *bo, uint32_t offset)
582 {
583 /* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and
584 * 9 for gen8+. We only write the first dword for gen8+ here and rely on
585 * the initial state to set the high bits to 0. */
586
587 const uint32_t dword = cmd_buffer->device->info.gen < 8 ? 1 : 8;
588
589 anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
590 state.offset + dword * 4, bo, offset);
591 }
592
593 const struct anv_format *
594 anv_format_for_descriptor_type(VkDescriptorType type)
595 {
596 switch (type) {
597 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
598 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
599 return anv_format_for_vk_format(VK_FORMAT_R32G32B32A32_SFLOAT);
600
601 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
602 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
603 return anv_format_for_vk_format(VK_FORMAT_UNDEFINED);
604
605 default:
606 unreachable("Invalid descriptor type");
607 }
608 }
609
610 VkResult
611 anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
612 gl_shader_stage stage,
613 struct anv_state *bt_state)
614 {
615 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
616 struct anv_subpass *subpass = cmd_buffer->state.subpass;
617 struct anv_pipeline_layout *layout;
618 uint32_t color_count, bias, state_offset;
619
620 switch (stage) {
621 case MESA_SHADER_FRAGMENT:
622 layout = cmd_buffer->state.pipeline->layout;
623 bias = MAX_RTS;
624 color_count = subpass->color_count;
625 break;
626 case MESA_SHADER_COMPUTE:
627 layout = cmd_buffer->state.compute_pipeline->layout;
628 bias = 1;
629 color_count = 0;
630 break;
631 default:
632 layout = cmd_buffer->state.pipeline->layout;
633 bias = 0;
634 color_count = 0;
635 break;
636 }
637
638 /* This is a little awkward: layout can be NULL but we still have to
639 * allocate and set a binding table for the PS stage for render
640 * targets. */
641 uint32_t surface_count = layout ? layout->stage[stage].surface_count : 0;
642
643 if (color_count + surface_count == 0) {
644 *bt_state = (struct anv_state) { 0, };
645 return VK_SUCCESS;
646 }
647
648 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
649 bias + surface_count,
650 &state_offset);
651 uint32_t *bt_map = bt_state->map;
652
653 if (bt_state->map == NULL)
654 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
655
656 for (uint32_t a = 0; a < color_count; a++) {
657 const struct anv_image_view *iview =
658 fb->attachments[subpass->color_attachments[a]];
659
660 assert(iview->color_rt_surface_state.alloc_size);
661 bt_map[a] = iview->color_rt_surface_state.offset + state_offset;
662 add_surface_state_reloc(cmd_buffer, iview->color_rt_surface_state,
663 iview->bo, iview->offset);
664 }
665
666 if (stage == MESA_SHADER_COMPUTE &&
667 cmd_buffer->state.compute_pipeline->cs_prog_data.uses_num_work_groups) {
668 struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo;
669 uint32_t bo_offset = cmd_buffer->state.num_workgroups_offset;
670
671 struct anv_state surface_state;
672 surface_state =
673 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
674
675 const struct anv_format *format =
676 anv_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
677 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state.map,
678 format->surface_format, bo_offset, 12, 1);
679
680 if (!cmd_buffer->device->info.has_llc)
681 anv_state_clflush(surface_state);
682
683 bt_map[0] = surface_state.offset + state_offset;
684 add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset);
685 }
686
687 if (layout == NULL)
688 goto out;
689
690 if (layout->stage[stage].image_count > 0) {
691 VkResult result =
692 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
693 if (result != VK_SUCCESS)
694 return result;
695
696 cmd_buffer->state.push_constants_dirty |= 1 << stage;
697 }
698
699 uint32_t image = 0;
700 for (uint32_t s = 0; s < layout->stage[stage].surface_count; s++) {
701 struct anv_pipeline_binding *binding =
702 &layout->stage[stage].surface_to_descriptor[s];
703 struct anv_descriptor_set *set =
704 cmd_buffer->state.descriptors[binding->set];
705 struct anv_descriptor *desc = &set->descriptors[binding->offset];
706
707 struct anv_state surface_state;
708 struct anv_bo *bo;
709 uint32_t bo_offset;
710
711 switch (desc->type) {
712 case VK_DESCRIPTOR_TYPE_SAMPLER:
713 /* Nothing for us to do here */
714 continue;
715
716 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
717 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
718 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
719 surface_state = desc->image_view->nonrt_surface_state;
720 assert(surface_state.alloc_size);
721 bo = desc->image_view->bo;
722 bo_offset = desc->image_view->offset;
723 break;
724
725 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
726 surface_state = desc->image_view->storage_surface_state;
727 assert(surface_state.alloc_size);
728 bo = desc->image_view->bo;
729 bo_offset = desc->image_view->offset;
730
731 struct brw_image_param *image_param =
732 &cmd_buffer->state.push_constants[stage]->images[image++];
733
734 anv_image_view_fill_image_param(cmd_buffer->device, desc->image_view,
735 image_param);
736 image_param->surface_idx = bias + s;
737 break;
738 }
739
740 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
741 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
742 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
743 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
744 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
745 surface_state = desc->buffer_view->surface_state;
746 assert(surface_state.alloc_size);
747 bo = desc->buffer_view->bo;
748 bo_offset = desc->buffer_view->offset;
749 break;
750
751 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
752 surface_state = desc->buffer_view->storage_surface_state;
753 assert(surface_state.alloc_size);
754 bo = desc->buffer_view->bo;
755 bo_offset = desc->buffer_view->offset;
756
757 struct brw_image_param *image_param =
758 &cmd_buffer->state.push_constants[stage]->images[image++];
759
760 anv_buffer_view_fill_image_param(cmd_buffer->device, desc->buffer_view,
761 image_param);
762 image_param->surface_idx = bias + s;
763 break;
764
765 default:
766 assert(!"Invalid descriptor type");
767 continue;
768 }
769
770 bt_map[bias + s] = surface_state.offset + state_offset;
771 add_surface_state_reloc(cmd_buffer, surface_state, bo, bo_offset);
772 }
773 assert(image == layout->stage[stage].image_count);
774
775 out:
776 if (!cmd_buffer->device->info.has_llc)
777 anv_state_clflush(*bt_state);
778
779 return VK_SUCCESS;
780 }
781
782 VkResult
783 anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
784 gl_shader_stage stage, struct anv_state *state)
785 {
786 struct anv_pipeline_layout *layout;
787 uint32_t sampler_count;
788
789 if (stage == MESA_SHADER_COMPUTE)
790 layout = cmd_buffer->state.compute_pipeline->layout;
791 else
792 layout = cmd_buffer->state.pipeline->layout;
793
794 sampler_count = layout ? layout->stage[stage].sampler_count : 0;
795 if (sampler_count == 0) {
796 *state = (struct anv_state) { 0, };
797 return VK_SUCCESS;
798 }
799
800 uint32_t size = sampler_count * 16;
801 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
802
803 if (state->map == NULL)
804 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
805
806 for (uint32_t s = 0; s < layout->stage[stage].sampler_count; s++) {
807 struct anv_pipeline_binding *binding =
808 &layout->stage[stage].sampler_to_descriptor[s];
809 struct anv_descriptor_set *set =
810 cmd_buffer->state.descriptors[binding->set];
811 struct anv_descriptor *desc = &set->descriptors[binding->offset];
812
813 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
814 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
815 continue;
816
817 struct anv_sampler *sampler = desc->sampler;
818
819 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
820 * happens to be zero.
821 */
822 if (sampler == NULL)
823 continue;
824
825 memcpy(state->map + (s * 16),
826 sampler->state, sizeof(sampler->state));
827 }
828
829 if (!cmd_buffer->device->info.has_llc)
830 anv_state_clflush(*state);
831
832 return VK_SUCCESS;
833 }
834
835 struct anv_state
836 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
837 const void *data, uint32_t size, uint32_t alignment)
838 {
839 struct anv_state state;
840
841 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
842 memcpy(state.map, data, size);
843
844 if (!cmd_buffer->device->info.has_llc)
845 anv_state_clflush(state);
846
847 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
848
849 return state;
850 }
851
852 struct anv_state
853 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
854 uint32_t *a, uint32_t *b,
855 uint32_t dwords, uint32_t alignment)
856 {
857 struct anv_state state;
858 uint32_t *p;
859
860 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
861 dwords * 4, alignment);
862 p = state.map;
863 for (uint32_t i = 0; i < dwords; i++)
864 p[i] = a[i] | b[i];
865
866 if (!cmd_buffer->device->info.has_llc)
867 anv_state_clflush(state);
868
869 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
870
871 return state;
872 }
873
874 void
875 anv_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
876 struct anv_subpass *subpass)
877 {
878 switch (cmd_buffer->device->info.gen) {
879 case 7:
880 gen7_cmd_buffer_begin_subpass(cmd_buffer, subpass);
881 break;
882 case 8:
883 gen8_cmd_buffer_begin_subpass(cmd_buffer, subpass);
884 break;
885 case 9:
886 gen9_cmd_buffer_begin_subpass(cmd_buffer, subpass);
887 break;
888 default:
889 unreachable("unsupported gen\n");
890 }
891 }
892
893 struct anv_state
894 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
895 gl_shader_stage stage)
896 {
897 struct anv_push_constants *data =
898 cmd_buffer->state.push_constants[stage];
899 struct brw_stage_prog_data *prog_data =
900 cmd_buffer->state.pipeline->prog_data[stage];
901
902 /* If we don't actually have any push constants, bail. */
903 if (data == NULL || prog_data->nr_params == 0)
904 return (struct anv_state) { .offset = 0 };
905
906 struct anv_state state =
907 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
908 prog_data->nr_params * sizeof(float),
909 32 /* bottom 5 bits MBZ */);
910
911 /* Walk through the param array and fill the buffer with data */
912 uint32_t *u32_map = state.map;
913 for (unsigned i = 0; i < prog_data->nr_params; i++) {
914 uint32_t offset = (uintptr_t)prog_data->param[i];
915 u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
916 }
917
918 if (!cmd_buffer->device->info.has_llc)
919 anv_state_clflush(state);
920
921 return state;
922 }
923
924 struct anv_state
925 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
926 {
927 struct anv_push_constants *data =
928 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
929 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
930 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
931 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
932
933 const unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
934 const unsigned push_constant_data_size =
935 (local_id_dwords + prog_data->nr_params) * 4;
936 const unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
937 const unsigned param_aligned_count =
938 reg_aligned_constant_size / sizeof(uint32_t);
939
940 /* If we don't actually have any push constants, bail. */
941 if (reg_aligned_constant_size == 0)
942 return (struct anv_state) { .offset = 0 };
943
944 const unsigned threads = pipeline->cs_thread_width_max;
945 const unsigned total_push_constants_size =
946 reg_aligned_constant_size * threads;
947 const unsigned push_constant_alignment =
948 cmd_buffer->device->info.gen < 8 ? 32 : 64;
949 const unsigned aligned_total_push_constants_size =
950 ALIGN(total_push_constants_size, push_constant_alignment);
951 struct anv_state state =
952 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
953 aligned_total_push_constants_size,
954 push_constant_alignment);
955
956 /* Walk through the param array and fill the buffer with data */
957 uint32_t *u32_map = state.map;
958
959 brw_cs_fill_local_id_payload(cs_prog_data, u32_map, threads,
960 reg_aligned_constant_size);
961
962 /* Setup uniform data for the first thread */
963 for (unsigned i = 0; i < prog_data->nr_params; i++) {
964 uint32_t offset = (uintptr_t)prog_data->param[i];
965 u32_map[local_id_dwords + i] = *(uint32_t *)((uint8_t *)data + offset);
966 }
967
968 /* Copy uniform data from the first thread to every other thread */
969 const size_t uniform_data_size = prog_data->nr_params * sizeof(uint32_t);
970 for (unsigned t = 1; t < threads; t++) {
971 memcpy(&u32_map[t * param_aligned_count + local_id_dwords],
972 &u32_map[local_id_dwords],
973 uniform_data_size);
974 }
975
976 if (!cmd_buffer->device->info.has_llc)
977 anv_state_clflush(state);
978
979 return state;
980 }
981
982 void anv_CmdPushConstants(
983 VkCommandBuffer commandBuffer,
984 VkPipelineLayout layout,
985 VkShaderStageFlags stageFlags,
986 uint32_t offset,
987 uint32_t size,
988 const void* pValues)
989 {
990 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
991
992 anv_foreach_stage(stage, stageFlags) {
993 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, client_data);
994
995 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
996 pValues, size);
997 }
998
999 cmd_buffer->state.push_constants_dirty |= stageFlags;
1000 }
1001
1002 void anv_CmdExecuteCommands(
1003 VkCommandBuffer commandBuffer,
1004 uint32_t commandBuffersCount,
1005 const VkCommandBuffer* pCmdBuffers)
1006 {
1007 ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
1008
1009 assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1010
1011 anv_assert(primary->state.subpass == &primary->state.pass->subpasses[0]);
1012
1013 for (uint32_t i = 0; i < commandBuffersCount; i++) {
1014 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
1015
1016 assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
1017
1018 anv_cmd_buffer_add_secondary(primary, secondary);
1019 }
1020 }
1021
1022 VkResult anv_CreateCommandPool(
1023 VkDevice _device,
1024 const VkCommandPoolCreateInfo* pCreateInfo,
1025 const VkAllocationCallbacks* pAllocator,
1026 VkCommandPool* pCmdPool)
1027 {
1028 ANV_FROM_HANDLE(anv_device, device, _device);
1029 struct anv_cmd_pool *pool;
1030
1031 pool = anv_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
1032 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1033 if (pool == NULL)
1034 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1035
1036 if (pAllocator)
1037 pool->alloc = *pAllocator;
1038 else
1039 pool->alloc = device->alloc;
1040
1041 list_inithead(&pool->cmd_buffers);
1042
1043 *pCmdPool = anv_cmd_pool_to_handle(pool);
1044
1045 return VK_SUCCESS;
1046 }
1047
1048 void anv_DestroyCommandPool(
1049 VkDevice _device,
1050 VkCommandPool commandPool,
1051 const VkAllocationCallbacks* pAllocator)
1052 {
1053 ANV_FROM_HANDLE(anv_device, device, _device);
1054 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
1055
1056 anv_ResetCommandPool(_device, commandPool, 0);
1057
1058 anv_free2(&device->alloc, pAllocator, pool);
1059 }
1060
1061 VkResult anv_ResetCommandPool(
1062 VkDevice device,
1063 VkCommandPool commandPool,
1064 VkCommandPoolResetFlags flags)
1065 {
1066 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
1067
1068 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
1069 &pool->cmd_buffers, pool_link) {
1070 anv_cmd_buffer_destroy(cmd_buffer);
1071 }
1072
1073 return VK_SUCCESS;
1074 }
1075
1076 /**
1077 * Return NULL if the current subpass has no depthstencil attachment.
1078 */
1079 const struct anv_image_view *
1080 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
1081 {
1082 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1083 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1084
1085 if (subpass->depth_stencil_attachment == VK_ATTACHMENT_UNUSED)
1086 return NULL;
1087
1088 const struct anv_image_view *iview =
1089 fb->attachments[subpass->depth_stencil_attachment];
1090
1091 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1092 VK_IMAGE_ASPECT_STENCIL_BIT));
1093
1094 return iview;
1095 }