src/vulkan/anv_nir_apply_dynamic_offsets.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "anv_nir.h"
  25 #include "glsl/nir/nir_builder.h"
  26
  27 struct apply_dynamic_offsets_state {
  28    nir_shader *shader;
  29    nir_builder builder;
  30
  31    struct anv_pipeline_layout *layout;
  32
  33    uint32_t indices_start;
  34 };
  35
  36 static bool
  37 apply_dynamic_offsets_block(nir_block *block, void *void_state)
  38 {
  39    struct apply_dynamic_offsets_state *state = void_state;
  40    struct anv_descriptor_set_layout *set_layout;
  41
  42    nir_builder *b = &state->builder;
  43
  44    nir_foreach_instr_safe(block, instr) {
  45       if (instr->type != nir_instr_type_intrinsic)
  46          continue;
  47
  48       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  49
  50       unsigned block_idx_src;
  51       switch (intrin->intrinsic) {
  52       case nir_intrinsic_load_ubo:
  53       case nir_intrinsic_load_ubo_indirect:
  54       case nir_intrinsic_load_ssbo:
  55       case nir_intrinsic_load_ssbo_indirect:
  56          block_idx_src = 0;
  57          break;
  58       case nir_intrinsic_store_ssbo:
  59       case nir_intrinsic_store_ssbo_indirect:
  60          block_idx_src = 1;
  61          break;
  62       default:
  63          continue; /* the loop */
  64       }
  65
  66       nir_instr *res_instr = intrin->src[block_idx_src].ssa->parent_instr;
  67       assert(res_instr->type == nir_instr_type_intrinsic);
  68       nir_intrinsic_instr *res_intrin = nir_instr_as_intrinsic(res_instr);
  69       assert(res_intrin->intrinsic == nir_intrinsic_vulkan_resource_index);
  70
  71       unsigned set = res_intrin->const_index[0];
  72       unsigned binding = res_intrin->const_index[1];
  73
  74       set_layout = state->layout->set[set].layout;
  75       if (set_layout->binding[binding].dynamic_offset_index < 0)
  76          continue;
  77
  78       b->cursor = nir_before_instr(&intrin->instr);
  79
  80       int indirect_src;
  81       switch (intrin->intrinsic) {
  82       case nir_intrinsic_load_ubo_indirect:
  83       case nir_intrinsic_load_ssbo_indirect:
  84          indirect_src = 1;
  85          break;
  86       case nir_intrinsic_store_ssbo_indirect:
  87          indirect_src = 2;
  88          break;
  89       default:
  90          indirect_src = -1;
  91          break;
  92       }
  93
  94       /* First, we need to generate the uniform load for the buffer offset */
  95       uint32_t index = state->layout->set[set].dynamic_offset_start +
  96                        set_layout->binding[binding].dynamic_offset_index;
  97
  98       nir_const_value *const_arr_idx =
  99          nir_src_as_const_value(res_intrin->src[0]);
 100
 101       nir_intrinsic_op offset_load_op;
 102       if (const_arr_idx)
 103          offset_load_op = nir_intrinsic_load_uniform;
 104       else
 105          offset_load_op = nir_intrinsic_load_uniform_indirect;
 106
 107       nir_intrinsic_instr *offset_load =
 108          nir_intrinsic_instr_create(state->shader, offset_load_op);
 109       offset_load->num_components = 2;
 110       offset_load->const_index[0] = state->indices_start + index * 2;
 111
 112       if (const_arr_idx) {
 113          offset_load->const_index[1] = const_arr_idx->u[0] * 2;
 114       } else {
 115          offset_load->const_index[1] = 0;
 116          offset_load->src[0] = nir_src_for_ssa(
 117             nir_imul(b, nir_ssa_for_src(b, res_intrin->src[0], 1),
 118                      nir_imm_int(b, 2)));
 119       }
 120
 121       nir_ssa_dest_init(&offset_load->instr, &offset_load->dest, 2, NULL);
 122       nir_builder_instr_insert(b, &offset_load->instr);
 123
 124       /* We calculate the full offset and don't bother with the base
 125        * offset.  We need the full offset for the predicate anyway.
 126        */
 127       nir_ssa_def *rel_offset = nir_imm_int(b, intrin->const_index[0]);
 128       if (indirect_src >= 0) {
 129          assert(intrin->src[indirect_src].is_ssa);
 130          rel_offset = nir_iadd(b, intrin->src[indirect_src].ssa, rel_offset);
 131       }
 132       nir_ssa_def *global_offset = nir_iadd(b, rel_offset,
 133                                             &offset_load->dest.ssa);
 134
 135       /* Now we replace the load/store intrinsic */
 136
 137       nir_intrinsic_op indirect_op;
 138       switch (intrin->intrinsic) {
 139       case nir_intrinsic_load_ubo:
 140          indirect_op = nir_intrinsic_load_ubo_indirect;
 141          break;
 142       case nir_intrinsic_load_ssbo:
 143          indirect_op = nir_intrinsic_load_ssbo_indirect;
 144          break;
 145       case nir_intrinsic_store_ssbo:
 146          indirect_op = nir_intrinsic_store_ssbo_indirect;
 147          break;
 148       default:
 149          unreachable("Invalid direct load/store intrinsic");
 150       }
 151
 152       nir_intrinsic_instr *copy =
 153          nir_intrinsic_instr_create(state->shader, indirect_op);
 154       copy->num_components = intrin->num_components;
 155
 156       /* The indirect is always the last source */
 157       indirect_src = nir_intrinsic_infos[indirect_op].num_srcs - 1;
 158
 159       for (unsigned i = 0; i < (unsigned)indirect_src; i++)
 160          nir_src_copy(&copy->src[i], &intrin->src[i], &copy->instr);
 161
 162       copy->src[indirect_src] = nir_src_for_ssa(global_offset);
 163       nir_ssa_dest_init(&copy->instr, &copy->dest,
 164                         intrin->dest.ssa.num_components,
 165                         intrin->dest.ssa.name);
 166
 167       /* In order to avoid out-of-bounds access, we predicate */
 168       nir_ssa_def *pred = nir_fge(b, nir_channel(b, &offset_load->dest.ssa, 1),
 169                                   rel_offset);
 170       nir_if *if_stmt = nir_if_create(b->shader);
 171       if_stmt->condition = nir_src_for_ssa(pred);
 172       nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
 173
 174       nir_instr_insert_after_cf_list(&if_stmt->then_list, &copy->instr);
 175
 176       if (indirect_op != nir_intrinsic_store_ssbo) {
 177          /* It's a load, we need a phi node */
 178          nir_phi_instr *phi = nir_phi_instr_create(b->shader);
 179          nir_ssa_dest_init(&phi->instr, &phi->dest,
 180                            intrin->num_components, NULL);
 181
 182          nir_phi_src *src1 = ralloc(phi, nir_phi_src);
 183          struct exec_node *tnode = exec_list_get_tail(&if_stmt->then_list);
 184          src1->pred = exec_node_data(nir_block, tnode, cf_node.node);
 185          src1->src = nir_src_for_ssa(&copy->dest.ssa);
 186          exec_list_push_tail(&phi->srcs, &src1->node);
 187
 188          b->cursor = nir_after_cf_list(&if_stmt->else_list);
 189          nir_ssa_def *zero = nir_build_imm(b, intrin->num_components,
 190             (nir_const_value) { .u = { 0, 0, 0, 0 } });
 191
 192          nir_phi_src *src2 = ralloc(phi, nir_phi_src);
 193          struct exec_node *enode = exec_list_get_tail(&if_stmt->else_list);
 194          src2->pred = exec_node_data(nir_block, enode, cf_node.node);
 195          src2->src = nir_src_for_ssa(zero);
 196          exec_list_push_tail(&phi->srcs, &src2->node);
 197
 198          nir_instr_insert_after_cf(&if_stmt->cf_node, &phi->instr);
 199
 200          assert(intrin->dest.is_ssa);
 201          nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
 202                                   nir_src_for_ssa(&phi->dest.ssa));
 203       }
 204
 205       nir_instr_remove(&intrin->instr);
 206    }
 207
 208    return true;
 209 }
 210
 211 void
 212 anv_nir_apply_dynamic_offsets(struct anv_pipeline *pipeline,
 213                               nir_shader *shader,
 214                               struct brw_stage_prog_data *prog_data)
 215 {
 216    struct apply_dynamic_offsets_state state = {
 217       .shader = shader,
 218       .layout = pipeline->layout,
 219       .indices_start = shader->num_uniforms,
 220    };
 221
 222    if (!state.layout || !state.layout->stage[shader->stage].has_dynamic_offsets)
 223       return;
 224
 225    nir_foreach_overload(shader, overload) {
 226       if (overload->impl) {
 227          nir_builder_init(&state.builder, overload->impl);
 228          nir_foreach_block(overload->impl, apply_dynamic_offsets_block, &state);
 229          nir_metadata_preserve(overload->impl, nir_metadata_block_index |
 230                                                nir_metadata_dominance);
 231       }
 232    }
 233
 234    struct anv_push_constants *null_data = NULL;
 235    for (unsigned i = 0; i < MAX_DYNAMIC_BUFFERS; i++) {
 236       prog_data->param[i * 2 + shader->num_uniforms] =
 237          (const gl_constant_value *)&null_data->dynamic[i].offset;
 238       prog_data->param[i * 2 + 1 + shader->num_uniforms] =
 239          (const gl_constant_value *)&null_data->dynamic[i].range;
 240    }
 241
 242    shader->num_uniforms += MAX_DYNAMIC_BUFFERS * 2;
 243 }