src/vulkan/anv_nir_apply_pipeline_layout.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "anv_nir.h"
  25 #include "program/prog_parameter.h"
  26 #include "glsl/nir/nir_builder.h"
  27
  28 struct apply_pipeline_layout_state {
  29    nir_shader *shader;
  30    nir_builder builder;
  31
  32    const struct anv_pipeline_layout *layout;
  33
  34    bool progress;
  35 };
  36
  37 static uint32_t
  38 get_surface_index(unsigned set, unsigned binding,
  39                   struct apply_pipeline_layout_state *state)
  40 {
  41    assert(set < state->layout->num_sets);
  42    struct anv_descriptor_set_layout *set_layout =
  43       state->layout->set[set].layout;
  44
  45    gl_shader_stage stage = state->shader->stage;
  46
  47    assert(binding < set_layout->binding_count);
  48
  49    assert(set_layout->binding[binding].stage[stage].surface_index >= 0);
  50
  51    uint32_t surface_index =
  52       state->layout->set[set].stage[stage].surface_start +
  53       set_layout->binding[binding].stage[stage].surface_index;
  54
  55    assert(surface_index < state->layout->stage[stage].surface_count);
  56
  57    return surface_index;
  58 }
  59
  60 static uint32_t
  61 get_sampler_index(unsigned set, unsigned binding, nir_texop tex_op,
  62                   struct apply_pipeline_layout_state *state)
  63 {
  64    assert(set < state->layout->num_sets);
  65    struct anv_descriptor_set_layout *set_layout =
  66       state->layout->set[set].layout;
  67
  68    assert(binding < set_layout->binding_count);
  69
  70    gl_shader_stage stage = state->shader->stage;
  71
  72    if (set_layout->binding[binding].stage[stage].sampler_index < 0) {
  73       assert(tex_op == nir_texop_txf);
  74       return 0;
  75    }
  76
  77    uint32_t sampler_index =
  78       state->layout->set[set].stage[stage].sampler_start +
  79       set_layout->binding[binding].stage[stage].sampler_index;
  80
  81    assert(sampler_index < state->layout->stage[stage].sampler_count);
  82
  83    return sampler_index;
  84 }
  85
  86 static uint32_t
  87 get_image_index(unsigned set, unsigned binding,
  88                 struct apply_pipeline_layout_state *state)
  89 {
  90    assert(set < state->layout->num_sets);
  91    struct anv_descriptor_set_layout *set_layout =
  92       state->layout->set[set].layout;
  93
  94    assert(binding < set_layout->binding_count);
  95
  96    gl_shader_stage stage = state->shader->stage;
  97
  98    assert(set_layout->binding[binding].stage[stage].image_index >= 0);
  99
 100    uint32_t image_index =
 101       state->layout->set[set].stage[stage].image_start +
 102       set_layout->binding[binding].stage[stage].image_index;
 103
 104    assert(image_index < state->layout->stage[stage].image_count);
 105
 106    return image_index;
 107 }
 108
 109 static void
 110 lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
 111                           struct apply_pipeline_layout_state *state)
 112 {
 113    nir_builder *b = &state->builder;
 114
 115    b->cursor = nir_before_instr(&intrin->instr);
 116
 117    uint32_t set = intrin->const_index[0];
 118    uint32_t binding = intrin->const_index[1];
 119
 120    uint32_t surface_index = get_surface_index(set, binding, state);
 121
 122    nir_const_value *const_block_idx =
 123       nir_src_as_const_value(intrin->src[0]);
 124
 125    nir_ssa_def *block_index;
 126    if (const_block_idx) {
 127       block_index = nir_imm_int(b, surface_index + const_block_idx->u[0]);
 128    } else {
 129       block_index = nir_iadd(b, nir_imm_int(b, surface_index),
 130                              nir_ssa_for_src(b, intrin->src[0], 1));
 131    }
 132
 133    assert(intrin->dest.is_ssa);
 134    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
 135    nir_instr_remove(&intrin->instr);
 136 }
 137
 138 static void
 139 lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
 140                 unsigned *const_index, nir_tex_src_type src_type,
 141                 struct apply_pipeline_layout_state *state)
 142 {
 143    if (deref->deref.child) {
 144       assert(deref->deref.child->deref_type == nir_deref_type_array);
 145       nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
 146
 147       *const_index += deref_array->base_offset;
 148
 149       if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
 150          nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
 151                                                tex->num_srcs + 1);
 152
 153          for (unsigned i = 0; i < tex->num_srcs; i++) {
 154             new_srcs[i].src_type = tex->src[i].src_type;
 155             nir_instr_move_src(&tex->instr, &new_srcs[i].src, &tex->src[i].src);
 156          }
 157
 158          ralloc_free(tex->src);
 159          tex->src = new_srcs;
 160
 161          /* Now we can go ahead and move the source over to being a
 162           * first-class texture source.
 163           */
 164          tex->src[tex->num_srcs].src_type = src_type;
 165          tex->num_srcs++;
 166          assert(deref_array->indirect.is_ssa);
 167          nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs - 1].src,
 168                                deref_array->indirect);
 169       }
 170    }
 171 }
 172
 173 static void
 174 cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref)
 175 {
 176    if (deref->deref.child == NULL)
 177       return;
 178
 179    nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
 180
 181    if (deref_array->deref_array_type != nir_deref_array_type_indirect)
 182       return;
 183
 184    nir_instr_rewrite_src(&tex->instr, &deref_array->indirect, NIR_SRC_INIT);
 185 }
 186
 187 static void
 188 lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
 189 {
 190    /* No one should have come by and lowered it already */
 191    assert(tex->sampler);
 192
 193    nir_deref_var *tex_deref = tex->texture ? tex->texture : tex->sampler;
 194    tex->texture_index =
 195       get_surface_index(tex_deref->var->data.descriptor_set,
 196                         tex_deref->var->data.binding, state);
 197    lower_tex_deref(tex, tex_deref, &tex->texture_index,
 198                    nir_tex_src_texture_offset, state);
 199
 200    tex->sampler_index =
 201       get_sampler_index(tex->sampler->var->data.descriptor_set,
 202                         tex->sampler->var->data.binding, tex->op, state);
 203    lower_tex_deref(tex, tex->sampler, &tex->sampler_index,
 204                    nir_tex_src_sampler_offset, state);
 205
 206    /* The backend only ever uses this to mark used surfaces.  We don't care
 207     * about that little optimization so it just needs to be non-zero.
 208     */
 209    tex->texture_array_size = 1;
 210
 211    if (tex->texture)
 212       cleanup_tex_deref(tex, tex->texture);
 213    cleanup_tex_deref(tex, tex->sampler);
 214    tex->texture = NULL;
 215    tex->sampler = NULL;
 216 }
 217
 218 static bool
 219 apply_pipeline_layout_block(nir_block *block, void *void_state)
 220 {
 221    struct apply_pipeline_layout_state *state = void_state;
 222
 223    nir_foreach_instr_safe(block, instr) {
 224       switch (instr->type) {
 225       case nir_instr_type_intrinsic: {
 226          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 227          if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
 228             lower_res_index_intrinsic(intrin, state);
 229             state->progress = true;
 230          }
 231          break;
 232       }
 233       case nir_instr_type_tex:
 234          lower_tex(nir_instr_as_tex(instr), state);
 235          /* All texture instructions need lowering */
 236          state->progress = true;
 237          break;
 238       default:
 239          continue;
 240       }
 241    }
 242
 243    return true;
 244 }
 245
 246 static void
 247 setup_vec4_uniform_value(const union gl_constant_value **params,
 248                          const union gl_constant_value *values,
 249                          unsigned n)
 250 {
 251    static const gl_constant_value zero = { 0 };
 252
 253    for (unsigned i = 0; i < n; ++i)
 254       params[i] = &values[i];
 255
 256    for (unsigned i = n; i < 4; ++i)
 257       params[i] = &zero;
 258 }
 259
 260 bool
 261 anv_nir_apply_pipeline_layout(nir_shader *shader,
 262                               struct brw_stage_prog_data *prog_data,
 263                               const struct anv_pipeline_layout *layout)
 264 {
 265    struct apply_pipeline_layout_state state = {
 266       .shader = shader,
 267       .layout = layout,
 268    };
 269
 270    nir_foreach_function(shader, function) {
 271       if (function->impl) {
 272          nir_builder_init(&state.builder, function->impl);
 273          nir_foreach_block(function->impl, apply_pipeline_layout_block, &state);
 274          nir_metadata_preserve(function->impl, nir_metadata_block_index |
 275                                                nir_metadata_dominance);
 276       }
 277    }
 278
 279    if (layout->stage[shader->stage].image_count > 0) {
 280       nir_foreach_variable(var, &shader->uniforms) {
 281          if (glsl_type_is_image(var->type) ||
 282              (glsl_type_is_array(var->type) &&
 283               glsl_type_is_image(glsl_get_array_element(var->type)))) {
 284             /* Images are represented as uniform push constants and the actual
 285              * information required for reading/writing to/from the image is
 286              * storred in the uniform.
 287              */
 288             unsigned image_index = get_image_index(var->data.descriptor_set,
 289                                                    var->data.binding, &state);
 290
 291             var->data.driver_location = shader->num_uniforms +
 292                                         image_index * BRW_IMAGE_PARAM_SIZE * 4;
 293          }
 294       }
 295
 296       struct anv_push_constants *null_data = NULL;
 297       const gl_constant_value **param = prog_data->param + shader->num_uniforms;
 298       const struct brw_image_param *image_param = null_data->images;
 299       for (uint32_t i = 0; i < layout->stage[shader->stage].image_count; i++) {
 300          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
 301             (const union gl_constant_value *)&image_param->surface_idx, 1);
 302          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
 303             (const union gl_constant_value *)image_param->offset, 2);
 304          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
 305             (const union gl_constant_value *)image_param->size, 3);
 306          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
 307             (const union gl_constant_value *)image_param->stride, 4);
 308          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
 309             (const union gl_constant_value *)image_param->tiling, 3);
 310          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
 311             (const union gl_constant_value *)image_param->swizzling, 2);
 312
 313          param += BRW_IMAGE_PARAM_SIZE;
 314          image_param ++;
 315       }
 316
 317       shader->num_uniforms += layout->stage[shader->stage].image_count *
 318                               BRW_IMAGE_PARAM_SIZE * 4;
 319    }
 320
 321    return state.progress;
 322 }