src/vulkan/anv_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31 #include "brw_nir.h"
  32 #include "anv_nir.h"
  33 #include "glsl/nir/nir_spirv.h"
  34
  35 /* Needed for SWIZZLE macros */
  36 #include "program/prog_instruction.h"
  37
  38 // Shader functions
  39
  40 VkResult anv_CreateShaderModule(
  41     VkDevice                                    _device,
  42     const VkShaderModuleCreateInfo*             pCreateInfo,
  43     const VkAllocationCallbacks*                pAllocator,
  44     VkShaderModule*                             pShaderModule)
  45 {
  46    ANV_FROM_HANDLE(anv_device, device, _device);
  47    struct anv_shader_module *module;
  48
  49    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  50    assert(pCreateInfo->flags == 0);
  51
  52    module = anv_alloc2(&device->alloc, pAllocator,
  53                        sizeof(*module) + pCreateInfo->codeSize, 8,
  54                        VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  55    if (module == NULL)
  56       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  57
  58    module->nir = NULL;
  59    module->size = pCreateInfo->codeSize;
  60    memcpy(module->data, pCreateInfo->pCode, module->size);
  61
  62    *pShaderModule = anv_shader_module_to_handle(module);
  63
  64    return VK_SUCCESS;
  65 }
  66
  67 void anv_DestroyShaderModule(
  68     VkDevice                                    _device,
  69     VkShaderModule                              _module,
  70     const VkAllocationCallbacks*                pAllocator)
  71 {
  72    ANV_FROM_HANDLE(anv_device, device, _device);
  73    ANV_FROM_HANDLE(anv_shader_module, module, _module);
  74
  75    anv_free2(&device->alloc, pAllocator, module);
  76 }
  77
  78 #define SPIR_V_MAGIC_NUMBER 0x07230203
  79
  80 /* Eventually, this will become part of anv_CreateShader.  Unfortunately,
  81  * we can't do that yet because we don't have the ability to copy nir.
  82  */
  83 static nir_shader *
  84 anv_shader_compile_to_nir(struct anv_device *device,
  85                           struct anv_shader_module *module,
  86                           const char *entrypoint_name,
  87                           gl_shader_stage stage)
  88 {
  89    if (strcmp(entrypoint_name, "main") != 0) {
  90       anv_finishme("Multiple shaders per module not really supported");
  91    }
  92
  93    const struct brw_compiler *compiler =
  94       device->instance->physicalDevice.compiler;
  95    const nir_shader_compiler_options *nir_options =
  96       compiler->glsl_compiler_options[stage].NirOptions;
  97
  98    nir_shader *nir;
  99    if (module->nir) {
 100       /* Some things such as our meta clear/blit code will give us a NIR
 101        * shader directly.  In that case, we just ignore the SPIR-V entirely
 102        * and just use the NIR shader */
 103       nir = module->nir;
 104       nir->options = nir_options;
 105    } else {
 106       uint32_t *spirv = (uint32_t *) module->data;
 107       assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
 108       assert(module->size % 4 == 0);
 109
 110       nir = spirv_to_nir(spirv, module->size / 4, stage, nir_options);
 111    }
 112    nir_validate_shader(nir);
 113
 114    /* Vulkan uses the separate-shader linking model */
 115    nir->info.separate_shader = true;
 116
 117    /* Make sure the provided shader has exactly one entrypoint and that the
 118     * name matches the name that came in from the VkShader.
 119     */
 120    nir_function_impl *entrypoint = NULL;
 121    nir_foreach_overload(nir, overload) {
 122       if (strcmp(entrypoint_name, overload->function->name) == 0 &&
 123           overload->impl) {
 124          assert(entrypoint == NULL);
 125          entrypoint = overload->impl;
 126       }
 127    }
 128    assert(entrypoint != NULL);
 129
 130    nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
 131
 132    nir_shader_gather_info(nir, entrypoint);
 133
 134    return nir;
 135 }
 136
 137 VkResult anv_CreatePipelineCache(
 138     VkDevice                                    device,
 139     const VkPipelineCacheCreateInfo*            pCreateInfo,
 140     const VkAllocationCallbacks*                pAllocator,
 141     VkPipelineCache*                            pPipelineCache)
 142 {
 143    *pPipelineCache = (VkPipelineCache)1;
 144
 145    stub_return(VK_SUCCESS);
 146 }
 147
 148 void anv_DestroyPipelineCache(
 149     VkDevice                                    _device,
 150     VkPipelineCache                             _cache,
 151     const VkAllocationCallbacks*                pAllocator)
 152 {
 153 }
 154
 155 VkResult anv_GetPipelineCacheData(
 156     VkDevice                                    device,
 157     VkPipelineCache                             pipelineCache,
 158     size_t*                                     pDataSize,
 159     void*                                       pData)
 160 {
 161    *pDataSize = 0;
 162    stub_return(VK_SUCCESS);
 163 }
 164
 165 VkResult anv_MergePipelineCaches(
 166     VkDevice                                    device,
 167     VkPipelineCache                             destCache,
 168     uint32_t                                    srcCacheCount,
 169     const VkPipelineCache*                      pSrcCaches)
 170 {
 171    stub_return(VK_SUCCESS);
 172 }
 173
 174 void anv_DestroyPipeline(
 175     VkDevice                                    _device,
 176     VkPipeline                                  _pipeline,
 177     const VkAllocationCallbacks*                pAllocator)
 178 {
 179    ANV_FROM_HANDLE(anv_device, device, _device);
 180    ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
 181
 182    anv_reloc_list_finish(&pipeline->batch_relocs,
 183                          pAllocator ? pAllocator : &device->alloc);
 184    anv_state_stream_finish(&pipeline->program_stream);
 185    if (pipeline->blend_state.map)
 186       anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
 187    anv_free2(&device->alloc, pAllocator, pipeline);
 188 }
 189
 190 static const uint32_t vk_to_gen_primitive_type[] = {
 191    [VK_PRIMITIVE_TOPOLOGY_POINT_LIST]                    = _3DPRIM_POINTLIST,
 192    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST]                     = _3DPRIM_LINELIST,
 193    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP]                    = _3DPRIM_LINESTRIP,
 194    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST]                 = _3DPRIM_TRILIST,
 195    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP]                = _3DPRIM_TRISTRIP,
 196    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN]                  = _3DPRIM_TRIFAN,
 197    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY]      = _3DPRIM_LINELIST_ADJ,
 198    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY]     = _3DPRIM_LINESTRIP_ADJ,
 199    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY]  = _3DPRIM_TRILIST_ADJ,
 200    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
 201 /*   [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST]                = _3DPRIM_PATCHLIST_1 */
 202 };
 203
 204 static void
 205 populate_sampler_prog_key(const struct brw_device_info *devinfo,
 206                           struct brw_sampler_prog_key_data *key)
 207 {
 208    /* XXX: Handle texture swizzle on HSW- */
 209    for (int i = 0; i < MAX_SAMPLERS; i++) {
 210       /* Assume color sampler, no swizzling. (Works for BDW+) */
 211       key->swizzles[i] = SWIZZLE_XYZW;
 212    }
 213 }
 214
 215 static void
 216 populate_vs_prog_key(const struct brw_device_info *devinfo,
 217                      struct brw_vs_prog_key *key)
 218 {
 219    memset(key, 0, sizeof(*key));
 220
 221    populate_sampler_prog_key(devinfo, &key->tex);
 222
 223    /* XXX: Handle vertex input work-arounds */
 224
 225    /* XXX: Handle sampler_prog_key */
 226 }
 227
 228 static void
 229 populate_gs_prog_key(const struct brw_device_info *devinfo,
 230                      struct brw_gs_prog_key *key)
 231 {
 232    memset(key, 0, sizeof(*key));
 233
 234    populate_sampler_prog_key(devinfo, &key->tex);
 235 }
 236
 237 static void
 238 populate_wm_prog_key(const struct brw_device_info *devinfo,
 239                      const VkGraphicsPipelineCreateInfo *info,
 240                      struct brw_wm_prog_key *key)
 241 {
 242    ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
 243
 244    memset(key, 0, sizeof(*key));
 245
 246    populate_sampler_prog_key(devinfo, &key->tex);
 247
 248    /* TODO: Fill out key->input_slots_valid */
 249
 250    /* Vulkan doesn't specify a default */
 251    key->high_quality_derivatives = false;
 252
 253    /* XXX Vulkan doesn't appear to specify */
 254    key->clamp_fragment_color = false;
 255
 256    /* Vulkan always specifies upper-left coordinates */
 257    key->drawable_height = 0;
 258    key->render_to_fbo = false;
 259
 260    key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
 261
 262    key->replicate_alpha = key->nr_color_regions > 1 &&
 263                           info->pMultisampleState &&
 264                           info->pMultisampleState->alphaToCoverageEnable;
 265
 266    if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
 267       /* We should probably pull this out of the shader, but it's fairly
 268        * harmless to compute it and then let dead-code take care of it.
 269        */
 270       key->persample_shading = info->pMultisampleState->sampleShadingEnable;
 271       if (key->persample_shading)
 272          key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
 273
 274       key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
 275       key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
 276    }
 277 }
 278
 279 static void
 280 populate_cs_prog_key(const struct brw_device_info *devinfo,
 281                      struct brw_cs_prog_key *key)
 282 {
 283    memset(key, 0, sizeof(*key));
 284
 285    populate_sampler_prog_key(devinfo, &key->tex);
 286 }
 287
 288 static nir_shader *
 289 anv_pipeline_compile(struct anv_pipeline *pipeline,
 290                      struct anv_shader_module *module,
 291                      const char *entrypoint,
 292                      gl_shader_stage stage,
 293                      struct brw_stage_prog_data *prog_data)
 294 {
 295    const struct brw_compiler *compiler =
 296       pipeline->device->instance->physicalDevice.compiler;
 297
 298    nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
 299                                                module, entrypoint, stage);
 300    if (nir == NULL)
 301       return NULL;
 302
 303    anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
 304
 305    /* Figure out the number of parameters */
 306    prog_data->nr_params = 0;
 307
 308    if (nir->num_uniforms > 0) {
 309       /* If the shader uses any push constants at all, we'll just give
 310        * them the maximum possible number
 311        */
 312       prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
 313    }
 314
 315    if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
 316       prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
 317
 318    if (prog_data->nr_params > 0) {
 319       /* XXX: I think we're leaking this */
 320       prog_data->param = (const gl_constant_value **)
 321          malloc(prog_data->nr_params * sizeof(gl_constant_value *));
 322
 323       /* We now set the param values to be offsets into a
 324        * anv_push_constant_data structure.  Since the compiler doesn't
 325        * actually dereference any of the gl_constant_value pointers in the
 326        * params array, it doesn't really matter what we put here.
 327        */
 328       struct anv_push_constants *null_data = NULL;
 329       if (nir->num_uniforms > 0) {
 330          /* Fill out the push constants section of the param array */
 331          for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
 332             prog_data->param[i] = (const gl_constant_value *)
 333                &null_data->client_data[i * sizeof(float)];
 334       }
 335    }
 336
 337    /* Set up dynamic offsets */
 338    anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
 339
 340    /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
 341    anv_nir_apply_pipeline_layout(nir, pipeline->layout);
 342
 343    /* All binding table offsets provided by apply_pipeline_layout() are
 344     * relative to the start of the bindint table (plus MAX_RTS for VS).
 345     */
 346    unsigned bias = stage == MESA_SHADER_FRAGMENT ? MAX_RTS : 0;
 347    prog_data->binding_table.size_bytes = 0;
 348    prog_data->binding_table.texture_start = bias;
 349    prog_data->binding_table.ubo_start = bias;
 350    prog_data->binding_table.ssbo_start = bias;
 351    prog_data->binding_table.image_start = bias;
 352
 353    /* Finish the optimization and compilation process */
 354    nir = brw_lower_nir(nir, &pipeline->device->info, NULL,
 355                        compiler->scalar_stage[stage]);
 356
 357    /* nir_lower_io will only handle the push constants; we need to set this
 358     * to the full number of possible uniforms.
 359     */
 360    nir->num_uniforms = prog_data->nr_params;
 361
 362    return nir;
 363 }
 364
 365 static uint32_t
 366 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
 367                            const void *data, size_t size)
 368 {
 369    struct anv_state state =
 370       anv_state_stream_alloc(&pipeline->program_stream, size, 64);
 371
 372    assert(size < pipeline->program_stream.block_pool->block_size);
 373
 374    memcpy(state.map, data, size);
 375
 376    return state.offset;
 377 }
 378 static void
 379 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
 380                                 gl_shader_stage stage,
 381                                 struct brw_stage_prog_data *prog_data)
 382 {
 383    struct brw_device_info *devinfo = &pipeline->device->info;
 384    uint32_t max_threads[] = {
 385       [MESA_SHADER_VERTEX]                  = devinfo->max_vs_threads,
 386       [MESA_SHADER_TESS_CTRL]               = 0,
 387       [MESA_SHADER_TESS_EVAL]               = 0,
 388       [MESA_SHADER_GEOMETRY]                = devinfo->max_gs_threads,
 389       [MESA_SHADER_FRAGMENT]                = devinfo->max_wm_threads,
 390       [MESA_SHADER_COMPUTE]                 = devinfo->max_cs_threads,
 391    };
 392
 393    pipeline->prog_data[stage] = prog_data;
 394    pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
 395    pipeline->scratch_start[stage] = pipeline->total_scratch;
 396    pipeline->total_scratch =
 397       align_u32(pipeline->total_scratch, 1024) +
 398       prog_data->total_scratch * max_threads[stage];
 399 }
 400
 401 static VkResult
 402 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
 403                         const VkGraphicsPipelineCreateInfo *info,
 404                         struct anv_shader_module *module,
 405                         const char *entrypoint)
 406 {
 407    const struct brw_compiler *compiler =
 408       pipeline->device->instance->physicalDevice.compiler;
 409    struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
 410    struct brw_vs_prog_key key;
 411
 412    populate_vs_prog_key(&pipeline->device->info, &key);
 413
 414    /* TODO: Look up shader in cache */
 415
 416    memset(prog_data, 0, sizeof(*prog_data));
 417
 418    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 419                                           MESA_SHADER_VERTEX,
 420                                           &prog_data->base.base);
 421    if (nir == NULL)
 422       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 423
 424    void *mem_ctx = ralloc_context(NULL);
 425
 426    if (module->nir == NULL)
 427       ralloc_steal(mem_ctx, nir);
 428
 429    prog_data->inputs_read = nir->info.inputs_read;
 430    pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
 431
 432    brw_compute_vue_map(&pipeline->device->info,
 433                        &prog_data->base.vue_map,
 434                        nir->info.outputs_written,
 435                        nir->info.separate_shader);
 436
 437    unsigned code_size;
 438    const unsigned *shader_code =
 439       brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 440                      NULL, false, -1, &code_size, NULL);
 441    if (shader_code == NULL) {
 442       ralloc_free(mem_ctx);
 443       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 444    }
 445
 446    const uint32_t offset =
 447       anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
 448    if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
 449       pipeline->vs_simd8 = offset;
 450       pipeline->vs_vec4 = NO_KERNEL;
 451    } else {
 452       pipeline->vs_simd8 = NO_KERNEL;
 453       pipeline->vs_vec4 = offset;
 454    }
 455
 456    ralloc_free(mem_ctx);
 457
 458    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
 459                                    &prog_data->base.base);
 460
 461    return VK_SUCCESS;
 462 }
 463
 464 static VkResult
 465 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
 466                         const VkGraphicsPipelineCreateInfo *info,
 467                         struct anv_shader_module *module,
 468                         const char *entrypoint)
 469 {
 470    const struct brw_compiler *compiler =
 471       pipeline->device->instance->physicalDevice.compiler;
 472    struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
 473    struct brw_gs_prog_key key;
 474
 475    populate_gs_prog_key(&pipeline->device->info, &key);
 476
 477    /* TODO: Look up shader in cache */
 478
 479    memset(prog_data, 0, sizeof(*prog_data));
 480
 481    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 482                                           MESA_SHADER_GEOMETRY,
 483                                           &prog_data->base.base);
 484    if (nir == NULL)
 485       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 486
 487    void *mem_ctx = ralloc_context(NULL);
 488
 489    if (module->nir == NULL)
 490       ralloc_steal(mem_ctx, nir);
 491
 492    brw_compute_vue_map(&pipeline->device->info,
 493                        &prog_data->base.vue_map,
 494                        nir->info.outputs_written,
 495                        nir->info.separate_shader);
 496
 497    unsigned code_size;
 498    const unsigned *shader_code =
 499       brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 500                      NULL, -1, &code_size, NULL);
 501    if (shader_code == NULL) {
 502       ralloc_free(mem_ctx);
 503       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 504    }
 505
 506    /* TODO: SIMD8 GS */
 507    pipeline->gs_vec4 =
 508       anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
 509    pipeline->gs_vertex_count = nir->info.gs.vertices_in;
 510
 511    ralloc_free(mem_ctx);
 512
 513    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
 514                                    &prog_data->base.base);
 515
 516    return VK_SUCCESS;
 517 }
 518
 519 static VkResult
 520 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
 521                         const VkGraphicsPipelineCreateInfo *info,
 522                         struct anv_shader_module *module,
 523                         const char *entrypoint)
 524 {
 525    const struct brw_compiler *compiler =
 526       pipeline->device->instance->physicalDevice.compiler;
 527    struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
 528    struct brw_wm_prog_key key;
 529
 530    populate_wm_prog_key(&pipeline->device->info, info, &key);
 531
 532    if (pipeline->use_repclear)
 533       key.nr_color_regions = 1;
 534
 535    /* TODO: Look up shader in cache */
 536
 537    memset(prog_data, 0, sizeof(*prog_data));
 538
 539    prog_data->binding_table.render_target_start = 0;
 540
 541    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 542                                           MESA_SHADER_FRAGMENT,
 543                                           &prog_data->base);
 544    if (nir == NULL)
 545       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 546
 547    void *mem_ctx = ralloc_context(NULL);
 548
 549    if (module->nir == NULL)
 550       ralloc_steal(mem_ctx, nir);
 551
 552    unsigned code_size;
 553    const unsigned *shader_code =
 554       brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 555                      NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
 556    if (shader_code == NULL) {
 557       ralloc_free(mem_ctx);
 558       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 559    }
 560
 561    uint32_t offset = anv_pipeline_upload_kernel(pipeline,
 562                                                 shader_code, code_size);
 563    if (prog_data->no_8)
 564       pipeline->ps_simd8 = NO_KERNEL;
 565    else
 566       pipeline->ps_simd8 = offset;
 567
 568    if (prog_data->no_8 || prog_data->prog_offset_16) {
 569       pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
 570    } else {
 571       pipeline->ps_simd16 = NO_KERNEL;
 572    }
 573
 574    pipeline->ps_ksp2 = 0;
 575    pipeline->ps_grf_start2 = 0;
 576    if (pipeline->ps_simd8 != NO_KERNEL) {
 577       pipeline->ps_ksp0 = pipeline->ps_simd8;
 578       pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
 579       if (pipeline->ps_simd16 != NO_KERNEL) {
 580          pipeline->ps_ksp2 = pipeline->ps_simd16;
 581          pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
 582       }
 583    } else if (pipeline->ps_simd16 != NO_KERNEL) {
 584       pipeline->ps_ksp0 = pipeline->ps_simd16;
 585       pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
 586    }
 587
 588    ralloc_free(mem_ctx);
 589
 590    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
 591                                    &prog_data->base);
 592
 593    return VK_SUCCESS;
 594 }
 595
 596 VkResult
 597 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
 598                         const VkComputePipelineCreateInfo *info,
 599                         struct anv_shader_module *module,
 600                         const char *entrypoint)
 601 {
 602    const struct brw_compiler *compiler =
 603       pipeline->device->instance->physicalDevice.compiler;
 604    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 605    struct brw_cs_prog_key key;
 606
 607    populate_cs_prog_key(&pipeline->device->info, &key);
 608
 609    /* TODO: Look up shader in cache */
 610
 611    memset(prog_data, 0, sizeof(*prog_data));
 612
 613    nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
 614                                           MESA_SHADER_COMPUTE,
 615                                           &prog_data->base);
 616    if (nir == NULL)
 617       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 618
 619    void *mem_ctx = ralloc_context(NULL);
 620
 621    if (module->nir == NULL)
 622       ralloc_steal(mem_ctx, nir);
 623
 624    unsigned code_size;
 625    const unsigned *shader_code =
 626       brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
 627                      -1, &code_size, NULL);
 628    if (shader_code == NULL) {
 629       ralloc_free(mem_ctx);
 630       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 631    }
 632
 633    pipeline->cs_simd = anv_pipeline_upload_kernel(pipeline,
 634                                                   shader_code, code_size);
 635    ralloc_free(mem_ctx);
 636
 637    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
 638                                    &prog_data->base);
 639
 640    return VK_SUCCESS;
 641 }
 642
 643 static const int gen8_push_size = 32 * 1024;
 644
 645 static void
 646 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
 647 {
 648    const struct brw_device_info *devinfo = &pipeline->device->info;
 649    bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
 650    unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
 651    unsigned vs_entry_size_bytes = vs_size * 64;
 652    bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
 653    unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
 654    unsigned gs_entry_size_bytes = gs_size * 64;
 655
 656    /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
 657     *
 658     *     VS Number of URB Entries must be divisible by 8 if the VS URB Entry
 659     *     Allocation Size is less than 9 512-bit URB entries.
 660     *
 661     * Similar text exists for GS.
 662     */
 663    unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
 664    unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
 665
 666    /* URB allocations must be done in 8k chunks. */
 667    unsigned chunk_size_bytes = 8192;
 668
 669    /* Determine the size of the URB in chunks. */
 670    unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
 671
 672    /* Reserve space for push constants */
 673    unsigned push_constant_bytes = gen8_push_size;
 674    unsigned push_constant_chunks =
 675       push_constant_bytes / chunk_size_bytes;
 676
 677    /* Initially, assign each stage the minimum amount of URB space it needs,
 678     * and make a note of how much additional space it "wants" (the amount of
 679     * additional space it could actually make use of).
 680     */
 681
 682    /* VS has a lower limit on the number of URB entries */
 683    unsigned vs_chunks =
 684       ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
 685             chunk_size_bytes) / chunk_size_bytes;
 686    unsigned vs_wants =
 687       ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
 688             chunk_size_bytes) / chunk_size_bytes - vs_chunks;
 689
 690    unsigned gs_chunks = 0;
 691    unsigned gs_wants = 0;
 692    if (gs_present) {
 693       /* There are two constraints on the minimum amount of URB space we can
 694        * allocate:
 695        *
 696        * (1) We need room for at least 2 URB entries, since we always operate
 697        * the GS in DUAL_OBJECT mode.
 698        *
 699        * (2) We can't allocate less than nr_gs_entries_granularity.
 700        */
 701       gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
 702                         chunk_size_bytes) / chunk_size_bytes;
 703       gs_wants =
 704          ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
 705                chunk_size_bytes) / chunk_size_bytes - gs_chunks;
 706    }
 707
 708    /* There should always be enough URB space to satisfy the minimum
 709     * requirements of each stage.
 710     */
 711    unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
 712    assert(total_needs <= urb_chunks);
 713
 714    /* Mete out remaining space (if any) in proportion to "wants". */
 715    unsigned total_wants = vs_wants + gs_wants;
 716    unsigned remaining_space = urb_chunks - total_needs;
 717    if (remaining_space > total_wants)
 718       remaining_space = total_wants;
 719    if (remaining_space > 0) {
 720       unsigned vs_additional = (unsigned)
 721          round(vs_wants * (((double) remaining_space) / total_wants));
 722       vs_chunks += vs_additional;
 723       remaining_space -= vs_additional;
 724       gs_chunks += remaining_space;
 725    }
 726
 727    /* Sanity check that we haven't over-allocated. */
 728    assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
 729
 730    /* Finally, compute the number of entries that can fit in the space
 731     * allocated to each stage.
 732     */
 733    unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
 734    unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
 735
 736    /* Since we rounded up when computing *_wants, this may be slightly more
 737     * than the maximum allowed amount, so correct for that.
 738     */
 739    nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
 740    nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
 741
 742    /* Ensure that we program a multiple of the granularity. */
 743    nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
 744    nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
 745
 746    /* Finally, sanity check to make sure we have at least the minimum number
 747     * of entries needed for each stage.
 748     */
 749    assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
 750    if (gs_present)
 751       assert(nr_gs_entries >= 2);
 752
 753    /* Lay out the URB in the following order:
 754     * - push constants
 755     * - VS
 756     * - GS
 757     */
 758    pipeline->urb.vs_start = push_constant_chunks;
 759    pipeline->urb.vs_size = vs_size;
 760    pipeline->urb.nr_vs_entries = nr_vs_entries;
 761
 762    pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
 763    pipeline->urb.gs_size = gs_size;
 764    pipeline->urb.nr_gs_entries = nr_gs_entries;
 765 }
 766
 767 static void
 768 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
 769                                 const VkGraphicsPipelineCreateInfo *pCreateInfo)
 770 {
 771    anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
 772    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
 773    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
 774
 775    pipeline->dynamic_state = default_dynamic_state;
 776
 777    if (pCreateInfo->pDynamicState) {
 778       /* Remove all of the states that are marked as dynamic */
 779       uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
 780       for (uint32_t s = 0; s < count; s++)
 781          states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
 782    }
 783
 784    struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
 785
 786    dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
 787    if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
 788       typed_memcpy(dynamic->viewport.viewports,
 789                    pCreateInfo->pViewportState->pViewports,
 790                    pCreateInfo->pViewportState->viewportCount);
 791    }
 792
 793    dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
 794    if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
 795       typed_memcpy(dynamic->scissor.scissors,
 796                    pCreateInfo->pViewportState->pScissors,
 797                    pCreateInfo->pViewportState->scissorCount);
 798    }
 799
 800    if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
 801       assert(pCreateInfo->pRasterizationState);
 802       dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
 803    }
 804
 805    if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
 806       assert(pCreateInfo->pRasterizationState);
 807       dynamic->depth_bias.bias =
 808          pCreateInfo->pRasterizationState->depthBiasConstantFactor;
 809       dynamic->depth_bias.clamp =
 810          pCreateInfo->pRasterizationState->depthBiasClamp;
 811       dynamic->depth_bias.slope =
 812          pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
 813    }
 814
 815    if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
 816       assert(pCreateInfo->pColorBlendState);
 817       typed_memcpy(dynamic->blend_constants,
 818                    pCreateInfo->pColorBlendState->blendConstants, 4);
 819    }
 820
 821    /* If there is no depthstencil attachment, then don't read
 822     * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
 823     * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
 824     * no need to override the depthstencil defaults in
 825     * anv_pipeline::dynamic_state when there is no depthstencil attachment.
 826     *
 827     * From the Vulkan spec (20 Oct 2015, git-aa308cb):
 828     *
 829     *    pDepthStencilState [...] may only be NULL if renderPass and subpass
 830     *    specify a subpass that has no depth/stencil attachment.
 831     */
 832    if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
 833       if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
 834          assert(pCreateInfo->pDepthStencilState);
 835          dynamic->depth_bounds.min =
 836             pCreateInfo->pDepthStencilState->minDepthBounds;
 837          dynamic->depth_bounds.max =
 838             pCreateInfo->pDepthStencilState->maxDepthBounds;
 839       }
 840
 841       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
 842          assert(pCreateInfo->pDepthStencilState);
 843          dynamic->stencil_compare_mask.front =
 844             pCreateInfo->pDepthStencilState->front.compareMask;
 845          dynamic->stencil_compare_mask.back =
 846             pCreateInfo->pDepthStencilState->back.compareMask;
 847       }
 848
 849       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
 850          assert(pCreateInfo->pDepthStencilState);
 851          dynamic->stencil_write_mask.front =
 852             pCreateInfo->pDepthStencilState->front.writeMask;
 853          dynamic->stencil_write_mask.back =
 854             pCreateInfo->pDepthStencilState->back.writeMask;
 855       }
 856
 857       if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
 858          assert(pCreateInfo->pDepthStencilState);
 859          dynamic->stencil_reference.front =
 860             pCreateInfo->pDepthStencilState->front.reference;
 861          dynamic->stencil_reference.back =
 862             pCreateInfo->pDepthStencilState->back.reference;
 863       }
 864    }
 865
 866    pipeline->dynamic_state_mask = states;
 867 }
 868
 869 static void
 870 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
 871 {
 872    struct anv_render_pass *renderpass = NULL;
 873    struct anv_subpass *subpass = NULL;
 874
 875    /* Assert that all required members of VkGraphicsPipelineCreateInfo are
 876     * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
 877     * 4.2 Graphics Pipeline.
 878     */
 879    assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 880
 881    renderpass = anv_render_pass_from_handle(info->renderPass);
 882    assert(renderpass);
 883
 884    if (renderpass != &anv_meta_dummy_renderpass) {
 885       assert(info->subpass < renderpass->subpass_count);
 886       subpass = &renderpass->subpasses[info->subpass];
 887    }
 888
 889    assert(info->stageCount >= 1);
 890    assert(info->pVertexInputState);
 891    assert(info->pInputAssemblyState);
 892    assert(info->pViewportState);
 893    assert(info->pRasterizationState);
 894    assert(info->pMultisampleState);
 895
 896    if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
 897       assert(info->pDepthStencilState);
 898
 899    if (subpass && subpass->color_count > 0)
 900       assert(info->pColorBlendState);
 901
 902    for (uint32_t i = 0; i < info->stageCount; ++i) {
 903       switch (info->pStages[i].stage) {
 904       case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
 905       case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
 906          assert(info->pTessellationState);
 907          break;
 908       default:
 909          break;
 910       }
 911    }
 912 }
 913
 914 VkResult
 915 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
 916                   const VkGraphicsPipelineCreateInfo *pCreateInfo,
 917                   const struct anv_graphics_pipeline_create_info *extra,
 918                   const VkAllocationCallbacks *alloc)
 919 {
 920    anv_validate {
 921       anv_pipeline_validate_create_info(pCreateInfo);
 922    }
 923
 924    if (alloc == NULL)
 925       alloc = &device->alloc;
 926
 927    pipeline->device = device;
 928    pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
 929
 930    anv_reloc_list_init(&pipeline->batch_relocs, alloc);
 931    /* TODO: Handle allocation fail */
 932
 933    pipeline->batch.alloc = alloc;
 934    pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
 935    pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
 936    pipeline->batch.relocs = &pipeline->batch_relocs;
 937
 938    anv_state_stream_init(&pipeline->program_stream,
 939                          &device->instruction_block_pool);
 940
 941    anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
 942
 943    if (pCreateInfo->pTessellationState)
 944       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
 945    if (pCreateInfo->pMultisampleState &&
 946        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 947       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 948
 949    pipeline->use_repclear = extra && extra->use_repclear;
 950    pipeline->writes_point_size = false;
 951
 952    /* When we free the pipeline, we detect stages based on the NULL status
 953     * of various prog_data pointers.  Make them NULL by default.
 954     */
 955    memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
 956    memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
 957
 958    pipeline->vs_simd8 = NO_KERNEL;
 959    pipeline->vs_vec4 = NO_KERNEL;
 960    pipeline->gs_vec4 = NO_KERNEL;
 961
 962    pipeline->active_stages = 0;
 963    pipeline->total_scratch = 0;
 964
 965    for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
 966       ANV_FROM_HANDLE(anv_shader_module, module,
 967                       pCreateInfo->pStages[i].module);
 968       const char *entrypoint = pCreateInfo->pStages[i].pName;
 969
 970       switch (pCreateInfo->pStages[i].stage) {
 971       case VK_SHADER_STAGE_VERTEX_BIT:
 972          anv_pipeline_compile_vs(pipeline, pCreateInfo, module, entrypoint);
 973          break;
 974       case VK_SHADER_STAGE_GEOMETRY_BIT:
 975          anv_pipeline_compile_gs(pipeline, pCreateInfo, module, entrypoint);
 976          break;
 977       case VK_SHADER_STAGE_FRAGMENT_BIT:
 978          anv_pipeline_compile_fs(pipeline, pCreateInfo, module, entrypoint);
 979          break;
 980       default:
 981          anv_finishme("Unsupported shader stage");
 982       }
 983    }
 984
 985    if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
 986       /* Vertex is only optional if disable_vs is set */
 987       assert(extra->disable_vs);
 988       memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
 989    }
 990
 991    gen7_compute_urb_partition(pipeline);
 992
 993    const VkPipelineVertexInputStateCreateInfo *vi_info =
 994       pCreateInfo->pVertexInputState;
 995    pipeline->vb_used = 0;
 996    for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
 997       const VkVertexInputBindingDescription *desc =
 998          &vi_info->pVertexBindingDescriptions[i];
 999
1000       pipeline->vb_used |= 1 << desc->binding;
1001       pipeline->binding_stride[desc->binding] = desc->stride;
1002
1003       /* Step rate is programmed per vertex element (attribute), not
1004        * binding. Set up a map of which bindings step per instance, for
1005        * reference by vertex element setup. */
1006       switch (desc->inputRate) {
1007       default:
1008       case VK_VERTEX_INPUT_RATE_VERTEX:
1009          pipeline->instancing_enable[desc->binding] = false;
1010          break;
1011       case VK_VERTEX_INPUT_RATE_INSTANCE:
1012          pipeline->instancing_enable[desc->binding] = true;
1013          break;
1014       }
1015    }
1016
1017    const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1018       pCreateInfo->pInputAssemblyState;
1019    pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1020    pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1021
1022    if (extra && extra->use_rectlist)
1023       pipeline->topology = _3DPRIM_RECTLIST;
1024
1025    return VK_SUCCESS;
1026 }
1027
1028 VkResult
1029 anv_graphics_pipeline_create(
1030    VkDevice _device,
1031    const VkGraphicsPipelineCreateInfo *pCreateInfo,
1032    const struct anv_graphics_pipeline_create_info *extra,
1033    const VkAllocationCallbacks *pAllocator,
1034    VkPipeline *pPipeline)
1035 {
1036    ANV_FROM_HANDLE(anv_device, device, _device);
1037
1038    switch (device->info.gen) {
1039    case 7:
1040       if (device->info.is_haswell)
1041          return gen75_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1042       else
1043          return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1044    case 8:
1045       return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1046    case 9:
1047       return gen9_graphics_pipeline_create(_device, pCreateInfo, extra, pAllocator, pPipeline);
1048    default:
1049       unreachable("unsupported gen\n");
1050    }
1051 }
1052
1053 VkResult anv_CreateGraphicsPipelines(
1054     VkDevice                                    _device,
1055     VkPipelineCache                             pipelineCache,
1056     uint32_t                                    count,
1057     const VkGraphicsPipelineCreateInfo*         pCreateInfos,
1058     const VkAllocationCallbacks*                pAllocator,
1059     VkPipeline*                                 pPipelines)
1060 {
1061    VkResult result = VK_SUCCESS;
1062
1063    unsigned i = 0;
1064    for (; i < count; i++) {
1065       result = anv_graphics_pipeline_create(_device, &pCreateInfos[i],
1066                                             NULL, pAllocator, &pPipelines[i]);
1067       if (result != VK_SUCCESS) {
1068          for (unsigned j = 0; j < i; j++) {
1069             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1070          }
1071
1072          return result;
1073       }
1074    }
1075
1076    return VK_SUCCESS;
1077 }
1078
1079 static VkResult anv_compute_pipeline_create(
1080     VkDevice                                    _device,
1081     const VkComputePipelineCreateInfo*          pCreateInfo,
1082     const VkAllocationCallbacks*                pAllocator,
1083     VkPipeline*                                 pPipeline)
1084 {
1085    ANV_FROM_HANDLE(anv_device, device, _device);
1086
1087    switch (device->info.gen) {
1088    case 7:
1089       if (device->info.is_haswell)
1090          return gen75_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1091       else
1092          return gen7_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1093    case 8:
1094       return gen8_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1095    case 9:
1096       return gen9_compute_pipeline_create(_device, pCreateInfo, pAllocator, pPipeline);
1097    default:
1098       unreachable("unsupported gen\n");
1099    }
1100 }
1101
1102 VkResult anv_CreateComputePipelines(
1103     VkDevice                                    _device,
1104     VkPipelineCache                             pipelineCache,
1105     uint32_t                                    count,
1106     const VkComputePipelineCreateInfo*          pCreateInfos,
1107     const VkAllocationCallbacks*                pAllocator,
1108     VkPipeline*                                 pPipelines)
1109 {
1110    VkResult result = VK_SUCCESS;
1111
1112    unsigned i = 0;
1113    for (; i < count; i++) {
1114       result = anv_compute_pipeline_create(_device, &pCreateInfos[i],
1115                                            pAllocator, &pPipelines[i]);
1116       if (result != VK_SUCCESS) {
1117          for (unsigned j = 0; j < i; j++) {
1118             anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1119          }
1120
1121          return result;
1122       }
1123    }
1124
1125    return VK_SUCCESS;
1126 }