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vulkan-1.0.0: Re-order some structs in the header
[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "brw_nir.h"
32 #include "anv_nir.h"
33 #include "glsl/nir/spirv/nir_spirv.h"
34
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
37
38 // Shader functions
39
40 VkResult anv_CreateShaderModule(
41 VkDevice _device,
42 const VkShaderModuleCreateInfo* pCreateInfo,
43 const VkAllocationCallbacks* pAllocator,
44 VkShaderModule* pShaderModule)
45 {
46 ANV_FROM_HANDLE(anv_device, device, _device);
47 struct anv_shader_module *module;
48
49 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
50 assert(pCreateInfo->flags == 0);
51
52 module = anv_alloc2(&device->alloc, pAllocator,
53 sizeof(*module) + pCreateInfo->codeSize, 8,
54 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
55 if (module == NULL)
56 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
57
58 module->nir = NULL;
59 module->size = pCreateInfo->codeSize;
60 memcpy(module->data, pCreateInfo->pCode, module->size);
61
62 *pShaderModule = anv_shader_module_to_handle(module);
63
64 return VK_SUCCESS;
65 }
66
67 void anv_DestroyShaderModule(
68 VkDevice _device,
69 VkShaderModule _module,
70 const VkAllocationCallbacks* pAllocator)
71 {
72 ANV_FROM_HANDLE(anv_device, device, _device);
73 ANV_FROM_HANDLE(anv_shader_module, module, _module);
74
75 anv_free2(&device->alloc, pAllocator, module);
76 }
77
78 #define SPIR_V_MAGIC_NUMBER 0x07230203
79
80 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
81 * we can't do that yet because we don't have the ability to copy nir.
82 */
83 static nir_shader *
84 anv_shader_compile_to_nir(struct anv_device *device,
85 struct anv_shader_module *module,
86 const char *entrypoint_name,
87 gl_shader_stage stage,
88 const VkSpecializationInfo *spec_info)
89 {
90 if (strcmp(entrypoint_name, "main") != 0) {
91 anv_finishme("Multiple shaders per module not really supported");
92 }
93
94 const struct brw_compiler *compiler =
95 device->instance->physicalDevice.compiler;
96 const nir_shader_compiler_options *nir_options =
97 compiler->glsl_compiler_options[stage].NirOptions;
98
99 nir_shader *nir;
100 nir_function *entry_point;
101 if (module->nir) {
102 /* Some things such as our meta clear/blit code will give us a NIR
103 * shader directly. In that case, we just ignore the SPIR-V entirely
104 * and just use the NIR shader */
105 nir = module->nir;
106 nir->options = nir_options;
107 nir_validate_shader(nir);
108
109 assert(exec_list_length(&nir->functions) == 1);
110 struct exec_node *node = exec_list_get_head(&nir->functions);
111 entry_point = exec_node_data(nir_function, node, node);
112 } else {
113 uint32_t *spirv = (uint32_t *) module->data;
114 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
115 assert(module->size % 4 == 0);
116
117 uint32_t num_spec_entries = 0;
118 struct nir_spirv_specialization *spec_entries = NULL;
119 if (spec_info && spec_info->mapEntryCount > 0) {
120 num_spec_entries = spec_info->mapEntryCount;
121 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
122 for (uint32_t i = 0; i < num_spec_entries; i++) {
123 const uint32_t *data =
124 spec_info->pData + spec_info->pMapEntries[i].offset;
125 assert((const void *)(data + 1) <=
126 spec_info->pData + spec_info->dataSize);
127
128 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
129 spec_entries[i].data = *data;
130 }
131 }
132
133 entry_point = spirv_to_nir(spirv, module->size / 4,
134 spec_entries, num_spec_entries,
135 stage, entrypoint_name, nir_options);
136 nir = entry_point->shader;
137 assert(nir->stage == stage);
138 nir_validate_shader(nir);
139
140 free(spec_entries);
141
142 nir_lower_returns(nir);
143 nir_validate_shader(nir);
144
145 nir_inline_functions(nir);
146 nir_validate_shader(nir);
147
148 /* Pick off the single entrypoint that we want */
149 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
150 if (func != entry_point)
151 exec_node_remove(&func->node);
152 }
153 assert(exec_list_length(&nir->functions) == 1);
154 entry_point->name = ralloc_strdup(entry_point, "main");
155
156 nir_remove_dead_variables(nir, nir_var_shader_in);
157 nir_remove_dead_variables(nir, nir_var_shader_out);
158 nir_remove_dead_variables(nir, nir_var_system_value);
159 nir_validate_shader(nir);
160
161 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
162
163 nir_lower_system_values(nir);
164 nir_validate_shader(nir);
165 }
166
167 /* Vulkan uses the separate-shader linking model */
168 nir->info.separate_shader = true;
169
170 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
171
172 nir_shader_gather_info(nir, entry_point->impl);
173
174 uint32_t indirect_mask = (1 << nir_var_shader_in);
175 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
176 indirect_mask |= 1 << nir_var_local;
177
178 nir_lower_indirect_derefs(nir, indirect_mask);
179
180 return nir;
181 }
182
183 void
184 anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
185 struct anv_device *device)
186 {
187 cache->device = device;
188 anv_state_stream_init(&cache->program_stream,
189 &device->instruction_block_pool);
190 pthread_mutex_init(&cache->mutex, NULL);
191 }
192
193 void
194 anv_pipeline_cache_finish(struct anv_pipeline_cache *cache)
195 {
196 anv_state_stream_finish(&cache->program_stream);
197 pthread_mutex_destroy(&cache->mutex);
198 }
199
200 static uint32_t
201 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
202 const void *data, size_t size)
203 {
204 pthread_mutex_lock(&cache->mutex);
205
206 struct anv_state state =
207 anv_state_stream_alloc(&cache->program_stream, size, 64);
208
209 pthread_mutex_unlock(&cache->mutex);
210
211 assert(size < cache->program_stream.block_pool->block_size);
212
213 memcpy(state.map, data, size);
214
215 if (!cache->device->info.has_llc)
216 anv_state_clflush(state);
217
218 return state.offset;
219 }
220
221 VkResult anv_CreatePipelineCache(
222 VkDevice _device,
223 const VkPipelineCacheCreateInfo* pCreateInfo,
224 const VkAllocationCallbacks* pAllocator,
225 VkPipelineCache* pPipelineCache)
226 {
227 ANV_FROM_HANDLE(anv_device, device, _device);
228 struct anv_pipeline_cache *cache;
229
230 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
231 assert(pCreateInfo->flags == 0);
232
233 cache = anv_alloc2(&device->alloc, pAllocator,
234 sizeof(*cache), 8,
235 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
236 if (cache == NULL)
237 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
238
239 anv_pipeline_cache_init(cache, device);
240
241 *pPipelineCache = anv_pipeline_cache_to_handle(cache);
242
243 return VK_SUCCESS;
244 }
245
246 void anv_DestroyPipelineCache(
247 VkDevice _device,
248 VkPipelineCache _cache,
249 const VkAllocationCallbacks* pAllocator)
250 {
251 ANV_FROM_HANDLE(anv_device, device, _device);
252 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
253
254 anv_pipeline_cache_finish(cache);
255
256 anv_free2(&device->alloc, pAllocator, cache);
257 }
258
259 VkResult anv_GetPipelineCacheData(
260 VkDevice device,
261 VkPipelineCache pipelineCache,
262 size_t* pDataSize,
263 void* pData)
264 {
265 *pDataSize = 0;
266
267 return VK_SUCCESS;
268 }
269
270 VkResult anv_MergePipelineCaches(
271 VkDevice device,
272 VkPipelineCache destCache,
273 uint32_t srcCacheCount,
274 const VkPipelineCache* pSrcCaches)
275 {
276 stub_return(VK_SUCCESS);
277 }
278
279 void anv_DestroyPipeline(
280 VkDevice _device,
281 VkPipeline _pipeline,
282 const VkAllocationCallbacks* pAllocator)
283 {
284 ANV_FROM_HANDLE(anv_device, device, _device);
285 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
286
287 anv_reloc_list_finish(&pipeline->batch_relocs,
288 pAllocator ? pAllocator : &device->alloc);
289 if (pipeline->blend_state.map)
290 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
291 anv_free2(&device->alloc, pAllocator, pipeline);
292 }
293
294 static const uint32_t vk_to_gen_primitive_type[] = {
295 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
296 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
297 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
298 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
299 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
300 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
301 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
302 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
303 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
304 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
305 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
306 };
307
308 static void
309 populate_sampler_prog_key(const struct brw_device_info *devinfo,
310 struct brw_sampler_prog_key_data *key)
311 {
312 /* XXX: Handle texture swizzle on HSW- */
313 for (int i = 0; i < MAX_SAMPLERS; i++) {
314 /* Assume color sampler, no swizzling. (Works for BDW+) */
315 key->swizzles[i] = SWIZZLE_XYZW;
316 }
317 }
318
319 static void
320 populate_vs_prog_key(const struct brw_device_info *devinfo,
321 struct brw_vs_prog_key *key)
322 {
323 memset(key, 0, sizeof(*key));
324
325 populate_sampler_prog_key(devinfo, &key->tex);
326
327 /* XXX: Handle vertex input work-arounds */
328
329 /* XXX: Handle sampler_prog_key */
330 }
331
332 static void
333 populate_gs_prog_key(const struct brw_device_info *devinfo,
334 struct brw_gs_prog_key *key)
335 {
336 memset(key, 0, sizeof(*key));
337
338 populate_sampler_prog_key(devinfo, &key->tex);
339 }
340
341 static void
342 populate_wm_prog_key(const struct brw_device_info *devinfo,
343 const VkGraphicsPipelineCreateInfo *info,
344 struct brw_wm_prog_key *key)
345 {
346 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
347
348 memset(key, 0, sizeof(*key));
349
350 populate_sampler_prog_key(devinfo, &key->tex);
351
352 /* TODO: Fill out key->input_slots_valid */
353
354 /* Vulkan doesn't specify a default */
355 key->high_quality_derivatives = false;
356
357 /* XXX Vulkan doesn't appear to specify */
358 key->clamp_fragment_color = false;
359
360 /* Vulkan always specifies upper-left coordinates */
361 key->drawable_height = 0;
362 key->render_to_fbo = false;
363
364 key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
365
366 key->replicate_alpha = key->nr_color_regions > 1 &&
367 info->pMultisampleState &&
368 info->pMultisampleState->alphaToCoverageEnable;
369
370 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
371 /* We should probably pull this out of the shader, but it's fairly
372 * harmless to compute it and then let dead-code take care of it.
373 */
374 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
375 if (key->persample_shading)
376 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
377
378 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
379 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
380 }
381 }
382
383 static void
384 populate_cs_prog_key(const struct brw_device_info *devinfo,
385 struct brw_cs_prog_key *key)
386 {
387 memset(key, 0, sizeof(*key));
388
389 populate_sampler_prog_key(devinfo, &key->tex);
390 }
391
392 static nir_shader *
393 anv_pipeline_compile(struct anv_pipeline *pipeline,
394 struct anv_shader_module *module,
395 const char *entrypoint,
396 gl_shader_stage stage,
397 const VkSpecializationInfo *spec_info,
398 struct brw_stage_prog_data *prog_data)
399 {
400 const struct brw_compiler *compiler =
401 pipeline->device->instance->physicalDevice.compiler;
402
403 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
404 module, entrypoint, stage,
405 spec_info);
406 if (nir == NULL)
407 return NULL;
408
409 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
410
411 /* Figure out the number of parameters */
412 prog_data->nr_params = 0;
413
414 if (nir->num_uniforms > 0) {
415 /* If the shader uses any push constants at all, we'll just give
416 * them the maximum possible number
417 */
418 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
419 }
420
421 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
422 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
423
424 if (pipeline->layout && pipeline->layout->stage[stage].image_count > 0)
425 prog_data->nr_params += pipeline->layout->stage[stage].image_count *
426 BRW_IMAGE_PARAM_SIZE;
427
428 if (prog_data->nr_params > 0) {
429 /* XXX: I think we're leaking this */
430 prog_data->param = (const union gl_constant_value **)
431 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
432
433 /* We now set the param values to be offsets into a
434 * anv_push_constant_data structure. Since the compiler doesn't
435 * actually dereference any of the gl_constant_value pointers in the
436 * params array, it doesn't really matter what we put here.
437 */
438 struct anv_push_constants *null_data = NULL;
439 if (nir->num_uniforms > 0) {
440 /* Fill out the push constants section of the param array */
441 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
442 prog_data->param[i] = (const union gl_constant_value *)
443 &null_data->client_data[i * sizeof(float)];
444 }
445 }
446
447 /* Set up dynamic offsets */
448 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
449
450 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
451 if (pipeline->layout)
452 anv_nir_apply_pipeline_layout(nir, prog_data, pipeline->layout);
453
454 /* All binding table offsets provided by apply_pipeline_layout() are
455 * relative to the start of the bindint table (plus MAX_RTS for VS).
456 */
457 unsigned bias;
458 switch (stage) {
459 case MESA_SHADER_FRAGMENT:
460 bias = MAX_RTS;
461 break;
462 case MESA_SHADER_COMPUTE:
463 bias = 1;
464 break;
465 default:
466 bias = 0;
467 break;
468 }
469 prog_data->binding_table.size_bytes = 0;
470 prog_data->binding_table.texture_start = bias;
471 prog_data->binding_table.ubo_start = bias;
472 prog_data->binding_table.ssbo_start = bias;
473 prog_data->binding_table.image_start = bias;
474
475 /* Finish the optimization and compilation process */
476 nir = brw_nir_lower_io(nir, &pipeline->device->info,
477 compiler->scalar_stage[stage]);
478
479 /* nir_lower_io will only handle the push constants; we need to set this
480 * to the full number of possible uniforms.
481 */
482 nir->num_uniforms = prog_data->nr_params * 4;
483
484 return nir;
485 }
486
487 static void
488 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
489 gl_shader_stage stage,
490 struct brw_stage_prog_data *prog_data)
491 {
492 struct brw_device_info *devinfo = &pipeline->device->info;
493 uint32_t max_threads[] = {
494 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
495 [MESA_SHADER_TESS_CTRL] = 0,
496 [MESA_SHADER_TESS_EVAL] = 0,
497 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
498 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
499 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
500 };
501
502 pipeline->prog_data[stage] = prog_data;
503 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
504 pipeline->scratch_start[stage] = pipeline->total_scratch;
505 pipeline->total_scratch =
506 align_u32(pipeline->total_scratch, 1024) +
507 prog_data->total_scratch * max_threads[stage];
508 }
509
510 static VkResult
511 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
512 struct anv_pipeline_cache *cache,
513 const VkGraphicsPipelineCreateInfo *info,
514 struct anv_shader_module *module,
515 const char *entrypoint,
516 const VkSpecializationInfo *spec_info)
517 {
518 const struct brw_compiler *compiler =
519 pipeline->device->instance->physicalDevice.compiler;
520 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
521 struct brw_vs_prog_key key;
522
523 populate_vs_prog_key(&pipeline->device->info, &key);
524
525 /* TODO: Look up shader in cache */
526
527 memset(prog_data, 0, sizeof(*prog_data));
528
529 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
530 MESA_SHADER_VERTEX, spec_info,
531 &prog_data->base.base);
532 if (nir == NULL)
533 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
534
535 void *mem_ctx = ralloc_context(NULL);
536
537 if (module->nir == NULL)
538 ralloc_steal(mem_ctx, nir);
539
540 prog_data->inputs_read = nir->info.inputs_read;
541 pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
542
543 brw_compute_vue_map(&pipeline->device->info,
544 &prog_data->base.vue_map,
545 nir->info.outputs_written,
546 nir->info.separate_shader);
547
548 unsigned code_size;
549 const unsigned *shader_code =
550 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
551 NULL, false, -1, &code_size, NULL);
552 if (shader_code == NULL) {
553 ralloc_free(mem_ctx);
554 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
555 }
556
557 const uint32_t offset =
558 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
559 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
560 pipeline->vs_simd8 = offset;
561 pipeline->vs_vec4 = NO_KERNEL;
562 } else {
563 pipeline->vs_simd8 = NO_KERNEL;
564 pipeline->vs_vec4 = offset;
565 }
566
567 ralloc_free(mem_ctx);
568
569 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
570 &prog_data->base.base);
571
572 return VK_SUCCESS;
573 }
574
575 static VkResult
576 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
577 struct anv_pipeline_cache *cache,
578 const VkGraphicsPipelineCreateInfo *info,
579 struct anv_shader_module *module,
580 const char *entrypoint,
581 const VkSpecializationInfo *spec_info)
582 {
583 const struct brw_compiler *compiler =
584 pipeline->device->instance->physicalDevice.compiler;
585 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
586 struct brw_gs_prog_key key;
587
588 populate_gs_prog_key(&pipeline->device->info, &key);
589
590 /* TODO: Look up shader in cache */
591
592 memset(prog_data, 0, sizeof(*prog_data));
593
594 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
595 MESA_SHADER_GEOMETRY, spec_info,
596 &prog_data->base.base);
597 if (nir == NULL)
598 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
599
600 void *mem_ctx = ralloc_context(NULL);
601
602 if (module->nir == NULL)
603 ralloc_steal(mem_ctx, nir);
604
605 brw_compute_vue_map(&pipeline->device->info,
606 &prog_data->base.vue_map,
607 nir->info.outputs_written,
608 nir->info.separate_shader);
609
610 unsigned code_size;
611 const unsigned *shader_code =
612 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
613 NULL, -1, &code_size, NULL);
614 if (shader_code == NULL) {
615 ralloc_free(mem_ctx);
616 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
617 }
618
619 /* TODO: SIMD8 GS */
620 pipeline->gs_kernel =
621 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
622 pipeline->gs_vertex_count = nir->info.gs.vertices_in;
623
624 ralloc_free(mem_ctx);
625
626 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
627 &prog_data->base.base);
628
629 return VK_SUCCESS;
630 }
631
632 static VkResult
633 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
634 struct anv_pipeline_cache *cache,
635 const VkGraphicsPipelineCreateInfo *info,
636 struct anv_shader_module *module,
637 const char *entrypoint,
638 const VkSpecializationInfo *spec_info)
639 {
640 const struct brw_compiler *compiler =
641 pipeline->device->instance->physicalDevice.compiler;
642 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
643 struct brw_wm_prog_key key;
644
645 populate_wm_prog_key(&pipeline->device->info, info, &key);
646
647 if (pipeline->use_repclear)
648 key.nr_color_regions = 1;
649
650 /* TODO: Look up shader in cache */
651
652 memset(prog_data, 0, sizeof(*prog_data));
653
654 prog_data->binding_table.render_target_start = 0;
655
656 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
657 MESA_SHADER_FRAGMENT, spec_info,
658 &prog_data->base);
659 if (nir == NULL)
660 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
661
662 void *mem_ctx = ralloc_context(NULL);
663
664 if (module->nir == NULL)
665 ralloc_steal(mem_ctx, nir);
666
667 unsigned code_size;
668 const unsigned *shader_code =
669 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
670 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
671 if (shader_code == NULL) {
672 ralloc_free(mem_ctx);
673 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
674 }
675
676 uint32_t offset =
677 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
678 if (prog_data->no_8)
679 pipeline->ps_simd8 = NO_KERNEL;
680 else
681 pipeline->ps_simd8 = offset;
682
683 if (prog_data->no_8 || prog_data->prog_offset_16) {
684 pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
685 } else {
686 pipeline->ps_simd16 = NO_KERNEL;
687 }
688
689 pipeline->ps_ksp2 = 0;
690 pipeline->ps_grf_start2 = 0;
691 if (pipeline->ps_simd8 != NO_KERNEL) {
692 pipeline->ps_ksp0 = pipeline->ps_simd8;
693 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
694 if (pipeline->ps_simd16 != NO_KERNEL) {
695 pipeline->ps_ksp2 = pipeline->ps_simd16;
696 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
697 }
698 } else if (pipeline->ps_simd16 != NO_KERNEL) {
699 pipeline->ps_ksp0 = pipeline->ps_simd16;
700 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
701 }
702
703 ralloc_free(mem_ctx);
704
705 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
706 &prog_data->base);
707
708 return VK_SUCCESS;
709 }
710
711 VkResult
712 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
713 struct anv_pipeline_cache *cache,
714 const VkComputePipelineCreateInfo *info,
715 struct anv_shader_module *module,
716 const char *entrypoint,
717 const VkSpecializationInfo *spec_info)
718 {
719 const struct brw_compiler *compiler =
720 pipeline->device->instance->physicalDevice.compiler;
721 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
722 struct brw_cs_prog_key key;
723
724 populate_cs_prog_key(&pipeline->device->info, &key);
725
726 /* TODO: Look up shader in cache */
727
728 memset(prog_data, 0, sizeof(*prog_data));
729
730 prog_data->binding_table.work_groups_start = 0;
731
732 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
733 MESA_SHADER_COMPUTE, spec_info,
734 &prog_data->base);
735 if (nir == NULL)
736 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
737
738 void *mem_ctx = ralloc_context(NULL);
739
740 if (module->nir == NULL)
741 ralloc_steal(mem_ctx, nir);
742
743 unsigned code_size;
744 const unsigned *shader_code =
745 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
746 -1, &code_size, NULL);
747 if (shader_code == NULL) {
748 ralloc_free(mem_ctx);
749 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
750 }
751
752 pipeline->cs_simd =
753 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
754 ralloc_free(mem_ctx);
755
756 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
757 &prog_data->base);
758
759 return VK_SUCCESS;
760 }
761
762 static const int gen8_push_size = 32 * 1024;
763
764 static void
765 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
766 {
767 const struct brw_device_info *devinfo = &pipeline->device->info;
768 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
769 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
770 unsigned vs_entry_size_bytes = vs_size * 64;
771 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
772 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
773 unsigned gs_entry_size_bytes = gs_size * 64;
774
775 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
776 *
777 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
778 * Allocation Size is less than 9 512-bit URB entries.
779 *
780 * Similar text exists for GS.
781 */
782 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
783 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
784
785 /* URB allocations must be done in 8k chunks. */
786 unsigned chunk_size_bytes = 8192;
787
788 /* Determine the size of the URB in chunks. */
789 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
790
791 /* Reserve space for push constants */
792 unsigned push_constant_bytes = gen8_push_size;
793 unsigned push_constant_chunks =
794 push_constant_bytes / chunk_size_bytes;
795
796 /* Initially, assign each stage the minimum amount of URB space it needs,
797 * and make a note of how much additional space it "wants" (the amount of
798 * additional space it could actually make use of).
799 */
800
801 /* VS has a lower limit on the number of URB entries */
802 unsigned vs_chunks =
803 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
804 chunk_size_bytes) / chunk_size_bytes;
805 unsigned vs_wants =
806 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
807 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
808
809 unsigned gs_chunks = 0;
810 unsigned gs_wants = 0;
811 if (gs_present) {
812 /* There are two constraints on the minimum amount of URB space we can
813 * allocate:
814 *
815 * (1) We need room for at least 2 URB entries, since we always operate
816 * the GS in DUAL_OBJECT mode.
817 *
818 * (2) We can't allocate less than nr_gs_entries_granularity.
819 */
820 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
821 chunk_size_bytes) / chunk_size_bytes;
822 gs_wants =
823 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
824 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
825 }
826
827 /* There should always be enough URB space to satisfy the minimum
828 * requirements of each stage.
829 */
830 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
831 assert(total_needs <= urb_chunks);
832
833 /* Mete out remaining space (if any) in proportion to "wants". */
834 unsigned total_wants = vs_wants + gs_wants;
835 unsigned remaining_space = urb_chunks - total_needs;
836 if (remaining_space > total_wants)
837 remaining_space = total_wants;
838 if (remaining_space > 0) {
839 unsigned vs_additional = (unsigned)
840 round(vs_wants * (((double) remaining_space) / total_wants));
841 vs_chunks += vs_additional;
842 remaining_space -= vs_additional;
843 gs_chunks += remaining_space;
844 }
845
846 /* Sanity check that we haven't over-allocated. */
847 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
848
849 /* Finally, compute the number of entries that can fit in the space
850 * allocated to each stage.
851 */
852 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
853 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
854
855 /* Since we rounded up when computing *_wants, this may be slightly more
856 * than the maximum allowed amount, so correct for that.
857 */
858 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
859 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
860
861 /* Ensure that we program a multiple of the granularity. */
862 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
863 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
864
865 /* Finally, sanity check to make sure we have at least the minimum number
866 * of entries needed for each stage.
867 */
868 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
869 if (gs_present)
870 assert(nr_gs_entries >= 2);
871
872 /* Lay out the URB in the following order:
873 * - push constants
874 * - VS
875 * - GS
876 */
877 pipeline->urb.vs_start = push_constant_chunks;
878 pipeline->urb.vs_size = vs_size;
879 pipeline->urb.nr_vs_entries = nr_vs_entries;
880
881 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
882 pipeline->urb.gs_size = gs_size;
883 pipeline->urb.nr_gs_entries = nr_gs_entries;
884 }
885
886 static void
887 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
888 const VkGraphicsPipelineCreateInfo *pCreateInfo)
889 {
890 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
891 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
892 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
893
894 pipeline->dynamic_state = default_dynamic_state;
895
896 if (pCreateInfo->pDynamicState) {
897 /* Remove all of the states that are marked as dynamic */
898 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
899 for (uint32_t s = 0; s < count; s++)
900 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
901 }
902
903 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
904
905 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
906 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
907 typed_memcpy(dynamic->viewport.viewports,
908 pCreateInfo->pViewportState->pViewports,
909 pCreateInfo->pViewportState->viewportCount);
910 }
911
912 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
913 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
914 typed_memcpy(dynamic->scissor.scissors,
915 pCreateInfo->pViewportState->pScissors,
916 pCreateInfo->pViewportState->scissorCount);
917 }
918
919 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
920 assert(pCreateInfo->pRasterizationState);
921 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
922 }
923
924 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
925 assert(pCreateInfo->pRasterizationState);
926 dynamic->depth_bias.bias =
927 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
928 dynamic->depth_bias.clamp =
929 pCreateInfo->pRasterizationState->depthBiasClamp;
930 dynamic->depth_bias.slope =
931 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
932 }
933
934 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
935 assert(pCreateInfo->pColorBlendState);
936 typed_memcpy(dynamic->blend_constants,
937 pCreateInfo->pColorBlendState->blendConstants, 4);
938 }
939
940 /* If there is no depthstencil attachment, then don't read
941 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
942 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
943 * no need to override the depthstencil defaults in
944 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
945 *
946 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
947 *
948 * pDepthStencilState [...] may only be NULL if renderPass and subpass
949 * specify a subpass that has no depth/stencil attachment.
950 */
951 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
952 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
953 assert(pCreateInfo->pDepthStencilState);
954 dynamic->depth_bounds.min =
955 pCreateInfo->pDepthStencilState->minDepthBounds;
956 dynamic->depth_bounds.max =
957 pCreateInfo->pDepthStencilState->maxDepthBounds;
958 }
959
960 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
961 assert(pCreateInfo->pDepthStencilState);
962 dynamic->stencil_compare_mask.front =
963 pCreateInfo->pDepthStencilState->front.compareMask;
964 dynamic->stencil_compare_mask.back =
965 pCreateInfo->pDepthStencilState->back.compareMask;
966 }
967
968 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
969 assert(pCreateInfo->pDepthStencilState);
970 dynamic->stencil_write_mask.front =
971 pCreateInfo->pDepthStencilState->front.writeMask;
972 dynamic->stencil_write_mask.back =
973 pCreateInfo->pDepthStencilState->back.writeMask;
974 }
975
976 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
977 assert(pCreateInfo->pDepthStencilState);
978 dynamic->stencil_reference.front =
979 pCreateInfo->pDepthStencilState->front.reference;
980 dynamic->stencil_reference.back =
981 pCreateInfo->pDepthStencilState->back.reference;
982 }
983 }
984
985 pipeline->dynamic_state_mask = states;
986 }
987
988 static void
989 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
990 {
991 struct anv_render_pass *renderpass = NULL;
992 struct anv_subpass *subpass = NULL;
993
994 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
995 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
996 * 4.2 Graphics Pipeline.
997 */
998 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
999
1000 renderpass = anv_render_pass_from_handle(info->renderPass);
1001 assert(renderpass);
1002
1003 if (renderpass != &anv_meta_dummy_renderpass) {
1004 assert(info->subpass < renderpass->subpass_count);
1005 subpass = &renderpass->subpasses[info->subpass];
1006 }
1007
1008 assert(info->stageCount >= 1);
1009 assert(info->pVertexInputState);
1010 assert(info->pInputAssemblyState);
1011 assert(info->pViewportState);
1012 assert(info->pRasterizationState);
1013
1014 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1015 assert(info->pDepthStencilState);
1016
1017 if (subpass && subpass->color_count > 0)
1018 assert(info->pColorBlendState);
1019
1020 for (uint32_t i = 0; i < info->stageCount; ++i) {
1021 switch (info->pStages[i].stage) {
1022 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1023 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1024 assert(info->pTessellationState);
1025 break;
1026 default:
1027 break;
1028 }
1029 }
1030 }
1031
1032 VkResult
1033 anv_pipeline_init(struct anv_pipeline *pipeline,
1034 struct anv_device *device,
1035 struct anv_pipeline_cache *cache,
1036 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1037 const struct anv_graphics_pipeline_create_info *extra,
1038 const VkAllocationCallbacks *alloc)
1039 {
1040 VkResult result;
1041
1042 anv_validate {
1043 anv_pipeline_validate_create_info(pCreateInfo);
1044 }
1045
1046 if (alloc == NULL)
1047 alloc = &device->alloc;
1048
1049 pipeline->device = device;
1050 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1051
1052 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1053 if (result != VK_SUCCESS)
1054 return result;
1055
1056 pipeline->batch.alloc = alloc;
1057 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1058 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1059 pipeline->batch.relocs = &pipeline->batch_relocs;
1060
1061 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1062
1063 if (pCreateInfo->pTessellationState)
1064 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1065 if (pCreateInfo->pMultisampleState &&
1066 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1067 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
1068
1069 pipeline->use_repclear = extra && extra->use_repclear;
1070 pipeline->writes_point_size = false;
1071
1072 /* When we free the pipeline, we detect stages based on the NULL status
1073 * of various prog_data pointers. Make them NULL by default.
1074 */
1075 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1076 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1077
1078 pipeline->vs_simd8 = NO_KERNEL;
1079 pipeline->vs_vec4 = NO_KERNEL;
1080 pipeline->gs_kernel = NO_KERNEL;
1081
1082 pipeline->active_stages = 0;
1083 pipeline->total_scratch = 0;
1084
1085 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1086 ANV_FROM_HANDLE(anv_shader_module, module,
1087 pCreateInfo->pStages[i].module);
1088
1089 switch (pCreateInfo->pStages[i].stage) {
1090 case VK_SHADER_STAGE_VERTEX_BIT:
1091 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module,
1092 pCreateInfo->pStages[i].pName,
1093 pCreateInfo->pStages[i].pSpecializationInfo);
1094 break;
1095 case VK_SHADER_STAGE_GEOMETRY_BIT:
1096 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module,
1097 pCreateInfo->pStages[i].pName,
1098 pCreateInfo->pStages[i].pSpecializationInfo);
1099 break;
1100 case VK_SHADER_STAGE_FRAGMENT_BIT:
1101 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, module,
1102 pCreateInfo->pStages[i].pName,
1103 pCreateInfo->pStages[i].pSpecializationInfo);
1104 break;
1105 default:
1106 anv_finishme("Unsupported shader stage");
1107 }
1108 }
1109
1110 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1111 /* Vertex is only optional if disable_vs is set */
1112 assert(extra->disable_vs);
1113 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1114 }
1115
1116 gen7_compute_urb_partition(pipeline);
1117
1118 const VkPipelineVertexInputStateCreateInfo *vi_info =
1119 pCreateInfo->pVertexInputState;
1120
1121 uint64_t inputs_read;
1122 if (extra && extra->disable_vs) {
1123 /* If the VS is disabled, just assume the user knows what they're
1124 * doing and apply the layout blindly. This can only come from
1125 * meta, so this *should* be safe.
1126 */
1127 inputs_read = ~0ull;
1128 } else {
1129 inputs_read = pipeline->vs_prog_data.inputs_read;
1130 }
1131
1132 pipeline->vb_used = 0;
1133 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1134 const VkVertexInputAttributeDescription *desc =
1135 &vi_info->pVertexAttributeDescriptions[i];
1136
1137 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1138 pipeline->vb_used |= 1 << desc->binding;
1139 }
1140
1141 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1142 const VkVertexInputBindingDescription *desc =
1143 &vi_info->pVertexBindingDescriptions[i];
1144
1145 pipeline->binding_stride[desc->binding] = desc->stride;
1146
1147 /* Step rate is programmed per vertex element (attribute), not
1148 * binding. Set up a map of which bindings step per instance, for
1149 * reference by vertex element setup. */
1150 switch (desc->inputRate) {
1151 default:
1152 case VK_VERTEX_INPUT_RATE_VERTEX:
1153 pipeline->instancing_enable[desc->binding] = false;
1154 break;
1155 case VK_VERTEX_INPUT_RATE_INSTANCE:
1156 pipeline->instancing_enable[desc->binding] = true;
1157 break;
1158 }
1159 }
1160
1161 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1162 pCreateInfo->pInputAssemblyState;
1163 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1164 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1165
1166 if (extra && extra->use_rectlist)
1167 pipeline->topology = _3DPRIM_RECTLIST;
1168
1169 return VK_SUCCESS;
1170 }
1171
1172 VkResult
1173 anv_graphics_pipeline_create(
1174 VkDevice _device,
1175 VkPipelineCache _cache,
1176 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1177 const struct anv_graphics_pipeline_create_info *extra,
1178 const VkAllocationCallbacks *pAllocator,
1179 VkPipeline *pPipeline)
1180 {
1181 ANV_FROM_HANDLE(anv_device, device, _device);
1182 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1183
1184 if (cache == NULL)
1185 cache = &device->default_pipeline_cache;
1186
1187 switch (device->info.gen) {
1188 case 7:
1189 if (device->info.is_haswell)
1190 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1191 else
1192 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1193 case 8:
1194 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1195 case 9:
1196 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1197 default:
1198 unreachable("unsupported gen\n");
1199 }
1200 }
1201
1202 VkResult anv_CreateGraphicsPipelines(
1203 VkDevice _device,
1204 VkPipelineCache pipelineCache,
1205 uint32_t count,
1206 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1207 const VkAllocationCallbacks* pAllocator,
1208 VkPipeline* pPipelines)
1209 {
1210 VkResult result = VK_SUCCESS;
1211
1212 unsigned i = 0;
1213 for (; i < count; i++) {
1214 result = anv_graphics_pipeline_create(_device,
1215 pipelineCache,
1216 &pCreateInfos[i],
1217 NULL, pAllocator, &pPipelines[i]);
1218 if (result != VK_SUCCESS) {
1219 for (unsigned j = 0; j < i; j++) {
1220 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1221 }
1222
1223 return result;
1224 }
1225 }
1226
1227 return VK_SUCCESS;
1228 }
1229
1230 static VkResult anv_compute_pipeline_create(
1231 VkDevice _device,
1232 VkPipelineCache _cache,
1233 const VkComputePipelineCreateInfo* pCreateInfo,
1234 const VkAllocationCallbacks* pAllocator,
1235 VkPipeline* pPipeline)
1236 {
1237 ANV_FROM_HANDLE(anv_device, device, _device);
1238 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1239
1240 if (cache == NULL)
1241 cache = &device->default_pipeline_cache;
1242
1243 switch (device->info.gen) {
1244 case 7:
1245 if (device->info.is_haswell)
1246 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1247 else
1248 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1249 case 8:
1250 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1251 case 9:
1252 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1253 default:
1254 unreachable("unsupported gen\n");
1255 }
1256 }
1257
1258 VkResult anv_CreateComputePipelines(
1259 VkDevice _device,
1260 VkPipelineCache pipelineCache,
1261 uint32_t count,
1262 const VkComputePipelineCreateInfo* pCreateInfos,
1263 const VkAllocationCallbacks* pAllocator,
1264 VkPipeline* pPipelines)
1265 {
1266 VkResult result = VK_SUCCESS;
1267
1268 unsigned i = 0;
1269 for (; i < count; i++) {
1270 result = anv_compute_pipeline_create(_device, pipelineCache,
1271 &pCreateInfos[i],
1272 pAllocator, &pPipelines[i]);
1273 if (result != VK_SUCCESS) {
1274 for (unsigned j = 0; j < i; j++) {
1275 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1276 }
1277
1278 return result;
1279 }
1280 }
1281
1282 return VK_SUCCESS;
1283 }