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[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "brw_nir.h"
32 #include "anv_nir.h"
33 #include "glsl/nir/spirv/nir_spirv.h"
34
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
37
38 // Shader functions
39
40 VkResult anv_CreateShaderModule(
41 VkDevice _device,
42 const VkShaderModuleCreateInfo* pCreateInfo,
43 const VkAllocationCallbacks* pAllocator,
44 VkShaderModule* pShaderModule)
45 {
46 ANV_FROM_HANDLE(anv_device, device, _device);
47 struct anv_shader_module *module;
48
49 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
50 assert(pCreateInfo->flags == 0);
51
52 module = anv_alloc2(&device->alloc, pAllocator,
53 sizeof(*module) + pCreateInfo->codeSize, 8,
54 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
55 if (module == NULL)
56 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
57
58 module->nir = NULL;
59 module->size = pCreateInfo->codeSize;
60 memcpy(module->data, pCreateInfo->pCode, module->size);
61
62 *pShaderModule = anv_shader_module_to_handle(module);
63
64 return VK_SUCCESS;
65 }
66
67 void anv_DestroyShaderModule(
68 VkDevice _device,
69 VkShaderModule _module,
70 const VkAllocationCallbacks* pAllocator)
71 {
72 ANV_FROM_HANDLE(anv_device, device, _device);
73 ANV_FROM_HANDLE(anv_shader_module, module, _module);
74
75 anv_free2(&device->alloc, pAllocator, module);
76 }
77
78 #define SPIR_V_MAGIC_NUMBER 0x07230203
79
80 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
81 * we can't do that yet because we don't have the ability to copy nir.
82 */
83 static nir_shader *
84 anv_shader_compile_to_nir(struct anv_device *device,
85 struct anv_shader_module *module,
86 const char *entrypoint_name,
87 gl_shader_stage stage)
88 {
89 if (strcmp(entrypoint_name, "main") != 0) {
90 anv_finishme("Multiple shaders per module not really supported");
91 }
92
93 const struct brw_compiler *compiler =
94 device->instance->physicalDevice.compiler;
95 const nir_shader_compiler_options *nir_options =
96 compiler->glsl_compiler_options[stage].NirOptions;
97
98 nir_shader *nir;
99 nir_function *entry_point;
100 if (module->nir) {
101 /* Some things such as our meta clear/blit code will give us a NIR
102 * shader directly. In that case, we just ignore the SPIR-V entirely
103 * and just use the NIR shader */
104 nir = module->nir;
105 nir->options = nir_options;
106 nir_validate_shader(nir);
107
108 assert(exec_list_length(&nir->functions) == 1);
109 struct exec_node *node = exec_list_get_head(&nir->functions);
110 entry_point = exec_node_data(nir_function, node, node);
111 } else {
112 uint32_t *spirv = (uint32_t *) module->data;
113 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
114 assert(module->size % 4 == 0);
115
116 entry_point = spirv_to_nir(spirv, module->size / 4, entrypoint_name,
117 nir_options);
118 nir = entry_point->shader;
119 assert(nir->stage == stage);
120 nir_validate_shader(nir);
121
122 nir_lower_returns(nir);
123 nir_validate_shader(nir);
124
125 nir_inline_functions(nir);
126 nir_validate_shader(nir);
127
128 nir_lower_system_values(nir);
129 nir_validate_shader(nir);
130 }
131
132 /* Vulkan uses the separate-shader linking model */
133 nir->info.separate_shader = true;
134
135 /* Pick off the single entrypoint that we want */
136 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
137 if (func != entry_point)
138 exec_node_remove(&func->node);
139 }
140 assert(exec_list_length(&nir->functions) == 1);
141
142 nir = brw_preprocess_nir(nir, compiler->scalar_stage[stage]);
143
144 nir_shader_gather_info(nir, entry_point->impl);
145
146 return nir;
147 }
148
149 void
150 anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
151 struct anv_device *device)
152 {
153 cache->device = device;
154 anv_state_stream_init(&cache->program_stream,
155 &device->instruction_block_pool);
156 pthread_mutex_init(&cache->mutex, NULL);
157 }
158
159 void
160 anv_pipeline_cache_finish(struct anv_pipeline_cache *cache)
161 {
162 anv_state_stream_finish(&cache->program_stream);
163 pthread_mutex_destroy(&cache->mutex);
164 }
165
166 static uint32_t
167 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
168 const void *data, size_t size)
169 {
170 pthread_mutex_lock(&cache->mutex);
171
172 struct anv_state state =
173 anv_state_stream_alloc(&cache->program_stream, size, 64);
174
175 pthread_mutex_unlock(&cache->mutex);
176
177 assert(size < cache->program_stream.block_pool->block_size);
178
179 memcpy(state.map, data, size);
180
181 if (!cache->device->info.has_llc)
182 anv_state_clflush(state);
183
184 return state.offset;
185 }
186
187 VkResult anv_CreatePipelineCache(
188 VkDevice _device,
189 const VkPipelineCacheCreateInfo* pCreateInfo,
190 const VkAllocationCallbacks* pAllocator,
191 VkPipelineCache* pPipelineCache)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 struct anv_pipeline_cache *cache;
195
196 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
197 assert(pCreateInfo->flags == 0);
198
199 cache = anv_alloc2(&device->alloc, pAllocator,
200 sizeof(*cache), 8,
201 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
202 if (cache == NULL)
203 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
204
205 anv_pipeline_cache_init(cache, device);
206
207 *pPipelineCache = anv_pipeline_cache_to_handle(cache);
208
209 return VK_SUCCESS;
210 }
211
212 void anv_DestroyPipelineCache(
213 VkDevice _device,
214 VkPipelineCache _cache,
215 const VkAllocationCallbacks* pAllocator)
216 {
217 ANV_FROM_HANDLE(anv_device, device, _device);
218 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
219
220 anv_pipeline_cache_finish(cache);
221
222 anv_free2(&device->alloc, pAllocator, cache);
223 }
224
225 VkResult anv_GetPipelineCacheData(
226 VkDevice device,
227 VkPipelineCache pipelineCache,
228 size_t* pDataSize,
229 void* pData)
230 {
231 *pDataSize = 0;
232
233 return VK_SUCCESS;
234 }
235
236 VkResult anv_MergePipelineCaches(
237 VkDevice device,
238 VkPipelineCache destCache,
239 uint32_t srcCacheCount,
240 const VkPipelineCache* pSrcCaches)
241 {
242 stub_return(VK_SUCCESS);
243 }
244
245 void anv_DestroyPipeline(
246 VkDevice _device,
247 VkPipeline _pipeline,
248 const VkAllocationCallbacks* pAllocator)
249 {
250 ANV_FROM_HANDLE(anv_device, device, _device);
251 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
252
253 anv_reloc_list_finish(&pipeline->batch_relocs,
254 pAllocator ? pAllocator : &device->alloc);
255 if (pipeline->blend_state.map)
256 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
257 anv_free2(&device->alloc, pAllocator, pipeline);
258 }
259
260 static const uint32_t vk_to_gen_primitive_type[] = {
261 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
262 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
263 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
264 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
265 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
266 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
267 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
268 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
269 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
270 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
271 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
272 };
273
274 static void
275 populate_sampler_prog_key(const struct brw_device_info *devinfo,
276 struct brw_sampler_prog_key_data *key)
277 {
278 /* XXX: Handle texture swizzle on HSW- */
279 for (int i = 0; i < MAX_SAMPLERS; i++) {
280 /* Assume color sampler, no swizzling. (Works for BDW+) */
281 key->swizzles[i] = SWIZZLE_XYZW;
282 }
283 }
284
285 static void
286 populate_vs_prog_key(const struct brw_device_info *devinfo,
287 struct brw_vs_prog_key *key)
288 {
289 memset(key, 0, sizeof(*key));
290
291 populate_sampler_prog_key(devinfo, &key->tex);
292
293 /* XXX: Handle vertex input work-arounds */
294
295 /* XXX: Handle sampler_prog_key */
296 }
297
298 static void
299 populate_gs_prog_key(const struct brw_device_info *devinfo,
300 struct brw_gs_prog_key *key)
301 {
302 memset(key, 0, sizeof(*key));
303
304 populate_sampler_prog_key(devinfo, &key->tex);
305 }
306
307 static void
308 populate_wm_prog_key(const struct brw_device_info *devinfo,
309 const VkGraphicsPipelineCreateInfo *info,
310 struct brw_wm_prog_key *key)
311 {
312 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
313
314 memset(key, 0, sizeof(*key));
315
316 populate_sampler_prog_key(devinfo, &key->tex);
317
318 /* TODO: Fill out key->input_slots_valid */
319
320 /* Vulkan doesn't specify a default */
321 key->high_quality_derivatives = false;
322
323 /* XXX Vulkan doesn't appear to specify */
324 key->clamp_fragment_color = false;
325
326 /* Vulkan always specifies upper-left coordinates */
327 key->drawable_height = 0;
328 key->render_to_fbo = false;
329
330 key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
331
332 key->replicate_alpha = key->nr_color_regions > 1 &&
333 info->pMultisampleState &&
334 info->pMultisampleState->alphaToCoverageEnable;
335
336 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
337 /* We should probably pull this out of the shader, but it's fairly
338 * harmless to compute it and then let dead-code take care of it.
339 */
340 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
341 if (key->persample_shading)
342 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
343
344 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
345 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
346 }
347 }
348
349 static void
350 populate_cs_prog_key(const struct brw_device_info *devinfo,
351 struct brw_cs_prog_key *key)
352 {
353 memset(key, 0, sizeof(*key));
354
355 populate_sampler_prog_key(devinfo, &key->tex);
356 }
357
358 static nir_shader *
359 anv_pipeline_compile(struct anv_pipeline *pipeline,
360 struct anv_shader_module *module,
361 const char *entrypoint,
362 gl_shader_stage stage,
363 struct brw_stage_prog_data *prog_data)
364 {
365 const struct brw_compiler *compiler =
366 pipeline->device->instance->physicalDevice.compiler;
367
368 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
369 module, entrypoint, stage);
370 if (nir == NULL)
371 return NULL;
372
373 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
374
375 /* Figure out the number of parameters */
376 prog_data->nr_params = 0;
377
378 if (nir->num_uniforms > 0) {
379 /* If the shader uses any push constants at all, we'll just give
380 * them the maximum possible number
381 */
382 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
383 }
384
385 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
386 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
387
388 if (pipeline->layout && pipeline->layout->stage[stage].image_count > 0)
389 prog_data->nr_params += pipeline->layout->stage[stage].image_count *
390 BRW_IMAGE_PARAM_SIZE;
391
392 if (prog_data->nr_params > 0) {
393 /* XXX: I think we're leaking this */
394 prog_data->param = (const union gl_constant_value **)
395 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
396
397 /* We now set the param values to be offsets into a
398 * anv_push_constant_data structure. Since the compiler doesn't
399 * actually dereference any of the gl_constant_value pointers in the
400 * params array, it doesn't really matter what we put here.
401 */
402 struct anv_push_constants *null_data = NULL;
403 if (nir->num_uniforms > 0) {
404 /* Fill out the push constants section of the param array */
405 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
406 prog_data->param[i] = (const union gl_constant_value *)
407 &null_data->client_data[i * sizeof(float)];
408 }
409 }
410
411 /* Set up dynamic offsets */
412 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
413
414 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
415 if (pipeline->layout)
416 anv_nir_apply_pipeline_layout(nir, prog_data, pipeline->layout);
417
418 /* All binding table offsets provided by apply_pipeline_layout() are
419 * relative to the start of the bindint table (plus MAX_RTS for VS).
420 */
421 unsigned bias;
422 switch (stage) {
423 case MESA_SHADER_FRAGMENT:
424 bias = MAX_RTS;
425 break;
426 case MESA_SHADER_COMPUTE:
427 bias = 1;
428 break;
429 default:
430 bias = 0;
431 break;
432 }
433 prog_data->binding_table.size_bytes = 0;
434 prog_data->binding_table.texture_start = bias;
435 prog_data->binding_table.ubo_start = bias;
436 prog_data->binding_table.ssbo_start = bias;
437 prog_data->binding_table.image_start = bias;
438
439 /* Finish the optimization and compilation process */
440 nir = brw_nir_lower_io(nir, &pipeline->device->info,
441 compiler->scalar_stage[stage]);
442
443 /* nir_lower_io will only handle the push constants; we need to set this
444 * to the full number of possible uniforms.
445 */
446 nir->num_uniforms = prog_data->nr_params * 4;
447
448 return nir;
449 }
450
451 static void
452 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
453 gl_shader_stage stage,
454 struct brw_stage_prog_data *prog_data)
455 {
456 struct brw_device_info *devinfo = &pipeline->device->info;
457 uint32_t max_threads[] = {
458 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
459 [MESA_SHADER_TESS_CTRL] = 0,
460 [MESA_SHADER_TESS_EVAL] = 0,
461 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
462 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
463 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
464 };
465
466 pipeline->prog_data[stage] = prog_data;
467 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
468 pipeline->scratch_start[stage] = pipeline->total_scratch;
469 pipeline->total_scratch =
470 align_u32(pipeline->total_scratch, 1024) +
471 prog_data->total_scratch * max_threads[stage];
472 }
473
474 static VkResult
475 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
476 struct anv_pipeline_cache *cache,
477 const VkGraphicsPipelineCreateInfo *info,
478 struct anv_shader_module *module,
479 const char *entrypoint)
480 {
481 const struct brw_compiler *compiler =
482 pipeline->device->instance->physicalDevice.compiler;
483 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
484 struct brw_vs_prog_key key;
485
486 populate_vs_prog_key(&pipeline->device->info, &key);
487
488 /* TODO: Look up shader in cache */
489
490 memset(prog_data, 0, sizeof(*prog_data));
491
492 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
493 MESA_SHADER_VERTEX,
494 &prog_data->base.base);
495 if (nir == NULL)
496 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
497
498 void *mem_ctx = ralloc_context(NULL);
499
500 if (module->nir == NULL)
501 ralloc_steal(mem_ctx, nir);
502
503 prog_data->inputs_read = nir->info.inputs_read;
504 pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
505
506 brw_compute_vue_map(&pipeline->device->info,
507 &prog_data->base.vue_map,
508 nir->info.outputs_written,
509 nir->info.separate_shader);
510
511 unsigned code_size;
512 const unsigned *shader_code =
513 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
514 NULL, false, -1, &code_size, NULL);
515 if (shader_code == NULL) {
516 ralloc_free(mem_ctx);
517 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
518 }
519
520 const uint32_t offset =
521 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
522 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
523 pipeline->vs_simd8 = offset;
524 pipeline->vs_vec4 = NO_KERNEL;
525 } else {
526 pipeline->vs_simd8 = NO_KERNEL;
527 pipeline->vs_vec4 = offset;
528 }
529
530 ralloc_free(mem_ctx);
531
532 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
533 &prog_data->base.base);
534
535 return VK_SUCCESS;
536 }
537
538 static VkResult
539 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
540 struct anv_pipeline_cache *cache,
541 const VkGraphicsPipelineCreateInfo *info,
542 struct anv_shader_module *module,
543 const char *entrypoint)
544 {
545 const struct brw_compiler *compiler =
546 pipeline->device->instance->physicalDevice.compiler;
547 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
548 struct brw_gs_prog_key key;
549
550 populate_gs_prog_key(&pipeline->device->info, &key);
551
552 /* TODO: Look up shader in cache */
553
554 memset(prog_data, 0, sizeof(*prog_data));
555
556 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
557 MESA_SHADER_GEOMETRY,
558 &prog_data->base.base);
559 if (nir == NULL)
560 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
561
562 void *mem_ctx = ralloc_context(NULL);
563
564 if (module->nir == NULL)
565 ralloc_steal(mem_ctx, nir);
566
567 brw_compute_vue_map(&pipeline->device->info,
568 &prog_data->base.vue_map,
569 nir->info.outputs_written,
570 nir->info.separate_shader);
571
572 unsigned code_size;
573 const unsigned *shader_code =
574 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
575 NULL, -1, &code_size, NULL);
576 if (shader_code == NULL) {
577 ralloc_free(mem_ctx);
578 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
579 }
580
581 /* TODO: SIMD8 GS */
582 pipeline->gs_kernel =
583 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
584 pipeline->gs_vertex_count = nir->info.gs.vertices_in;
585
586 ralloc_free(mem_ctx);
587
588 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
589 &prog_data->base.base);
590
591 return VK_SUCCESS;
592 }
593
594 static VkResult
595 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
596 struct anv_pipeline_cache *cache,
597 const VkGraphicsPipelineCreateInfo *info,
598 struct anv_shader_module *module,
599 const char *entrypoint)
600 {
601 const struct brw_compiler *compiler =
602 pipeline->device->instance->physicalDevice.compiler;
603 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
604 struct brw_wm_prog_key key;
605
606 populate_wm_prog_key(&pipeline->device->info, info, &key);
607
608 if (pipeline->use_repclear)
609 key.nr_color_regions = 1;
610
611 /* TODO: Look up shader in cache */
612
613 memset(prog_data, 0, sizeof(*prog_data));
614
615 prog_data->binding_table.render_target_start = 0;
616
617 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
618 MESA_SHADER_FRAGMENT,
619 &prog_data->base);
620 if (nir == NULL)
621 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
622
623 void *mem_ctx = ralloc_context(NULL);
624
625 if (module->nir == NULL)
626 ralloc_steal(mem_ctx, nir);
627
628 unsigned code_size;
629 const unsigned *shader_code =
630 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
631 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
632 if (shader_code == NULL) {
633 ralloc_free(mem_ctx);
634 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
635 }
636
637 uint32_t offset =
638 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
639 if (prog_data->no_8)
640 pipeline->ps_simd8 = NO_KERNEL;
641 else
642 pipeline->ps_simd8 = offset;
643
644 if (prog_data->no_8 || prog_data->prog_offset_16) {
645 pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
646 } else {
647 pipeline->ps_simd16 = NO_KERNEL;
648 }
649
650 pipeline->ps_ksp2 = 0;
651 pipeline->ps_grf_start2 = 0;
652 if (pipeline->ps_simd8 != NO_KERNEL) {
653 pipeline->ps_ksp0 = pipeline->ps_simd8;
654 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
655 if (pipeline->ps_simd16 != NO_KERNEL) {
656 pipeline->ps_ksp2 = pipeline->ps_simd16;
657 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
658 }
659 } else if (pipeline->ps_simd16 != NO_KERNEL) {
660 pipeline->ps_ksp0 = pipeline->ps_simd16;
661 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
662 }
663
664 ralloc_free(mem_ctx);
665
666 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
667 &prog_data->base);
668
669 return VK_SUCCESS;
670 }
671
672 VkResult
673 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
674 struct anv_pipeline_cache *cache,
675 const VkComputePipelineCreateInfo *info,
676 struct anv_shader_module *module,
677 const char *entrypoint)
678 {
679 const struct brw_compiler *compiler =
680 pipeline->device->instance->physicalDevice.compiler;
681 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
682 struct brw_cs_prog_key key;
683
684 populate_cs_prog_key(&pipeline->device->info, &key);
685
686 /* TODO: Look up shader in cache */
687
688 memset(prog_data, 0, sizeof(*prog_data));
689
690 prog_data->binding_table.work_groups_start = 0;
691
692 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
693 MESA_SHADER_COMPUTE,
694 &prog_data->base);
695 if (nir == NULL)
696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
697
698 void *mem_ctx = ralloc_context(NULL);
699
700 if (module->nir == NULL)
701 ralloc_steal(mem_ctx, nir);
702
703 unsigned code_size;
704 const unsigned *shader_code =
705 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
706 -1, &code_size, NULL);
707 if (shader_code == NULL) {
708 ralloc_free(mem_ctx);
709 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
710 }
711
712 pipeline->cs_simd =
713 anv_pipeline_cache_upload_kernel(cache, shader_code, code_size);
714 ralloc_free(mem_ctx);
715
716 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
717 &prog_data->base);
718
719 return VK_SUCCESS;
720 }
721
722 static const int gen8_push_size = 32 * 1024;
723
724 static void
725 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
726 {
727 const struct brw_device_info *devinfo = &pipeline->device->info;
728 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
729 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
730 unsigned vs_entry_size_bytes = vs_size * 64;
731 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
732 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
733 unsigned gs_entry_size_bytes = gs_size * 64;
734
735 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
736 *
737 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
738 * Allocation Size is less than 9 512-bit URB entries.
739 *
740 * Similar text exists for GS.
741 */
742 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
743 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
744
745 /* URB allocations must be done in 8k chunks. */
746 unsigned chunk_size_bytes = 8192;
747
748 /* Determine the size of the URB in chunks. */
749 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
750
751 /* Reserve space for push constants */
752 unsigned push_constant_bytes = gen8_push_size;
753 unsigned push_constant_chunks =
754 push_constant_bytes / chunk_size_bytes;
755
756 /* Initially, assign each stage the minimum amount of URB space it needs,
757 * and make a note of how much additional space it "wants" (the amount of
758 * additional space it could actually make use of).
759 */
760
761 /* VS has a lower limit on the number of URB entries */
762 unsigned vs_chunks =
763 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
764 chunk_size_bytes) / chunk_size_bytes;
765 unsigned vs_wants =
766 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
767 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
768
769 unsigned gs_chunks = 0;
770 unsigned gs_wants = 0;
771 if (gs_present) {
772 /* There are two constraints on the minimum amount of URB space we can
773 * allocate:
774 *
775 * (1) We need room for at least 2 URB entries, since we always operate
776 * the GS in DUAL_OBJECT mode.
777 *
778 * (2) We can't allocate less than nr_gs_entries_granularity.
779 */
780 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
781 chunk_size_bytes) / chunk_size_bytes;
782 gs_wants =
783 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
784 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
785 }
786
787 /* There should always be enough URB space to satisfy the minimum
788 * requirements of each stage.
789 */
790 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
791 assert(total_needs <= urb_chunks);
792
793 /* Mete out remaining space (if any) in proportion to "wants". */
794 unsigned total_wants = vs_wants + gs_wants;
795 unsigned remaining_space = urb_chunks - total_needs;
796 if (remaining_space > total_wants)
797 remaining_space = total_wants;
798 if (remaining_space > 0) {
799 unsigned vs_additional = (unsigned)
800 round(vs_wants * (((double) remaining_space) / total_wants));
801 vs_chunks += vs_additional;
802 remaining_space -= vs_additional;
803 gs_chunks += remaining_space;
804 }
805
806 /* Sanity check that we haven't over-allocated. */
807 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
808
809 /* Finally, compute the number of entries that can fit in the space
810 * allocated to each stage.
811 */
812 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
813 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
814
815 /* Since we rounded up when computing *_wants, this may be slightly more
816 * than the maximum allowed amount, so correct for that.
817 */
818 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
819 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
820
821 /* Ensure that we program a multiple of the granularity. */
822 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
823 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
824
825 /* Finally, sanity check to make sure we have at least the minimum number
826 * of entries needed for each stage.
827 */
828 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
829 if (gs_present)
830 assert(nr_gs_entries >= 2);
831
832 /* Lay out the URB in the following order:
833 * - push constants
834 * - VS
835 * - GS
836 */
837 pipeline->urb.vs_start = push_constant_chunks;
838 pipeline->urb.vs_size = vs_size;
839 pipeline->urb.nr_vs_entries = nr_vs_entries;
840
841 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
842 pipeline->urb.gs_size = gs_size;
843 pipeline->urb.nr_gs_entries = nr_gs_entries;
844 }
845
846 static void
847 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
848 const VkGraphicsPipelineCreateInfo *pCreateInfo)
849 {
850 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
851 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
852 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
853
854 pipeline->dynamic_state = default_dynamic_state;
855
856 if (pCreateInfo->pDynamicState) {
857 /* Remove all of the states that are marked as dynamic */
858 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
859 for (uint32_t s = 0; s < count; s++)
860 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
861 }
862
863 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
864
865 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
866 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
867 typed_memcpy(dynamic->viewport.viewports,
868 pCreateInfo->pViewportState->pViewports,
869 pCreateInfo->pViewportState->viewportCount);
870 }
871
872 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
873 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
874 typed_memcpy(dynamic->scissor.scissors,
875 pCreateInfo->pViewportState->pScissors,
876 pCreateInfo->pViewportState->scissorCount);
877 }
878
879 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
880 assert(pCreateInfo->pRasterizationState);
881 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
882 }
883
884 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
885 assert(pCreateInfo->pRasterizationState);
886 dynamic->depth_bias.bias =
887 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
888 dynamic->depth_bias.clamp =
889 pCreateInfo->pRasterizationState->depthBiasClamp;
890 dynamic->depth_bias.slope =
891 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
892 }
893
894 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
895 assert(pCreateInfo->pColorBlendState);
896 typed_memcpy(dynamic->blend_constants,
897 pCreateInfo->pColorBlendState->blendConstants, 4);
898 }
899
900 /* If there is no depthstencil attachment, then don't read
901 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
902 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
903 * no need to override the depthstencil defaults in
904 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
905 *
906 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
907 *
908 * pDepthStencilState [...] may only be NULL if renderPass and subpass
909 * specify a subpass that has no depth/stencil attachment.
910 */
911 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
912 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
913 assert(pCreateInfo->pDepthStencilState);
914 dynamic->depth_bounds.min =
915 pCreateInfo->pDepthStencilState->minDepthBounds;
916 dynamic->depth_bounds.max =
917 pCreateInfo->pDepthStencilState->maxDepthBounds;
918 }
919
920 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
921 assert(pCreateInfo->pDepthStencilState);
922 dynamic->stencil_compare_mask.front =
923 pCreateInfo->pDepthStencilState->front.compareMask;
924 dynamic->stencil_compare_mask.back =
925 pCreateInfo->pDepthStencilState->back.compareMask;
926 }
927
928 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
929 assert(pCreateInfo->pDepthStencilState);
930 dynamic->stencil_write_mask.front =
931 pCreateInfo->pDepthStencilState->front.writeMask;
932 dynamic->stencil_write_mask.back =
933 pCreateInfo->pDepthStencilState->back.writeMask;
934 }
935
936 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
937 assert(pCreateInfo->pDepthStencilState);
938 dynamic->stencil_reference.front =
939 pCreateInfo->pDepthStencilState->front.reference;
940 dynamic->stencil_reference.back =
941 pCreateInfo->pDepthStencilState->back.reference;
942 }
943 }
944
945 pipeline->dynamic_state_mask = states;
946 }
947
948 static void
949 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
950 {
951 struct anv_render_pass *renderpass = NULL;
952 struct anv_subpass *subpass = NULL;
953
954 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
955 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
956 * 4.2 Graphics Pipeline.
957 */
958 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
959
960 renderpass = anv_render_pass_from_handle(info->renderPass);
961 assert(renderpass);
962
963 if (renderpass != &anv_meta_dummy_renderpass) {
964 assert(info->subpass < renderpass->subpass_count);
965 subpass = &renderpass->subpasses[info->subpass];
966 }
967
968 assert(info->stageCount >= 1);
969 assert(info->pVertexInputState);
970 assert(info->pInputAssemblyState);
971 assert(info->pViewportState);
972 assert(info->pRasterizationState);
973
974 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
975 assert(info->pDepthStencilState);
976
977 if (subpass && subpass->color_count > 0)
978 assert(info->pColorBlendState);
979
980 for (uint32_t i = 0; i < info->stageCount; ++i) {
981 switch (info->pStages[i].stage) {
982 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
983 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
984 assert(info->pTessellationState);
985 break;
986 default:
987 break;
988 }
989 }
990 }
991
992 VkResult
993 anv_pipeline_init(struct anv_pipeline *pipeline,
994 struct anv_device *device,
995 struct anv_pipeline_cache *cache,
996 const VkGraphicsPipelineCreateInfo *pCreateInfo,
997 const struct anv_graphics_pipeline_create_info *extra,
998 const VkAllocationCallbacks *alloc)
999 {
1000 VkResult result;
1001
1002 anv_validate {
1003 anv_pipeline_validate_create_info(pCreateInfo);
1004 }
1005
1006 if (alloc == NULL)
1007 alloc = &device->alloc;
1008
1009 pipeline->device = device;
1010 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1011
1012 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1013 if (result != VK_SUCCESS)
1014 return result;
1015
1016 pipeline->batch.alloc = alloc;
1017 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1018 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1019 pipeline->batch.relocs = &pipeline->batch_relocs;
1020
1021 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1022
1023 if (pCreateInfo->pTessellationState)
1024 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1025 if (pCreateInfo->pMultisampleState &&
1026 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1027 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
1028
1029 pipeline->use_repclear = extra && extra->use_repclear;
1030 pipeline->writes_point_size = false;
1031
1032 /* When we free the pipeline, we detect stages based on the NULL status
1033 * of various prog_data pointers. Make them NULL by default.
1034 */
1035 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1036 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1037
1038 pipeline->vs_simd8 = NO_KERNEL;
1039 pipeline->vs_vec4 = NO_KERNEL;
1040 pipeline->gs_kernel = NO_KERNEL;
1041
1042 pipeline->active_stages = 0;
1043 pipeline->total_scratch = 0;
1044
1045 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1046 ANV_FROM_HANDLE(anv_shader_module, module,
1047 pCreateInfo->pStages[i].module);
1048 const char *entrypoint = pCreateInfo->pStages[i].pName;
1049
1050 switch (pCreateInfo->pStages[i].stage) {
1051 case VK_SHADER_STAGE_VERTEX_BIT:
1052 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo, module, entrypoint);
1053 break;
1054 case VK_SHADER_STAGE_GEOMETRY_BIT:
1055 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo, module, entrypoint);
1056 break;
1057 case VK_SHADER_STAGE_FRAGMENT_BIT:
1058 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, module, entrypoint);
1059 break;
1060 default:
1061 anv_finishme("Unsupported shader stage");
1062 }
1063 }
1064
1065 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1066 /* Vertex is only optional if disable_vs is set */
1067 assert(extra->disable_vs);
1068 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1069 }
1070
1071 gen7_compute_urb_partition(pipeline);
1072
1073 const VkPipelineVertexInputStateCreateInfo *vi_info =
1074 pCreateInfo->pVertexInputState;
1075
1076 uint64_t inputs_read;
1077 if (extra && extra->disable_vs) {
1078 /* If the VS is disabled, just assume the user knows what they're
1079 * doing and apply the layout blindly. This can only come from
1080 * meta, so this *should* be safe.
1081 */
1082 inputs_read = ~0ull;
1083 } else {
1084 inputs_read = pipeline->vs_prog_data.inputs_read;
1085 }
1086
1087 pipeline->vb_used = 0;
1088 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1089 const VkVertexInputAttributeDescription *desc =
1090 &vi_info->pVertexAttributeDescriptions[i];
1091
1092 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1093 pipeline->vb_used |= 1 << desc->binding;
1094 }
1095
1096 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1097 const VkVertexInputBindingDescription *desc =
1098 &vi_info->pVertexBindingDescriptions[i];
1099
1100 pipeline->binding_stride[desc->binding] = desc->stride;
1101
1102 /* Step rate is programmed per vertex element (attribute), not
1103 * binding. Set up a map of which bindings step per instance, for
1104 * reference by vertex element setup. */
1105 switch (desc->inputRate) {
1106 default:
1107 case VK_VERTEX_INPUT_RATE_VERTEX:
1108 pipeline->instancing_enable[desc->binding] = false;
1109 break;
1110 case VK_VERTEX_INPUT_RATE_INSTANCE:
1111 pipeline->instancing_enable[desc->binding] = true;
1112 break;
1113 }
1114 }
1115
1116 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1117 pCreateInfo->pInputAssemblyState;
1118 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1119 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1120
1121 if (extra && extra->use_rectlist)
1122 pipeline->topology = _3DPRIM_RECTLIST;
1123
1124 return VK_SUCCESS;
1125 }
1126
1127 VkResult
1128 anv_graphics_pipeline_create(
1129 VkDevice _device,
1130 VkPipelineCache _cache,
1131 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1132 const struct anv_graphics_pipeline_create_info *extra,
1133 const VkAllocationCallbacks *pAllocator,
1134 VkPipeline *pPipeline)
1135 {
1136 ANV_FROM_HANDLE(anv_device, device, _device);
1137 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1138
1139 if (cache == NULL)
1140 cache = &device->default_pipeline_cache;
1141
1142 switch (device->info.gen) {
1143 case 7:
1144 if (device->info.is_haswell)
1145 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1146 else
1147 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1148 case 8:
1149 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1150 case 9:
1151 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1152 default:
1153 unreachable("unsupported gen\n");
1154 }
1155 }
1156
1157 VkResult anv_CreateGraphicsPipelines(
1158 VkDevice _device,
1159 VkPipelineCache pipelineCache,
1160 uint32_t count,
1161 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1162 const VkAllocationCallbacks* pAllocator,
1163 VkPipeline* pPipelines)
1164 {
1165 VkResult result = VK_SUCCESS;
1166
1167 unsigned i = 0;
1168 for (; i < count; i++) {
1169 result = anv_graphics_pipeline_create(_device,
1170 pipelineCache,
1171 &pCreateInfos[i],
1172 NULL, pAllocator, &pPipelines[i]);
1173 if (result != VK_SUCCESS) {
1174 for (unsigned j = 0; j < i; j++) {
1175 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1176 }
1177
1178 return result;
1179 }
1180 }
1181
1182 return VK_SUCCESS;
1183 }
1184
1185 static VkResult anv_compute_pipeline_create(
1186 VkDevice _device,
1187 VkPipelineCache _cache,
1188 const VkComputePipelineCreateInfo* pCreateInfo,
1189 const VkAllocationCallbacks* pAllocator,
1190 VkPipeline* pPipeline)
1191 {
1192 ANV_FROM_HANDLE(anv_device, device, _device);
1193 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1194
1195 if (cache == NULL)
1196 cache = &device->default_pipeline_cache;
1197
1198 switch (device->info.gen) {
1199 case 7:
1200 if (device->info.is_haswell)
1201 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1202 else
1203 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1204 case 8:
1205 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1206 case 9:
1207 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1208 default:
1209 unreachable("unsupported gen\n");
1210 }
1211 }
1212
1213 VkResult anv_CreateComputePipelines(
1214 VkDevice _device,
1215 VkPipelineCache pipelineCache,
1216 uint32_t count,
1217 const VkComputePipelineCreateInfo* pCreateInfos,
1218 const VkAllocationCallbacks* pAllocator,
1219 VkPipeline* pPipelines)
1220 {
1221 VkResult result = VK_SUCCESS;
1222
1223 unsigned i = 0;
1224 for (; i < count; i++) {
1225 result = anv_compute_pipeline_create(_device, pipelineCache,
1226 &pCreateInfos[i],
1227 pAllocator, &pPipelines[i]);
1228 if (result != VK_SUCCESS) {
1229 for (unsigned j = 0; j < i; j++) {
1230 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1231 }
1232
1233 return result;
1234 }
1235 }
1236
1237 return VK_SUCCESS;
1238 }