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anv/pipeline: Pull separate_shader from NIR for vue map setup
[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "brw_nir.h"
32 #include "anv_nir.h"
33 #include "glsl/nir/nir_spirv.h"
34
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
37
38 // Shader functions
39
40 VkResult anv_CreateShaderModule(
41 VkDevice _device,
42 const VkShaderModuleCreateInfo* pCreateInfo,
43 VkShaderModule* pShaderModule)
44 {
45 ANV_FROM_HANDLE(anv_device, device, _device);
46 struct anv_shader_module *module;
47
48 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
49 assert(pCreateInfo->flags == 0);
50
51 module = anv_device_alloc(device, sizeof(*module) + pCreateInfo->codeSize, 8,
52 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
53 if (module == NULL)
54 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
55
56 module->nir = NULL;
57 module->size = pCreateInfo->codeSize;
58 memcpy(module->data, pCreateInfo->pCode, module->size);
59
60 *pShaderModule = anv_shader_module_to_handle(module);
61
62 return VK_SUCCESS;
63 }
64
65 void anv_DestroyShaderModule(
66 VkDevice _device,
67 VkShaderModule _module)
68 {
69 ANV_FROM_HANDLE(anv_device, device, _device);
70 ANV_FROM_HANDLE(anv_shader_module, module, _module);
71
72 anv_device_free(device, module);
73 }
74
75 VkResult anv_CreateShader(
76 VkDevice _device,
77 const VkShaderCreateInfo* pCreateInfo,
78 VkShader* pShader)
79 {
80 ANV_FROM_HANDLE(anv_device, device, _device);
81 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->module);
82 struct anv_shader *shader;
83
84 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_CREATE_INFO);
85 assert(pCreateInfo->flags == 0);
86
87 const char *name = pCreateInfo->pName ? pCreateInfo->pName : "main";
88 size_t name_len = strlen(name);
89
90 shader = anv_device_alloc(device, sizeof(*shader) + name_len + 1, 8,
91 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
92 if (shader == NULL)
93 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
94
95 shader->module = module,
96 memcpy(shader->entrypoint, name, name_len + 1);
97
98 *pShader = anv_shader_to_handle(shader);
99
100 return VK_SUCCESS;
101 }
102
103 void anv_DestroyShader(
104 VkDevice _device,
105 VkShader _shader)
106 {
107 ANV_FROM_HANDLE(anv_device, device, _device);
108 ANV_FROM_HANDLE(anv_shader, shader, _shader);
109
110 anv_device_free(device, shader);
111 }
112
113 #define SPIR_V_MAGIC_NUMBER 0x07230203
114
115 static const gl_shader_stage vk_shader_stage_to_mesa_stage[] = {
116 [VK_SHADER_STAGE_VERTEX] = MESA_SHADER_VERTEX,
117 [VK_SHADER_STAGE_TESS_CONTROL] = -1,
118 [VK_SHADER_STAGE_TESS_EVALUATION] = -1,
119 [VK_SHADER_STAGE_GEOMETRY] = MESA_SHADER_GEOMETRY,
120 [VK_SHADER_STAGE_FRAGMENT] = MESA_SHADER_FRAGMENT,
121 [VK_SHADER_STAGE_COMPUTE] = MESA_SHADER_COMPUTE,
122 };
123
124 static bool
125 is_scalar_shader_stage(const struct brw_compiler *compiler, VkShaderStage stage)
126 {
127 switch (stage) {
128 case VK_SHADER_STAGE_VERTEX:
129 return compiler->scalar_vs;
130 case VK_SHADER_STAGE_GEOMETRY:
131 return false;
132 case VK_SHADER_STAGE_FRAGMENT:
133 case VK_SHADER_STAGE_COMPUTE:
134 return true;
135 default:
136 unreachable("Unsupported shader stage");
137 }
138 }
139
140 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
141 * we can't do that yet because we don't have the ability to copy nir.
142 */
143 static nir_shader *
144 anv_shader_compile_to_nir(struct anv_device *device,
145 struct anv_shader *shader, VkShaderStage vk_stage)
146 {
147 if (strcmp(shader->entrypoint, "main") != 0) {
148 anv_finishme("Multiple shaders per module not really supported");
149 }
150
151 gl_shader_stage stage = vk_shader_stage_to_mesa_stage[vk_stage];
152 const struct brw_compiler *compiler =
153 device->instance->physicalDevice.compiler;
154 const nir_shader_compiler_options *nir_options =
155 compiler->glsl_compiler_options[stage].NirOptions;
156
157 nir_shader *nir;
158 if (shader->module->nir) {
159 /* Some things such as our meta clear/blit code will give us a NIR
160 * shader directly. In that case, we just ignore the SPIR-V entirely
161 * and just use the NIR shader */
162 nir = shader->module->nir;
163 nir->options = nir_options;
164 } else {
165 uint32_t *spirv = (uint32_t *) shader->module->data;
166 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
167 assert(shader->module->size % 4 == 0);
168
169 nir = spirv_to_nir(spirv, shader->module->size / 4, stage, nir_options);
170 }
171 nir_validate_shader(nir);
172
173 /* Make sure the provided shader has exactly one entrypoint and that the
174 * name matches the name that came in from the VkShader.
175 */
176 nir_function_impl *entrypoint = NULL;
177 nir_foreach_overload(nir, overload) {
178 if (strcmp(shader->entrypoint, overload->function->name) == 0 &&
179 overload->impl) {
180 assert(entrypoint == NULL);
181 entrypoint = overload->impl;
182 }
183 }
184 assert(entrypoint != NULL);
185
186 brw_preprocess_nir(nir, &device->info,
187 is_scalar_shader_stage(compiler, vk_stage));
188
189 nir_shader_gather_info(nir, entrypoint);
190
191 return nir;
192 }
193
194 VkResult anv_CreatePipelineCache(
195 VkDevice device,
196 const VkPipelineCacheCreateInfo* pCreateInfo,
197 VkPipelineCache* pPipelineCache)
198 {
199 pPipelineCache->handle = 1;
200
201 stub_return(VK_SUCCESS);
202 }
203
204 void anv_DestroyPipelineCache(
205 VkDevice _device,
206 VkPipelineCache _cache)
207 {
208 }
209
210 size_t anv_GetPipelineCacheSize(
211 VkDevice device,
212 VkPipelineCache pipelineCache)
213 {
214 stub_return(0);
215 }
216
217 VkResult anv_GetPipelineCacheData(
218 VkDevice device,
219 VkPipelineCache pipelineCache,
220 void* pData)
221 {
222 stub_return(VK_UNSUPPORTED);
223 }
224
225 VkResult anv_MergePipelineCaches(
226 VkDevice device,
227 VkPipelineCache destCache,
228 uint32_t srcCacheCount,
229 const VkPipelineCache* pSrcCaches)
230 {
231 stub_return(VK_UNSUPPORTED);
232 }
233
234 void anv_DestroyPipeline(
235 VkDevice _device,
236 VkPipeline _pipeline)
237 {
238 ANV_FROM_HANDLE(anv_device, device, _device);
239 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
240
241 anv_reloc_list_finish(&pipeline->batch_relocs, pipeline->device);
242 anv_state_stream_finish(&pipeline->program_stream);
243 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
244 anv_device_free(pipeline->device, pipeline);
245 }
246
247 static const uint32_t vk_to_gen_primitive_type[] = {
248 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
249 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
250 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
251 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
252 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
253 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
254 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ,
255 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LINESTRIP_ADJ,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ,
258 [VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1
259 };
260
261 static void
262 populate_sampler_prog_key(const struct brw_device_info *devinfo,
263 struct brw_sampler_prog_key_data *key)
264 {
265 /* XXX: Handle texture swizzle on HSW- */
266 for (int i = 0; i < MAX_SAMPLERS; i++) {
267 /* Assume color sampler, no swizzling. (Works for BDW+) */
268 key->swizzles[i] = SWIZZLE_XYZW;
269 }
270 }
271
272 static void
273 populate_vs_prog_key(const struct brw_device_info *devinfo,
274 struct brw_vs_prog_key *key)
275 {
276 memset(key, 0, sizeof(*key));
277
278 populate_sampler_prog_key(devinfo, &key->tex);
279
280 /* XXX: Handle vertex input work-arounds */
281
282 /* XXX: Handle sampler_prog_key */
283 }
284
285 static void
286 populate_gs_prog_key(const struct brw_device_info *devinfo,
287 struct brw_gs_prog_key *key)
288 {
289 memset(key, 0, sizeof(*key));
290
291 populate_sampler_prog_key(devinfo, &key->tex);
292 }
293
294 static void
295 populate_wm_prog_key(const struct brw_device_info *devinfo,
296 const VkGraphicsPipelineCreateInfo *info,
297 struct brw_wm_prog_key *key)
298 {
299 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
300
301 memset(key, 0, sizeof(*key));
302
303 populate_sampler_prog_key(devinfo, &key->tex);
304
305 /* Vulkan doesn't specify a default */
306 key->high_quality_derivatives = false;
307
308 /* XXX Vulkan doesn't appear to specify */
309 key->clamp_fragment_color = false;
310
311 /* Vulkan always specifies upper-left coordinates */
312 key->drawable_height = 0;
313 key->render_to_fbo = false;
314
315 key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
316
317 key->replicate_alpha = key->nr_color_regions > 1 &&
318 info->pColorBlendState->alphaToCoverageEnable;
319
320 if (info->pMultisampleState && info->pMultisampleState->rasterSamples > 1) {
321 /* We should probably pull this out of the shader, but it's fairly
322 * harmless to compute it and then let dead-code take care of it.
323 */
324 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
325 if (key->persample_shading)
326 key->persample_2x = info->pMultisampleState->rasterSamples == 2;
327
328 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
329 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
330 }
331 }
332
333 static void
334 populate_cs_prog_key(const struct brw_device_info *devinfo,
335 struct brw_cs_prog_key *key)
336 {
337 memset(key, 0, sizeof(*key));
338
339 populate_sampler_prog_key(devinfo, &key->tex);
340 }
341
342 static nir_shader *
343 anv_pipeline_compile(struct anv_pipeline *pipeline,
344 struct anv_shader *shader,
345 VkShaderStage stage,
346 struct brw_stage_prog_data *prog_data)
347 {
348 const struct brw_compiler *compiler =
349 pipeline->device->instance->physicalDevice.compiler;
350
351 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device, shader, stage);
352 if (nir == NULL)
353 return NULL;
354
355 bool have_push_constants = false;
356 nir_foreach_variable(var, &nir->uniforms) {
357 const struct glsl_type *type = var->type;
358 if (glsl_type_is_array(type))
359 type = glsl_get_array_element(type);
360
361 if (!glsl_type_is_sampler(type)) {
362 have_push_constants = true;
363 break;
364 }
365 }
366
367 /* Figure out the number of parameters */
368 prog_data->nr_params = 0;
369
370 if (have_push_constants) {
371 /* If the shader uses any push constants at all, we'll just give
372 * them the maximum possible number
373 */
374 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
375 }
376
377 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
378 prog_data->nr_params += MAX_DYNAMIC_BUFFERS;
379
380 if (prog_data->nr_params > 0) {
381 prog_data->param = (const gl_constant_value **)
382 anv_device_alloc(pipeline->device,
383 prog_data->nr_params * sizeof(gl_constant_value *),
384 8, VK_SYSTEM_ALLOC_TYPE_INTERNAL_SHADER);
385
386 /* We now set the param values to be offsets into a
387 * anv_push_constant_data structure. Since the compiler doesn't
388 * actually dereference any of the gl_constant_value pointers in the
389 * params array, it doesn't really matter what we put here.
390 */
391 struct anv_push_constants *null_data = NULL;
392 if (have_push_constants) {
393 /* Fill out the push constants section of the param array */
394 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
395 prog_data->param[i] = (const gl_constant_value *)
396 &null_data->client_data[i * sizeof(float)];
397 }
398 }
399
400 /* Set up dynamic offsets */
401 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
402
403 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
404 anv_nir_apply_pipeline_layout(nir, pipeline->layout);
405
406 /* All binding table offsets provided by apply_pipeline_layout() are
407 * relative to the start of the bindint table (plus MAX_RTS for VS).
408 */
409 unsigned bias = stage == VK_SHADER_STAGE_FRAGMENT ? MAX_RTS : 0;
410 prog_data->binding_table.size_bytes = 0;
411 prog_data->binding_table.texture_start = bias;
412 prog_data->binding_table.ubo_start = bias;
413 prog_data->binding_table.image_start = bias;
414
415 /* Finish the optimization and compilation process */
416 brw_postprocess_nir(nir, &pipeline->device->info,
417 is_scalar_shader_stage(compiler, stage));
418
419 /* nir_lower_io will only handle the push constants; we need to set this
420 * to the full number of possible uniforms.
421 */
422 nir->num_uniforms = prog_data->nr_params;
423
424 return nir;
425 }
426
427 static uint32_t
428 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
429 const void *data, size_t size)
430 {
431 struct anv_state state =
432 anv_state_stream_alloc(&pipeline->program_stream, size, 64);
433
434 assert(size < pipeline->program_stream.block_pool->block_size);
435
436 memcpy(state.map, data, size);
437
438 return state.offset;
439 }
440 static void
441 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
442 VkShaderStage stage,
443 struct brw_stage_prog_data *prog_data)
444 {
445 struct brw_device_info *devinfo = &pipeline->device->info;
446 uint32_t max_threads[] = {
447 [VK_SHADER_STAGE_VERTEX] = devinfo->max_vs_threads,
448 [VK_SHADER_STAGE_TESS_CONTROL] = 0,
449 [VK_SHADER_STAGE_TESS_EVALUATION] = 0,
450 [VK_SHADER_STAGE_GEOMETRY] = devinfo->max_gs_threads,
451 [VK_SHADER_STAGE_FRAGMENT] = devinfo->max_wm_threads,
452 [VK_SHADER_STAGE_COMPUTE] = devinfo->max_cs_threads,
453 };
454
455 pipeline->prog_data[stage] = prog_data;
456 pipeline->active_stages |= 1 << stage;
457 pipeline->scratch_start[stage] = pipeline->total_scratch;
458 pipeline->total_scratch =
459 align_u32(pipeline->total_scratch, 1024) +
460 prog_data->total_scratch * max_threads[stage];
461 }
462
463 static VkResult
464 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
465 const VkGraphicsPipelineCreateInfo *info,
466 struct anv_shader *shader)
467 {
468 const struct brw_compiler *compiler =
469 pipeline->device->instance->physicalDevice.compiler;
470 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
471 struct brw_vs_prog_key key;
472
473 populate_vs_prog_key(&pipeline->device->info, &key);
474
475 /* TODO: Look up shader in cache */
476
477 memset(prog_data, 0, sizeof(*prog_data));
478
479 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
480 VK_SHADER_STAGE_VERTEX,
481 &prog_data->base.base);
482 if (nir == NULL)
483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
484
485 void *mem_ctx = ralloc_context(NULL);
486
487 if (shader->module->nir == NULL)
488 ralloc_steal(mem_ctx, nir);
489
490 prog_data->inputs_read = nir->info.inputs_read;
491 pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
492
493 brw_compute_vue_map(&pipeline->device->info,
494 &prog_data->base.vue_map,
495 nir->info.outputs_written,
496 nir->info.separate_shader);
497
498 unsigned code_size;
499 const unsigned *shader_code =
500 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
501 NULL, false, -1, &code_size, NULL);
502 if (shader_code == NULL) {
503 ralloc_free(mem_ctx);
504 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
505 }
506
507 const uint32_t offset =
508 anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
509 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
510 pipeline->vs_simd8 = offset;
511 pipeline->vs_vec4 = NO_KERNEL;
512 } else {
513 pipeline->vs_simd8 = NO_KERNEL;
514 pipeline->vs_vec4 = offset;
515 }
516
517 ralloc_free(mem_ctx);
518
519 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_VERTEX,
520 &prog_data->base.base);
521
522 return VK_SUCCESS;
523 }
524
525 static VkResult
526 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
527 const VkGraphicsPipelineCreateInfo *info,
528 struct anv_shader *shader)
529 {
530 const struct brw_compiler *compiler =
531 pipeline->device->instance->physicalDevice.compiler;
532 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
533 struct brw_gs_prog_key key;
534
535 populate_gs_prog_key(&pipeline->device->info, &key);
536
537 /* TODO: Look up shader in cache */
538
539 memset(prog_data, 0, sizeof(*prog_data));
540
541 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
542 VK_SHADER_STAGE_GEOMETRY,
543 &prog_data->base.base);
544 if (nir == NULL)
545 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
546
547 void *mem_ctx = ralloc_context(NULL);
548
549 if (shader->module->nir == NULL)
550 ralloc_steal(mem_ctx, nir);
551
552 brw_compute_vue_map(&pipeline->device->info,
553 &prog_data->base.vue_map,
554 nir->info.outputs_written,
555 nir->info.separate_shader);
556
557 unsigned code_size;
558 const unsigned *shader_code =
559 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
560 NULL, -1, &code_size, NULL);
561 if (shader_code == NULL) {
562 ralloc_free(mem_ctx);
563 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
564 }
565
566 /* TODO: SIMD8 GS */
567 pipeline->gs_vec4 =
568 anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
569 pipeline->gs_vertex_count = nir->info.gs.vertices_in;
570
571 ralloc_free(mem_ctx);
572
573 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_GEOMETRY,
574 &prog_data->base.base);
575
576 return VK_SUCCESS;
577 }
578
579 static VkResult
580 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
581 const VkGraphicsPipelineCreateInfo *info,
582 struct anv_shader *shader)
583 {
584 const struct brw_compiler *compiler =
585 pipeline->device->instance->physicalDevice.compiler;
586 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
587 struct brw_wm_prog_key key;
588
589 populate_wm_prog_key(&pipeline->device->info, info, &key);
590
591 if (pipeline->use_repclear)
592 key.nr_color_regions = 1;
593
594 /* TODO: Look up shader in cache */
595
596 memset(prog_data, 0, sizeof(*prog_data));
597
598 prog_data->binding_table.render_target_start = 0;
599
600 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
601 VK_SHADER_STAGE_FRAGMENT,
602 &prog_data->base);
603 if (nir == NULL)
604 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
605
606 void *mem_ctx = ralloc_context(NULL);
607
608 if (shader->module->nir == NULL)
609 ralloc_steal(mem_ctx, nir);
610
611 unsigned code_size;
612 const unsigned *shader_code =
613 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
614 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
615 if (shader_code == NULL) {
616 ralloc_free(mem_ctx);
617 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
618 }
619
620 uint32_t offset = anv_pipeline_upload_kernel(pipeline,
621 shader_code, code_size);
622 if (prog_data->no_8)
623 pipeline->ps_simd8 = NO_KERNEL;
624 else
625 pipeline->ps_simd8 = offset;
626
627 if (prog_data->no_8 || prog_data->prog_offset_16) {
628 pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
629 } else {
630 pipeline->ps_simd16 = NO_KERNEL;
631 }
632
633 pipeline->ps_ksp2 = 0;
634 pipeline->ps_grf_start2 = 0;
635 if (pipeline->ps_simd8 != NO_KERNEL) {
636 pipeline->ps_ksp0 = pipeline->ps_simd8;
637 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
638 if (pipeline->ps_simd16 != NO_KERNEL) {
639 pipeline->ps_ksp2 = pipeline->ps_simd16;
640 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
641 }
642 } else if (pipeline->ps_simd16 != NO_KERNEL) {
643 pipeline->ps_ksp0 = pipeline->ps_simd16;
644 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
645 }
646
647 ralloc_free(mem_ctx);
648
649 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_FRAGMENT,
650 &prog_data->base);
651
652 return VK_SUCCESS;
653 }
654
655 VkResult
656 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
657 const VkComputePipelineCreateInfo *info,
658 struct anv_shader *shader)
659 {
660 const struct brw_compiler *compiler =
661 pipeline->device->instance->physicalDevice.compiler;
662 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
663 struct brw_cs_prog_key key;
664
665 populate_cs_prog_key(&pipeline->device->info, &key);
666
667 /* TODO: Look up shader in cache */
668
669 memset(prog_data, 0, sizeof(*prog_data));
670
671 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
672 VK_SHADER_STAGE_COMPUTE,
673 &prog_data->base);
674 if (nir == NULL)
675 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
676
677 void *mem_ctx = ralloc_context(NULL);
678
679 if (shader->module->nir == NULL)
680 ralloc_steal(mem_ctx, nir);
681
682 unsigned code_size;
683 const unsigned *shader_code =
684 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
685 -1, &code_size, NULL);
686 if (shader_code == NULL) {
687 ralloc_free(mem_ctx);
688 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
689 }
690
691 pipeline->cs_simd = anv_pipeline_upload_kernel(pipeline,
692 shader_code, code_size);
693 ralloc_free(mem_ctx);
694
695 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_COMPUTE,
696 &prog_data->base);
697
698 return VK_SUCCESS;
699 }
700
701 static const int gen8_push_size = 32 * 1024;
702
703 static void
704 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
705 {
706 const struct brw_device_info *devinfo = &pipeline->device->info;
707 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
708 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
709 unsigned vs_entry_size_bytes = vs_size * 64;
710 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
711 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
712 unsigned gs_entry_size_bytes = gs_size * 64;
713
714 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
715 *
716 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
717 * Allocation Size is less than 9 512-bit URB entries.
718 *
719 * Similar text exists for GS.
720 */
721 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
722 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
723
724 /* URB allocations must be done in 8k chunks. */
725 unsigned chunk_size_bytes = 8192;
726
727 /* Determine the size of the URB in chunks. */
728 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
729
730 /* Reserve space for push constants */
731 unsigned push_constant_bytes = gen8_push_size;
732 unsigned push_constant_chunks =
733 push_constant_bytes / chunk_size_bytes;
734
735 /* Initially, assign each stage the minimum amount of URB space it needs,
736 * and make a note of how much additional space it "wants" (the amount of
737 * additional space it could actually make use of).
738 */
739
740 /* VS has a lower limit on the number of URB entries */
741 unsigned vs_chunks =
742 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
743 chunk_size_bytes) / chunk_size_bytes;
744 unsigned vs_wants =
745 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
746 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
747
748 unsigned gs_chunks = 0;
749 unsigned gs_wants = 0;
750 if (gs_present) {
751 /* There are two constraints on the minimum amount of URB space we can
752 * allocate:
753 *
754 * (1) We need room for at least 2 URB entries, since we always operate
755 * the GS in DUAL_OBJECT mode.
756 *
757 * (2) We can't allocate less than nr_gs_entries_granularity.
758 */
759 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
760 chunk_size_bytes) / chunk_size_bytes;
761 gs_wants =
762 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
763 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
764 }
765
766 /* There should always be enough URB space to satisfy the minimum
767 * requirements of each stage.
768 */
769 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
770 assert(total_needs <= urb_chunks);
771
772 /* Mete out remaining space (if any) in proportion to "wants". */
773 unsigned total_wants = vs_wants + gs_wants;
774 unsigned remaining_space = urb_chunks - total_needs;
775 if (remaining_space > total_wants)
776 remaining_space = total_wants;
777 if (remaining_space > 0) {
778 unsigned vs_additional = (unsigned)
779 round(vs_wants * (((double) remaining_space) / total_wants));
780 vs_chunks += vs_additional;
781 remaining_space -= vs_additional;
782 gs_chunks += remaining_space;
783 }
784
785 /* Sanity check that we haven't over-allocated. */
786 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
787
788 /* Finally, compute the number of entries that can fit in the space
789 * allocated to each stage.
790 */
791 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
792 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
793
794 /* Since we rounded up when computing *_wants, this may be slightly more
795 * than the maximum allowed amount, so correct for that.
796 */
797 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
798 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
799
800 /* Ensure that we program a multiple of the granularity. */
801 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
802 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
803
804 /* Finally, sanity check to make sure we have at least the minimum number
805 * of entries needed for each stage.
806 */
807 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
808 if (gs_present)
809 assert(nr_gs_entries >= 2);
810
811 /* Lay out the URB in the following order:
812 * - push constants
813 * - VS
814 * - GS
815 */
816 pipeline->urb.vs_start = push_constant_chunks;
817 pipeline->urb.vs_size = vs_size;
818 pipeline->urb.nr_vs_entries = nr_vs_entries;
819
820 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
821 pipeline->urb.gs_size = gs_size;
822 pipeline->urb.nr_gs_entries = nr_gs_entries;
823 }
824
825 static void
826 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
827 const VkGraphicsPipelineCreateInfo *pCreateInfo)
828 {
829 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
830 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
831 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
832
833 pipeline->dynamic_state = default_dynamic_state;
834
835 if (pCreateInfo->pDynamicState) {
836 /* Remove all of the states that are marked as dynamic */
837 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
838 for (uint32_t s = 0; s < count; s++)
839 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
840 }
841
842 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
843
844 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
845 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
846 typed_memcpy(dynamic->viewport.viewports,
847 pCreateInfo->pViewportState->pViewports,
848 pCreateInfo->pViewportState->viewportCount);
849 }
850
851 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
852 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
853 typed_memcpy(dynamic->scissor.scissors,
854 pCreateInfo->pViewportState->pScissors,
855 pCreateInfo->pViewportState->scissorCount);
856 }
857
858 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
859 assert(pCreateInfo->pRasterState);
860 dynamic->line_width = pCreateInfo->pRasterState->lineWidth;
861 }
862
863 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
864 assert(pCreateInfo->pRasterState);
865 dynamic->depth_bias.bias = pCreateInfo->pRasterState->depthBias;
866 dynamic->depth_bias.clamp = pCreateInfo->pRasterState->depthBiasClamp;
867 dynamic->depth_bias.slope_scaled =
868 pCreateInfo->pRasterState->slopeScaledDepthBias;
869 }
870
871 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
872 assert(pCreateInfo->pColorBlendState);
873 typed_memcpy(dynamic->blend_constants,
874 pCreateInfo->pColorBlendState->blendConst, 4);
875 }
876
877 /* If there is no depthstencil attachment, then don't read
878 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
879 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
880 * no need to override the depthstencil defaults in
881 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
882 *
883 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
884 *
885 * pDepthStencilState [...] may only be NULL if renderPass and subpass
886 * specify a subpass that has no depth/stencil attachment.
887 */
888 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
889 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
890 assert(pCreateInfo->pDepthStencilState);
891 dynamic->depth_bounds.min =
892 pCreateInfo->pDepthStencilState->minDepthBounds;
893 dynamic->depth_bounds.max =
894 pCreateInfo->pDepthStencilState->maxDepthBounds;
895 }
896
897 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
898 assert(pCreateInfo->pDepthStencilState);
899 dynamic->stencil_compare_mask.front =
900 pCreateInfo->pDepthStencilState->front.stencilCompareMask;
901 dynamic->stencil_compare_mask.back =
902 pCreateInfo->pDepthStencilState->back.stencilCompareMask;
903 }
904
905 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
906 assert(pCreateInfo->pDepthStencilState);
907 dynamic->stencil_write_mask.front =
908 pCreateInfo->pDepthStencilState->front.stencilWriteMask;
909 dynamic->stencil_write_mask.back =
910 pCreateInfo->pDepthStencilState->back.stencilWriteMask;
911 }
912
913 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
914 assert(pCreateInfo->pDepthStencilState);
915 dynamic->stencil_reference.front =
916 pCreateInfo->pDepthStencilState->front.stencilReference;
917 dynamic->stencil_reference.back =
918 pCreateInfo->pDepthStencilState->back.stencilReference;
919 }
920 }
921
922 pipeline->dynamic_state_mask = states;
923 }
924
925 static void
926 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
927 {
928 struct anv_render_pass *renderpass = NULL;
929 struct anv_subpass *subpass = NULL;
930
931 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
932 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
933 * 4.2 Graphics Pipeline.
934 */
935 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
936
937 renderpass = anv_render_pass_from_handle(info->renderPass);
938 assert(renderpass);
939
940 if (renderpass != &anv_meta_dummy_renderpass) {
941 assert(info->subpass < renderpass->subpass_count);
942 subpass = &renderpass->subpasses[info->subpass];
943 }
944
945 assert(info->stageCount >= 1);
946 assert(info->pVertexInputState);
947 assert(info->pInputAssemblyState);
948 assert(info->pViewportState);
949 assert(info->pRasterState);
950 assert(info->pMultisampleState);
951
952 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
953 assert(info->pDepthStencilState);
954
955 if (subpass && subpass->color_count > 0)
956 assert(info->pColorBlendState);
957
958 for (uint32_t i = 0; i < info->stageCount; ++i) {
959 switch (info->pStages[i].stage) {
960 case VK_SHADER_STAGE_TESS_CONTROL:
961 case VK_SHADER_STAGE_TESS_EVALUATION:
962 assert(info->pTessellationState);
963 break;
964 default:
965 break;
966 }
967 }
968 }
969
970 VkResult
971 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
972 const VkGraphicsPipelineCreateInfo *pCreateInfo,
973 const struct anv_graphics_pipeline_create_info *extra)
974 {
975 VkResult result;
976
977 anv_validate {
978 anv_pipeline_validate_create_info(pCreateInfo);
979 }
980
981 pipeline->device = device;
982 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
983
984 result = anv_reloc_list_init(&pipeline->batch_relocs, device);
985 if (result != VK_SUCCESS) {
986 anv_device_free(device, pipeline);
987 return result;
988 }
989 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
990 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
991 pipeline->batch.relocs = &pipeline->batch_relocs;
992
993 anv_state_stream_init(&pipeline->program_stream,
994 &device->instruction_block_pool);
995
996 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
997
998 if (pCreateInfo->pTessellationState)
999 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1000 if (pCreateInfo->pMultisampleState &&
1001 pCreateInfo->pMultisampleState->rasterSamples > 1)
1002 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
1003
1004 pipeline->use_repclear = extra && extra->use_repclear;
1005 pipeline->writes_point_size = false;
1006
1007 /* When we free the pipeline, we detect stages based on the NULL status
1008 * of various prog_data pointers. Make them NULL by default.
1009 */
1010 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1011 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1012
1013 pipeline->vs_simd8 = NO_KERNEL;
1014 pipeline->vs_vec4 = NO_KERNEL;
1015 pipeline->gs_vec4 = NO_KERNEL;
1016
1017 pipeline->active_stages = 0;
1018 pipeline->total_scratch = 0;
1019
1020 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1021 ANV_FROM_HANDLE(anv_shader, shader, pCreateInfo->pStages[i].shader);
1022
1023 switch (pCreateInfo->pStages[i].stage) {
1024 case VK_SHADER_STAGE_VERTEX:
1025 anv_pipeline_compile_vs(pipeline, pCreateInfo, shader);
1026 break;
1027 case VK_SHADER_STAGE_GEOMETRY:
1028 anv_pipeline_compile_gs(pipeline, pCreateInfo, shader);
1029 break;
1030 case VK_SHADER_STAGE_FRAGMENT:
1031 anv_pipeline_compile_fs(pipeline, pCreateInfo, shader);
1032 break;
1033 default:
1034 anv_finishme("Unsupported shader stage");
1035 }
1036 }
1037
1038 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1039 /* Vertex is only optional if disable_vs is set */
1040 assert(extra->disable_vs);
1041 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1042 }
1043
1044 gen7_compute_urb_partition(pipeline);
1045
1046 const VkPipelineVertexInputStateCreateInfo *vi_info =
1047 pCreateInfo->pVertexInputState;
1048 pipeline->vb_used = 0;
1049 for (uint32_t i = 0; i < vi_info->bindingCount; i++) {
1050 const VkVertexInputBindingDescription *desc =
1051 &vi_info->pVertexBindingDescriptions[i];
1052
1053 pipeline->vb_used |= 1 << desc->binding;
1054 pipeline->binding_stride[desc->binding] = desc->strideInBytes;
1055
1056 /* Step rate is programmed per vertex element (attribute), not
1057 * binding. Set up a map of which bindings step per instance, for
1058 * reference by vertex element setup. */
1059 switch (desc->stepRate) {
1060 default:
1061 case VK_VERTEX_INPUT_STEP_RATE_VERTEX:
1062 pipeline->instancing_enable[desc->binding] = false;
1063 break;
1064 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE:
1065 pipeline->instancing_enable[desc->binding] = true;
1066 break;
1067 }
1068 }
1069
1070 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1071 pCreateInfo->pInputAssemblyState;
1072 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1073 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1074
1075 if (extra && extra->use_rectlist)
1076 pipeline->topology = _3DPRIM_RECTLIST;
1077
1078 return VK_SUCCESS;
1079 }
1080
1081 VkResult
1082 anv_graphics_pipeline_create(
1083 VkDevice _device,
1084 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1085 const struct anv_graphics_pipeline_create_info *extra,
1086 VkPipeline *pPipeline)
1087 {
1088 ANV_FROM_HANDLE(anv_device, device, _device);
1089
1090 switch (device->info.gen) {
1091 case 7:
1092 return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
1093 case 8:
1094 return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
1095 default:
1096 unreachable("unsupported gen\n");
1097 }
1098 }
1099
1100 VkResult anv_CreateGraphicsPipelines(
1101 VkDevice _device,
1102 VkPipelineCache pipelineCache,
1103 uint32_t count,
1104 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1105 VkPipeline* pPipelines)
1106 {
1107 VkResult result = VK_SUCCESS;
1108
1109 unsigned i = 0;
1110 for (; i < count; i++) {
1111 result = anv_graphics_pipeline_create(_device, &pCreateInfos[i],
1112 NULL, &pPipelines[i]);
1113 if (result != VK_SUCCESS) {
1114 for (unsigned j = 0; j < i; j++) {
1115 anv_DestroyPipeline(_device, pPipelines[j]);
1116 }
1117
1118 return result;
1119 }
1120 }
1121
1122 return VK_SUCCESS;
1123 }
1124
1125 static VkResult anv_compute_pipeline_create(
1126 VkDevice _device,
1127 const VkComputePipelineCreateInfo* pCreateInfo,
1128 VkPipeline* pPipeline)
1129 {
1130 ANV_FROM_HANDLE(anv_device, device, _device);
1131
1132 switch (device->info.gen) {
1133 case 7:
1134 return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline);
1135 case 8:
1136 return gen8_compute_pipeline_create(_device, pCreateInfo, pPipeline);
1137 default:
1138 unreachable("unsupported gen\n");
1139 }
1140 }
1141
1142 VkResult anv_CreateComputePipelines(
1143 VkDevice _device,
1144 VkPipelineCache pipelineCache,
1145 uint32_t count,
1146 const VkComputePipelineCreateInfo* pCreateInfos,
1147 VkPipeline* pPipelines)
1148 {
1149 VkResult result = VK_SUCCESS;
1150
1151 unsigned i = 0;
1152 for (; i < count; i++) {
1153 result = anv_compute_pipeline_create(_device, &pCreateInfos[i],
1154 &pPipelines[i]);
1155 if (result != VK_SUCCESS) {
1156 for (unsigned j = 0; j < i; j++) {
1157 anv_DestroyPipeline(_device, pPipelines[j]);
1158 }
1159
1160 return result;
1161 }
1162 }
1163
1164 return VK_SUCCESS;
1165 }
1166
1167 // Pipeline layout functions
1168
1169 VkResult anv_CreatePipelineLayout(
1170 VkDevice _device,
1171 const VkPipelineLayoutCreateInfo* pCreateInfo,
1172 VkPipelineLayout* pPipelineLayout)
1173 {
1174 ANV_FROM_HANDLE(anv_device, device, _device);
1175 struct anv_pipeline_layout l, *layout;
1176
1177 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO);
1178
1179 l.num_sets = pCreateInfo->descriptorSetCount;
1180
1181 unsigned dynamic_offset_count = 0;
1182
1183 memset(l.stage, 0, sizeof(l.stage));
1184 for (uint32_t set = 0; set < pCreateInfo->descriptorSetCount; set++) {
1185 ANV_FROM_HANDLE(anv_descriptor_set_layout, set_layout,
1186 pCreateInfo->pSetLayouts[set]);
1187 l.set[set].layout = set_layout;
1188
1189 l.set[set].dynamic_offset_start = dynamic_offset_count;
1190 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1191 if (set_layout->binding[b].dynamic_offset_index >= 0)
1192 dynamic_offset_count += set_layout->binding[b].array_size;
1193 }
1194
1195 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++) {
1196 l.set[set].stage[s].surface_start = l.stage[s].surface_count;
1197 l.set[set].stage[s].sampler_start = l.stage[s].sampler_count;
1198
1199 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1200 unsigned array_size = set_layout->binding[b].array_size;
1201
1202 if (set_layout->binding[b].stage[s].surface_index >= 0) {
1203 l.stage[s].surface_count += array_size;
1204
1205 if (set_layout->binding[b].dynamic_offset_index >= 0)
1206 l.stage[s].has_dynamic_offsets = true;
1207 }
1208
1209 if (set_layout->binding[b].stage[s].sampler_index >= 0)
1210 l.stage[s].sampler_count += array_size;
1211 }
1212 }
1213 }
1214
1215 unsigned num_bindings = 0;
1216 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++)
1217 num_bindings += l.stage[s].surface_count + l.stage[s].sampler_count;
1218
1219 size_t size = sizeof(*layout) + num_bindings * sizeof(layout->entries[0]);
1220
1221 layout = anv_device_alloc(device, size, 8, VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
1222 if (layout == NULL)
1223 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1224
1225 /* Now we can actually build our surface and sampler maps */
1226 struct anv_pipeline_binding *entry = layout->entries;
1227 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++) {
1228 l.stage[s].surface_to_descriptor = entry;
1229 entry += l.stage[s].surface_count;
1230 l.stage[s].sampler_to_descriptor = entry;
1231 entry += l.stage[s].sampler_count;
1232
1233 int surface = 0;
1234 int sampler = 0;
1235 for (uint32_t set = 0; set < pCreateInfo->descriptorSetCount; set++) {
1236 struct anv_descriptor_set_layout *set_layout = l.set[set].layout;
1237
1238 unsigned set_offset = 0;
1239 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1240 unsigned array_size = set_layout->binding[b].array_size;
1241
1242 if (set_layout->binding[b].stage[s].surface_index >= 0) {
1243 assert(surface == l.set[set].stage[s].surface_start +
1244 set_layout->binding[b].stage[s].surface_index);
1245 for (unsigned i = 0; i < array_size; i++) {
1246 l.stage[s].surface_to_descriptor[surface + i].set = set;
1247 l.stage[s].surface_to_descriptor[surface + i].offset = set_offset + i;
1248 }
1249 surface += array_size;
1250 }
1251
1252 if (set_layout->binding[b].stage[s].sampler_index >= 0) {
1253 assert(sampler == l.set[set].stage[s].sampler_start +
1254 set_layout->binding[b].stage[s].sampler_index);
1255 for (unsigned i = 0; i < array_size; i++) {
1256 l.stage[s].sampler_to_descriptor[sampler + i].set = set;
1257 l.stage[s].sampler_to_descriptor[sampler + i].offset = set_offset + i;
1258 }
1259 sampler += array_size;
1260 }
1261
1262 set_offset += array_size;
1263 }
1264 }
1265 }
1266
1267 /* Finally, we're done setting it up, copy into the allocated version */
1268 *layout = l;
1269
1270 *pPipelineLayout = anv_pipeline_layout_to_handle(layout);
1271
1272 return VK_SUCCESS;
1273 }
1274
1275 void anv_DestroyPipelineLayout(
1276 VkDevice _device,
1277 VkPipelineLayout _pipelineLayout)
1278 {
1279 ANV_FROM_HANDLE(anv_device, device, _device);
1280 ANV_FROM_HANDLE(anv_pipeline_layout, pipeline_layout, _pipelineLayout);
1281
1282 anv_device_free(device, pipeline_layout);
1283 }