2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 #include "glsl/nir/nir_spirv.h"
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
40 VkResult
anv_CreateShaderModule(
42 const VkShaderModuleCreateInfo
* pCreateInfo
,
43 VkShaderModule
* pShaderModule
)
45 ANV_FROM_HANDLE(anv_device
, device
, _device
);
46 struct anv_shader_module
*module
;
48 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
49 assert(pCreateInfo
->flags
== 0);
51 module
= anv_device_alloc(device
, sizeof(*module
) + pCreateInfo
->codeSize
, 8,
52 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
54 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
57 module
->size
= pCreateInfo
->codeSize
;
58 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
60 *pShaderModule
= anv_shader_module_to_handle(module
);
65 void anv_DestroyShaderModule(
67 VkShaderModule _module
)
69 ANV_FROM_HANDLE(anv_device
, device
, _device
);
70 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
72 anv_device_free(device
, module
);
75 VkResult
anv_CreateShader(
77 const VkShaderCreateInfo
* pCreateInfo
,
80 ANV_FROM_HANDLE(anv_device
, device
, _device
);
81 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->module
);
82 struct anv_shader
*shader
;
84 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_CREATE_INFO
);
85 assert(pCreateInfo
->flags
== 0);
87 const char *name
= pCreateInfo
->pName
? pCreateInfo
->pName
: "main";
88 size_t name_len
= strlen(name
);
90 shader
= anv_device_alloc(device
, sizeof(*shader
) + name_len
+ 1, 8,
91 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
93 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
95 shader
->module
= module
,
96 memcpy(shader
->entrypoint
, name
, name_len
+ 1);
98 *pShader
= anv_shader_to_handle(shader
);
103 void anv_DestroyShader(
107 ANV_FROM_HANDLE(anv_device
, device
, _device
);
108 ANV_FROM_HANDLE(anv_shader
, shader
, _shader
);
110 anv_device_free(device
, shader
);
113 #define SPIR_V_MAGIC_NUMBER 0x07230203
115 static const gl_shader_stage vk_shader_stage_to_mesa_stage
[] = {
116 [VK_SHADER_STAGE_VERTEX
] = MESA_SHADER_VERTEX
,
117 [VK_SHADER_STAGE_TESS_CONTROL
] = -1,
118 [VK_SHADER_STAGE_TESS_EVALUATION
] = -1,
119 [VK_SHADER_STAGE_GEOMETRY
] = MESA_SHADER_GEOMETRY
,
120 [VK_SHADER_STAGE_FRAGMENT
] = MESA_SHADER_FRAGMENT
,
121 [VK_SHADER_STAGE_COMPUTE
] = MESA_SHADER_COMPUTE
,
125 is_scalar_shader_stage(const struct brw_compiler
*compiler
, VkShaderStage stage
)
128 case VK_SHADER_STAGE_VERTEX
:
129 return compiler
->scalar_vs
;
130 case VK_SHADER_STAGE_GEOMETRY
:
132 case VK_SHADER_STAGE_FRAGMENT
:
133 case VK_SHADER_STAGE_COMPUTE
:
136 unreachable("Unsupported shader stage");
140 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
141 * we can't do that yet because we don't have the ability to copy nir.
144 anv_shader_compile_to_nir(struct anv_device
*device
,
145 struct anv_shader
*shader
, VkShaderStage vk_stage
)
147 if (strcmp(shader
->entrypoint
, "main") != 0) {
148 anv_finishme("Multiple shaders per module not really supported");
151 gl_shader_stage stage
= vk_shader_stage_to_mesa_stage
[vk_stage
];
152 const struct brw_compiler
*compiler
=
153 device
->instance
->physicalDevice
.compiler
;
154 const nir_shader_compiler_options
*nir_options
=
155 compiler
->glsl_compiler_options
[stage
].NirOptions
;
158 if (shader
->module
->nir
) {
159 /* Some things such as our meta clear/blit code will give us a NIR
160 * shader directly. In that case, we just ignore the SPIR-V entirely
161 * and just use the NIR shader */
162 nir
= shader
->module
->nir
;
163 nir
->options
= nir_options
;
165 uint32_t *spirv
= (uint32_t *) shader
->module
->data
;
166 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
167 assert(shader
->module
->size
% 4 == 0);
169 nir
= spirv_to_nir(spirv
, shader
->module
->size
/ 4, stage
, nir_options
);
171 nir_validate_shader(nir
);
173 /* Vulkan uses the separate-shader linking model */
174 nir
->info
.separate_shader
= true;
176 /* Make sure the provided shader has exactly one entrypoint and that the
177 * name matches the name that came in from the VkShader.
179 nir_function_impl
*entrypoint
= NULL
;
180 nir_foreach_overload(nir
, overload
) {
181 if (strcmp(shader
->entrypoint
, overload
->function
->name
) == 0 &&
183 assert(entrypoint
== NULL
);
184 entrypoint
= overload
->impl
;
187 assert(entrypoint
!= NULL
);
189 brw_preprocess_nir(nir
, &device
->info
,
190 is_scalar_shader_stage(compiler
, vk_stage
));
192 nir_shader_gather_info(nir
, entrypoint
);
197 VkResult
anv_CreatePipelineCache(
199 const VkPipelineCacheCreateInfo
* pCreateInfo
,
200 VkPipelineCache
* pPipelineCache
)
202 pPipelineCache
->handle
= 1;
204 stub_return(VK_SUCCESS
);
207 void anv_DestroyPipelineCache(
209 VkPipelineCache _cache
)
213 size_t anv_GetPipelineCacheSize(
215 VkPipelineCache pipelineCache
)
220 VkResult
anv_GetPipelineCacheData(
222 VkPipelineCache pipelineCache
,
225 stub_return(VK_UNSUPPORTED
);
228 VkResult
anv_MergePipelineCaches(
230 VkPipelineCache destCache
,
231 uint32_t srcCacheCount
,
232 const VkPipelineCache
* pSrcCaches
)
234 stub_return(VK_UNSUPPORTED
);
237 void anv_DestroyPipeline(
239 VkPipeline _pipeline
)
241 ANV_FROM_HANDLE(anv_device
, device
, _device
);
242 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
244 anv_reloc_list_finish(&pipeline
->batch_relocs
, pipeline
->device
);
245 anv_state_stream_finish(&pipeline
->program_stream
);
246 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
247 anv_device_free(pipeline
->device
, pipeline
);
250 static const uint32_t vk_to_gen_primitive_type
[] = {
251 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
252 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
253 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
254 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
255 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
257 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ
] = _3DPRIM_LINELIST_ADJ
,
258 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ
] = _3DPRIM_LINESTRIP_ADJ
,
259 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ
] = _3DPRIM_TRILIST_ADJ
,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ
] = _3DPRIM_TRISTRIP_ADJ
,
261 [VK_PRIMITIVE_TOPOLOGY_PATCH
] = _3DPRIM_PATCHLIST_1
265 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
266 struct brw_sampler_prog_key_data
*key
)
268 /* XXX: Handle texture swizzle on HSW- */
269 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
270 /* Assume color sampler, no swizzling. (Works for BDW+) */
271 key
->swizzles
[i
] = SWIZZLE_XYZW
;
276 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
277 struct brw_vs_prog_key
*key
)
279 memset(key
, 0, sizeof(*key
));
281 populate_sampler_prog_key(devinfo
, &key
->tex
);
283 /* XXX: Handle vertex input work-arounds */
285 /* XXX: Handle sampler_prog_key */
289 populate_gs_prog_key(const struct brw_device_info
*devinfo
,
290 struct brw_gs_prog_key
*key
)
292 memset(key
, 0, sizeof(*key
));
294 populate_sampler_prog_key(devinfo
, &key
->tex
);
298 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
299 const VkGraphicsPipelineCreateInfo
*info
,
300 struct brw_wm_prog_key
*key
)
302 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
304 memset(key
, 0, sizeof(*key
));
306 populate_sampler_prog_key(devinfo
, &key
->tex
);
308 /* TODO: Fill out key->input_slots_valid */
310 /* Vulkan doesn't specify a default */
311 key
->high_quality_derivatives
= false;
313 /* XXX Vulkan doesn't appear to specify */
314 key
->clamp_fragment_color
= false;
316 /* Vulkan always specifies upper-left coordinates */
317 key
->drawable_height
= 0;
318 key
->render_to_fbo
= false;
320 key
->nr_color_regions
= render_pass
->subpasses
[info
->subpass
].color_count
;
322 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
323 info
->pColorBlendState
->alphaToCoverageEnable
;
325 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterSamples
> 1) {
326 /* We should probably pull this out of the shader, but it's fairly
327 * harmless to compute it and then let dead-code take care of it.
329 key
->persample_shading
= info
->pMultisampleState
->sampleShadingEnable
;
330 if (key
->persample_shading
)
331 key
->persample_2x
= info
->pMultisampleState
->rasterSamples
== 2;
333 key
->compute_pos_offset
= info
->pMultisampleState
->sampleShadingEnable
;
334 key
->compute_sample_id
= info
->pMultisampleState
->sampleShadingEnable
;
339 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
340 struct brw_cs_prog_key
*key
)
342 memset(key
, 0, sizeof(*key
));
344 populate_sampler_prog_key(devinfo
, &key
->tex
);
348 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
349 struct anv_shader
*shader
,
351 struct brw_stage_prog_data
*prog_data
)
353 const struct brw_compiler
*compiler
=
354 pipeline
->device
->instance
->physicalDevice
.compiler
;
356 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
, shader
, stage
);
360 anv_nir_lower_push_constants(nir
, is_scalar_shader_stage(compiler
, stage
));
362 /* Figure out the number of parameters */
363 prog_data
->nr_params
= 0;
365 if (nir
->num_uniforms
> 0) {
366 /* If the shader uses any push constants at all, we'll just give
367 * them the maximum possible number
369 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
372 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
373 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
;
375 if (prog_data
->nr_params
> 0) {
376 prog_data
->param
= (const gl_constant_value
**)
377 anv_device_alloc(pipeline
->device
,
378 prog_data
->nr_params
* sizeof(gl_constant_value
*),
379 8, VK_SYSTEM_ALLOC_TYPE_INTERNAL_SHADER
);
381 /* We now set the param values to be offsets into a
382 * anv_push_constant_data structure. Since the compiler doesn't
383 * actually dereference any of the gl_constant_value pointers in the
384 * params array, it doesn't really matter what we put here.
386 struct anv_push_constants
*null_data
= NULL
;
387 if (nir
->num_uniforms
> 0) {
388 /* Fill out the push constants section of the param array */
389 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
390 prog_data
->param
[i
] = (const gl_constant_value
*)
391 &null_data
->client_data
[i
* sizeof(float)];
395 /* Set up dynamic offsets */
396 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
398 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
399 anv_nir_apply_pipeline_layout(nir
, pipeline
->layout
);
401 /* All binding table offsets provided by apply_pipeline_layout() are
402 * relative to the start of the bindint table (plus MAX_RTS for VS).
404 unsigned bias
= stage
== VK_SHADER_STAGE_FRAGMENT
? MAX_RTS
: 0;
405 prog_data
->binding_table
.size_bytes
= 0;
406 prog_data
->binding_table
.texture_start
= bias
;
407 prog_data
->binding_table
.ubo_start
= bias
;
408 prog_data
->binding_table
.image_start
= bias
;
410 /* Finish the optimization and compilation process */
411 brw_postprocess_nir(nir
, &pipeline
->device
->info
,
412 is_scalar_shader_stage(compiler
, stage
));
414 /* nir_lower_io will only handle the push constants; we need to set this
415 * to the full number of possible uniforms.
417 nir
->num_uniforms
= prog_data
->nr_params
;
423 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
424 const void *data
, size_t size
)
426 struct anv_state state
=
427 anv_state_stream_alloc(&pipeline
->program_stream
, size
, 64);
429 assert(size
< pipeline
->program_stream
.block_pool
->block_size
);
431 memcpy(state
.map
, data
, size
);
436 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
438 struct brw_stage_prog_data
*prog_data
)
440 struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
441 uint32_t max_threads
[] = {
442 [VK_SHADER_STAGE_VERTEX
] = devinfo
->max_vs_threads
,
443 [VK_SHADER_STAGE_TESS_CONTROL
] = 0,
444 [VK_SHADER_STAGE_TESS_EVALUATION
] = 0,
445 [VK_SHADER_STAGE_GEOMETRY
] = devinfo
->max_gs_threads
,
446 [VK_SHADER_STAGE_FRAGMENT
] = devinfo
->max_wm_threads
,
447 [VK_SHADER_STAGE_COMPUTE
] = devinfo
->max_cs_threads
,
450 pipeline
->prog_data
[stage
] = prog_data
;
451 pipeline
->active_stages
|= 1 << stage
;
452 pipeline
->scratch_start
[stage
] = pipeline
->total_scratch
;
453 pipeline
->total_scratch
=
454 align_u32(pipeline
->total_scratch
, 1024) +
455 prog_data
->total_scratch
* max_threads
[stage
];
459 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
460 const VkGraphicsPipelineCreateInfo
*info
,
461 struct anv_shader
*shader
)
463 const struct brw_compiler
*compiler
=
464 pipeline
->device
->instance
->physicalDevice
.compiler
;
465 struct brw_vs_prog_data
*prog_data
= &pipeline
->vs_prog_data
;
466 struct brw_vs_prog_key key
;
468 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
470 /* TODO: Look up shader in cache */
472 memset(prog_data
, 0, sizeof(*prog_data
));
474 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
475 VK_SHADER_STAGE_VERTEX
,
476 &prog_data
->base
.base
);
478 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
480 void *mem_ctx
= ralloc_context(NULL
);
482 if (shader
->module
->nir
== NULL
)
483 ralloc_steal(mem_ctx
, nir
);
485 prog_data
->inputs_read
= nir
->info
.inputs_read
;
486 pipeline
->writes_point_size
= nir
->info
.outputs_written
& VARYING_SLOT_PSIZ
;
488 brw_compute_vue_map(&pipeline
->device
->info
,
489 &prog_data
->base
.vue_map
,
490 nir
->info
.outputs_written
,
491 nir
->info
.separate_shader
);
494 const unsigned *shader_code
=
495 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
496 NULL
, false, -1, &code_size
, NULL
);
497 if (shader_code
== NULL
) {
498 ralloc_free(mem_ctx
);
499 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
502 const uint32_t offset
=
503 anv_pipeline_upload_kernel(pipeline
, shader_code
, code_size
);
504 if (prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
505 pipeline
->vs_simd8
= offset
;
506 pipeline
->vs_vec4
= NO_KERNEL
;
508 pipeline
->vs_simd8
= NO_KERNEL
;
509 pipeline
->vs_vec4
= offset
;
512 ralloc_free(mem_ctx
);
514 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_VERTEX
,
515 &prog_data
->base
.base
);
521 anv_pipeline_compile_gs(struct anv_pipeline
*pipeline
,
522 const VkGraphicsPipelineCreateInfo
*info
,
523 struct anv_shader
*shader
)
525 const struct brw_compiler
*compiler
=
526 pipeline
->device
->instance
->physicalDevice
.compiler
;
527 struct brw_gs_prog_data
*prog_data
= &pipeline
->gs_prog_data
;
528 struct brw_gs_prog_key key
;
530 populate_gs_prog_key(&pipeline
->device
->info
, &key
);
532 /* TODO: Look up shader in cache */
534 memset(prog_data
, 0, sizeof(*prog_data
));
536 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
537 VK_SHADER_STAGE_GEOMETRY
,
538 &prog_data
->base
.base
);
540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
542 void *mem_ctx
= ralloc_context(NULL
);
544 if (shader
->module
->nir
== NULL
)
545 ralloc_steal(mem_ctx
, nir
);
547 brw_compute_vue_map(&pipeline
->device
->info
,
548 &prog_data
->base
.vue_map
,
549 nir
->info
.outputs_written
,
550 nir
->info
.separate_shader
);
553 const unsigned *shader_code
=
554 brw_compile_gs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
555 NULL
, -1, &code_size
, NULL
);
556 if (shader_code
== NULL
) {
557 ralloc_free(mem_ctx
);
558 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
563 anv_pipeline_upload_kernel(pipeline
, shader_code
, code_size
);
564 pipeline
->gs_vertex_count
= nir
->info
.gs
.vertices_in
;
566 ralloc_free(mem_ctx
);
568 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_GEOMETRY
,
569 &prog_data
->base
.base
);
575 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
576 const VkGraphicsPipelineCreateInfo
*info
,
577 struct anv_shader
*shader
)
579 const struct brw_compiler
*compiler
=
580 pipeline
->device
->instance
->physicalDevice
.compiler
;
581 struct brw_wm_prog_data
*prog_data
= &pipeline
->wm_prog_data
;
582 struct brw_wm_prog_key key
;
584 populate_wm_prog_key(&pipeline
->device
->info
, info
, &key
);
586 if (pipeline
->use_repclear
)
587 key
.nr_color_regions
= 1;
589 /* TODO: Look up shader in cache */
591 memset(prog_data
, 0, sizeof(*prog_data
));
593 prog_data
->binding_table
.render_target_start
= 0;
595 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
596 VK_SHADER_STAGE_FRAGMENT
,
599 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
601 void *mem_ctx
= ralloc_context(NULL
);
603 if (shader
->module
->nir
== NULL
)
604 ralloc_steal(mem_ctx
, nir
);
607 const unsigned *shader_code
=
608 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
609 NULL
, -1, -1, pipeline
->use_repclear
, &code_size
, NULL
);
610 if (shader_code
== NULL
) {
611 ralloc_free(mem_ctx
);
612 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
615 uint32_t offset
= anv_pipeline_upload_kernel(pipeline
,
616 shader_code
, code_size
);
618 pipeline
->ps_simd8
= NO_KERNEL
;
620 pipeline
->ps_simd8
= offset
;
622 if (prog_data
->no_8
|| prog_data
->prog_offset_16
) {
623 pipeline
->ps_simd16
= offset
+ prog_data
->prog_offset_16
;
625 pipeline
->ps_simd16
= NO_KERNEL
;
628 pipeline
->ps_ksp2
= 0;
629 pipeline
->ps_grf_start2
= 0;
630 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
631 pipeline
->ps_ksp0
= pipeline
->ps_simd8
;
632 pipeline
->ps_grf_start0
= prog_data
->base
.dispatch_grf_start_reg
;
633 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
634 pipeline
->ps_ksp2
= pipeline
->ps_simd16
;
635 pipeline
->ps_grf_start2
= prog_data
->dispatch_grf_start_reg_16
;
637 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
638 pipeline
->ps_ksp0
= pipeline
->ps_simd16
;
639 pipeline
->ps_grf_start0
= prog_data
->dispatch_grf_start_reg_16
;
642 ralloc_free(mem_ctx
);
644 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_FRAGMENT
,
651 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
652 const VkComputePipelineCreateInfo
*info
,
653 struct anv_shader
*shader
)
655 const struct brw_compiler
*compiler
=
656 pipeline
->device
->instance
->physicalDevice
.compiler
;
657 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
658 struct brw_cs_prog_key key
;
660 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
662 /* TODO: Look up shader in cache */
664 memset(prog_data
, 0, sizeof(*prog_data
));
666 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
667 VK_SHADER_STAGE_COMPUTE
,
670 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
672 void *mem_ctx
= ralloc_context(NULL
);
674 if (shader
->module
->nir
== NULL
)
675 ralloc_steal(mem_ctx
, nir
);
678 const unsigned *shader_code
=
679 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
680 -1, &code_size
, NULL
);
681 if (shader_code
== NULL
) {
682 ralloc_free(mem_ctx
);
683 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
686 pipeline
->cs_simd
= anv_pipeline_upload_kernel(pipeline
,
687 shader_code
, code_size
);
688 ralloc_free(mem_ctx
);
690 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_COMPUTE
,
696 static const int gen8_push_size
= 32 * 1024;
699 gen7_compute_urb_partition(struct anv_pipeline
*pipeline
)
701 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
702 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
703 unsigned vs_size
= vs_present
? pipeline
->vs_prog_data
.base
.urb_entry_size
: 1;
704 unsigned vs_entry_size_bytes
= vs_size
* 64;
705 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
706 unsigned gs_size
= gs_present
? pipeline
->gs_prog_data
.base
.urb_entry_size
: 1;
707 unsigned gs_entry_size_bytes
= gs_size
* 64;
709 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
711 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
712 * Allocation Size is less than 9 512-bit URB entries.
714 * Similar text exists for GS.
716 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
717 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
719 /* URB allocations must be done in 8k chunks. */
720 unsigned chunk_size_bytes
= 8192;
722 /* Determine the size of the URB in chunks. */
723 unsigned urb_chunks
= devinfo
->urb
.size
* 1024 / chunk_size_bytes
;
725 /* Reserve space for push constants */
726 unsigned push_constant_bytes
= gen8_push_size
;
727 unsigned push_constant_chunks
=
728 push_constant_bytes
/ chunk_size_bytes
;
730 /* Initially, assign each stage the minimum amount of URB space it needs,
731 * and make a note of how much additional space it "wants" (the amount of
732 * additional space it could actually make use of).
735 /* VS has a lower limit on the number of URB entries */
737 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
738 chunk_size_bytes
) / chunk_size_bytes
;
740 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
741 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
743 unsigned gs_chunks
= 0;
744 unsigned gs_wants
= 0;
746 /* There are two constraints on the minimum amount of URB space we can
749 * (1) We need room for at least 2 URB entries, since we always operate
750 * the GS in DUAL_OBJECT mode.
752 * (2) We can't allocate less than nr_gs_entries_granularity.
754 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
755 chunk_size_bytes
) / chunk_size_bytes
;
757 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
758 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
761 /* There should always be enough URB space to satisfy the minimum
762 * requirements of each stage.
764 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
765 assert(total_needs
<= urb_chunks
);
767 /* Mete out remaining space (if any) in proportion to "wants". */
768 unsigned total_wants
= vs_wants
+ gs_wants
;
769 unsigned remaining_space
= urb_chunks
- total_needs
;
770 if (remaining_space
> total_wants
)
771 remaining_space
= total_wants
;
772 if (remaining_space
> 0) {
773 unsigned vs_additional
= (unsigned)
774 round(vs_wants
* (((double) remaining_space
) / total_wants
));
775 vs_chunks
+= vs_additional
;
776 remaining_space
-= vs_additional
;
777 gs_chunks
+= remaining_space
;
780 /* Sanity check that we haven't over-allocated. */
781 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
783 /* Finally, compute the number of entries that can fit in the space
784 * allocated to each stage.
786 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
787 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
789 /* Since we rounded up when computing *_wants, this may be slightly more
790 * than the maximum allowed amount, so correct for that.
792 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
793 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
795 /* Ensure that we program a multiple of the granularity. */
796 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
797 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
799 /* Finally, sanity check to make sure we have at least the minimum number
800 * of entries needed for each stage.
802 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
804 assert(nr_gs_entries
>= 2);
806 /* Lay out the URB in the following order:
811 pipeline
->urb
.vs_start
= push_constant_chunks
;
812 pipeline
->urb
.vs_size
= vs_size
;
813 pipeline
->urb
.nr_vs_entries
= nr_vs_entries
;
815 pipeline
->urb
.gs_start
= push_constant_chunks
+ vs_chunks
;
816 pipeline
->urb
.gs_size
= gs_size
;
817 pipeline
->urb
.nr_gs_entries
= nr_gs_entries
;
821 anv_pipeline_init_dynamic_state(struct anv_pipeline
*pipeline
,
822 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
824 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
825 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
826 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
828 pipeline
->dynamic_state
= default_dynamic_state
;
830 if (pCreateInfo
->pDynamicState
) {
831 /* Remove all of the states that are marked as dynamic */
832 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
833 for (uint32_t s
= 0; s
< count
; s
++)
834 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
837 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
839 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
840 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
841 typed_memcpy(dynamic
->viewport
.viewports
,
842 pCreateInfo
->pViewportState
->pViewports
,
843 pCreateInfo
->pViewportState
->viewportCount
);
846 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
847 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
848 typed_memcpy(dynamic
->scissor
.scissors
,
849 pCreateInfo
->pViewportState
->pScissors
,
850 pCreateInfo
->pViewportState
->scissorCount
);
853 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
854 assert(pCreateInfo
->pRasterState
);
855 dynamic
->line_width
= pCreateInfo
->pRasterState
->lineWidth
;
858 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
859 assert(pCreateInfo
->pRasterState
);
860 dynamic
->depth_bias
.bias
= pCreateInfo
->pRasterState
->depthBias
;
861 dynamic
->depth_bias
.clamp
= pCreateInfo
->pRasterState
->depthBiasClamp
;
862 dynamic
->depth_bias
.slope_scaled
=
863 pCreateInfo
->pRasterState
->slopeScaledDepthBias
;
866 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
867 assert(pCreateInfo
->pColorBlendState
);
868 typed_memcpy(dynamic
->blend_constants
,
869 pCreateInfo
->pColorBlendState
->blendConst
, 4);
872 /* If there is no depthstencil attachment, then don't read
873 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
874 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
875 * no need to override the depthstencil defaults in
876 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
878 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
880 * pDepthStencilState [...] may only be NULL if renderPass and subpass
881 * specify a subpass that has no depth/stencil attachment.
883 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
884 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
885 assert(pCreateInfo
->pDepthStencilState
);
886 dynamic
->depth_bounds
.min
=
887 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
888 dynamic
->depth_bounds
.max
=
889 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
892 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
893 assert(pCreateInfo
->pDepthStencilState
);
894 dynamic
->stencil_compare_mask
.front
=
895 pCreateInfo
->pDepthStencilState
->front
.stencilCompareMask
;
896 dynamic
->stencil_compare_mask
.back
=
897 pCreateInfo
->pDepthStencilState
->back
.stencilCompareMask
;
900 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
901 assert(pCreateInfo
->pDepthStencilState
);
902 dynamic
->stencil_write_mask
.front
=
903 pCreateInfo
->pDepthStencilState
->front
.stencilWriteMask
;
904 dynamic
->stencil_write_mask
.back
=
905 pCreateInfo
->pDepthStencilState
->back
.stencilWriteMask
;
908 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
909 assert(pCreateInfo
->pDepthStencilState
);
910 dynamic
->stencil_reference
.front
=
911 pCreateInfo
->pDepthStencilState
->front
.stencilReference
;
912 dynamic
->stencil_reference
.back
=
913 pCreateInfo
->pDepthStencilState
->back
.stencilReference
;
917 pipeline
->dynamic_state_mask
= states
;
921 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
923 struct anv_render_pass
*renderpass
= NULL
;
924 struct anv_subpass
*subpass
= NULL
;
926 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
927 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
928 * 4.2 Graphics Pipeline.
930 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
932 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
935 if (renderpass
!= &anv_meta_dummy_renderpass
) {
936 assert(info
->subpass
< renderpass
->subpass_count
);
937 subpass
= &renderpass
->subpasses
[info
->subpass
];
940 assert(info
->stageCount
>= 1);
941 assert(info
->pVertexInputState
);
942 assert(info
->pInputAssemblyState
);
943 assert(info
->pViewportState
);
944 assert(info
->pRasterState
);
945 assert(info
->pMultisampleState
);
947 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
948 assert(info
->pDepthStencilState
);
950 if (subpass
&& subpass
->color_count
> 0)
951 assert(info
->pColorBlendState
);
953 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
954 switch (info
->pStages
[i
].stage
) {
955 case VK_SHADER_STAGE_TESS_CONTROL
:
956 case VK_SHADER_STAGE_TESS_EVALUATION
:
957 assert(info
->pTessellationState
);
966 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
967 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
968 const struct anv_graphics_pipeline_create_info
*extra
)
973 anv_pipeline_validate_create_info(pCreateInfo
);
976 pipeline
->device
= device
;
977 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
979 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
980 if (result
!= VK_SUCCESS
) {
981 anv_device_free(device
, pipeline
);
984 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
985 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
986 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
988 anv_state_stream_init(&pipeline
->program_stream
,
989 &device
->instruction_block_pool
);
991 anv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
993 if (pCreateInfo
->pTessellationState
)
994 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
995 if (pCreateInfo
->pMultisampleState
&&
996 pCreateInfo
->pMultisampleState
->rasterSamples
> 1)
997 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
999 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
1000 pipeline
->writes_point_size
= false;
1002 /* When we free the pipeline, we detect stages based on the NULL status
1003 * of various prog_data pointers. Make them NULL by default.
1005 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
1006 memset(pipeline
->scratch_start
, 0, sizeof(pipeline
->scratch_start
));
1008 pipeline
->vs_simd8
= NO_KERNEL
;
1009 pipeline
->vs_vec4
= NO_KERNEL
;
1010 pipeline
->gs_vec4
= NO_KERNEL
;
1012 pipeline
->active_stages
= 0;
1013 pipeline
->total_scratch
= 0;
1015 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
1016 ANV_FROM_HANDLE(anv_shader
, shader
, pCreateInfo
->pStages
[i
].shader
);
1018 switch (pCreateInfo
->pStages
[i
].stage
) {
1019 case VK_SHADER_STAGE_VERTEX
:
1020 anv_pipeline_compile_vs(pipeline
, pCreateInfo
, shader
);
1022 case VK_SHADER_STAGE_GEOMETRY
:
1023 anv_pipeline_compile_gs(pipeline
, pCreateInfo
, shader
);
1025 case VK_SHADER_STAGE_FRAGMENT
:
1026 anv_pipeline_compile_fs(pipeline
, pCreateInfo
, shader
);
1029 anv_finishme("Unsupported shader stage");
1033 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
1034 /* Vertex is only optional if disable_vs is set */
1035 assert(extra
->disable_vs
);
1036 memset(&pipeline
->vs_prog_data
, 0, sizeof(pipeline
->vs_prog_data
));
1039 gen7_compute_urb_partition(pipeline
);
1041 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1042 pCreateInfo
->pVertexInputState
;
1043 pipeline
->vb_used
= 0;
1044 for (uint32_t i
= 0; i
< vi_info
->bindingCount
; i
++) {
1045 const VkVertexInputBindingDescription
*desc
=
1046 &vi_info
->pVertexBindingDescriptions
[i
];
1048 pipeline
->vb_used
|= 1 << desc
->binding
;
1049 pipeline
->binding_stride
[desc
->binding
] = desc
->strideInBytes
;
1051 /* Step rate is programmed per vertex element (attribute), not
1052 * binding. Set up a map of which bindings step per instance, for
1053 * reference by vertex element setup. */
1054 switch (desc
->stepRate
) {
1056 case VK_VERTEX_INPUT_STEP_RATE_VERTEX
:
1057 pipeline
->instancing_enable
[desc
->binding
] = false;
1059 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE
:
1060 pipeline
->instancing_enable
[desc
->binding
] = true;
1065 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1066 pCreateInfo
->pInputAssemblyState
;
1067 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1068 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1070 if (extra
&& extra
->use_rectlist
)
1071 pipeline
->topology
= _3DPRIM_RECTLIST
;
1077 anv_graphics_pipeline_create(
1079 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1080 const struct anv_graphics_pipeline_create_info
*extra
,
1081 VkPipeline
*pPipeline
)
1083 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1085 switch (device
->info
.gen
) {
1087 return gen7_graphics_pipeline_create(_device
, pCreateInfo
, extra
, pPipeline
);
1089 return gen8_graphics_pipeline_create(_device
, pCreateInfo
, extra
, pPipeline
);
1091 unreachable("unsupported gen\n");
1095 VkResult
anv_CreateGraphicsPipelines(
1097 VkPipelineCache pipelineCache
,
1099 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1100 VkPipeline
* pPipelines
)
1102 VkResult result
= VK_SUCCESS
;
1105 for (; i
< count
; i
++) {
1106 result
= anv_graphics_pipeline_create(_device
, &pCreateInfos
[i
],
1107 NULL
, &pPipelines
[i
]);
1108 if (result
!= VK_SUCCESS
) {
1109 for (unsigned j
= 0; j
< i
; j
++) {
1110 anv_DestroyPipeline(_device
, pPipelines
[j
]);
1120 static VkResult
anv_compute_pipeline_create(
1122 const VkComputePipelineCreateInfo
* pCreateInfo
,
1123 VkPipeline
* pPipeline
)
1125 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1127 switch (device
->info
.gen
) {
1129 return gen7_compute_pipeline_create(_device
, pCreateInfo
, pPipeline
);
1131 return gen8_compute_pipeline_create(_device
, pCreateInfo
, pPipeline
);
1133 unreachable("unsupported gen\n");
1137 VkResult
anv_CreateComputePipelines(
1139 VkPipelineCache pipelineCache
,
1141 const VkComputePipelineCreateInfo
* pCreateInfos
,
1142 VkPipeline
* pPipelines
)
1144 VkResult result
= VK_SUCCESS
;
1147 for (; i
< count
; i
++) {
1148 result
= anv_compute_pipeline_create(_device
, &pCreateInfos
[i
],
1150 if (result
!= VK_SUCCESS
) {
1151 for (unsigned j
= 0; j
< i
; j
++) {
1152 anv_DestroyPipeline(_device
, pPipelines
[j
]);
1162 // Pipeline layout functions
1164 VkResult
anv_CreatePipelineLayout(
1166 const VkPipelineLayoutCreateInfo
* pCreateInfo
,
1167 VkPipelineLayout
* pPipelineLayout
)
1169 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1170 struct anv_pipeline_layout l
, *layout
;
1172 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
);
1174 l
.num_sets
= pCreateInfo
->descriptorSetCount
;
1176 unsigned dynamic_offset_count
= 0;
1178 memset(l
.stage
, 0, sizeof(l
.stage
));
1179 for (uint32_t set
= 0; set
< pCreateInfo
->descriptorSetCount
; set
++) {
1180 ANV_FROM_HANDLE(anv_descriptor_set_layout
, set_layout
,
1181 pCreateInfo
->pSetLayouts
[set
]);
1182 l
.set
[set
].layout
= set_layout
;
1184 l
.set
[set
].dynamic_offset_start
= dynamic_offset_count
;
1185 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1186 if (set_layout
->binding
[b
].dynamic_offset_index
>= 0)
1187 dynamic_offset_count
+= set_layout
->binding
[b
].array_size
;
1190 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
1191 l
.set
[set
].stage
[s
].surface_start
= l
.stage
[s
].surface_count
;
1192 l
.set
[set
].stage
[s
].sampler_start
= l
.stage
[s
].sampler_count
;
1194 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1195 unsigned array_size
= set_layout
->binding
[b
].array_size
;
1197 if (set_layout
->binding
[b
].stage
[s
].surface_index
>= 0) {
1198 l
.stage
[s
].surface_count
+= array_size
;
1200 if (set_layout
->binding
[b
].dynamic_offset_index
>= 0)
1201 l
.stage
[s
].has_dynamic_offsets
= true;
1204 if (set_layout
->binding
[b
].stage
[s
].sampler_index
>= 0)
1205 l
.stage
[s
].sampler_count
+= array_size
;
1210 unsigned num_bindings
= 0;
1211 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++)
1212 num_bindings
+= l
.stage
[s
].surface_count
+ l
.stage
[s
].sampler_count
;
1214 size_t size
= sizeof(*layout
) + num_bindings
* sizeof(layout
->entries
[0]);
1216 layout
= anv_device_alloc(device
, size
, 8, VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
1218 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1220 /* Now we can actually build our surface and sampler maps */
1221 struct anv_pipeline_binding
*entry
= layout
->entries
;
1222 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
1223 l
.stage
[s
].surface_to_descriptor
= entry
;
1224 entry
+= l
.stage
[s
].surface_count
;
1225 l
.stage
[s
].sampler_to_descriptor
= entry
;
1226 entry
+= l
.stage
[s
].sampler_count
;
1230 for (uint32_t set
= 0; set
< pCreateInfo
->descriptorSetCount
; set
++) {
1231 struct anv_descriptor_set_layout
*set_layout
= l
.set
[set
].layout
;
1233 unsigned set_offset
= 0;
1234 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1235 unsigned array_size
= set_layout
->binding
[b
].array_size
;
1237 if (set_layout
->binding
[b
].stage
[s
].surface_index
>= 0) {
1238 assert(surface
== l
.set
[set
].stage
[s
].surface_start
+
1239 set_layout
->binding
[b
].stage
[s
].surface_index
);
1240 for (unsigned i
= 0; i
< array_size
; i
++) {
1241 l
.stage
[s
].surface_to_descriptor
[surface
+ i
].set
= set
;
1242 l
.stage
[s
].surface_to_descriptor
[surface
+ i
].offset
= set_offset
+ i
;
1244 surface
+= array_size
;
1247 if (set_layout
->binding
[b
].stage
[s
].sampler_index
>= 0) {
1248 assert(sampler
== l
.set
[set
].stage
[s
].sampler_start
+
1249 set_layout
->binding
[b
].stage
[s
].sampler_index
);
1250 for (unsigned i
= 0; i
< array_size
; i
++) {
1251 l
.stage
[s
].sampler_to_descriptor
[sampler
+ i
].set
= set
;
1252 l
.stage
[s
].sampler_to_descriptor
[sampler
+ i
].offset
= set_offset
+ i
;
1254 sampler
+= array_size
;
1257 set_offset
+= array_size
;
1262 /* Finally, we're done setting it up, copy into the allocated version */
1265 *pPipelineLayout
= anv_pipeline_layout_to_handle(layout
);
1270 void anv_DestroyPipelineLayout(
1272 VkPipelineLayout _pipelineLayout
)
1274 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1275 ANV_FROM_HANDLE(anv_pipeline_layout
, pipeline_layout
, _pipelineLayout
);
1277 anv_device_free(device
, pipeline_layout
);