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anv/pipeline: Use separate-shader
[mesa.git] / src / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "brw_nir.h"
32 #include "anv_nir.h"
33 #include "glsl/nir/nir_spirv.h"
34
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
37
38 // Shader functions
39
40 VkResult anv_CreateShaderModule(
41 VkDevice _device,
42 const VkShaderModuleCreateInfo* pCreateInfo,
43 VkShaderModule* pShaderModule)
44 {
45 ANV_FROM_HANDLE(anv_device, device, _device);
46 struct anv_shader_module *module;
47
48 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
49 assert(pCreateInfo->flags == 0);
50
51 module = anv_device_alloc(device, sizeof(*module) + pCreateInfo->codeSize, 8,
52 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
53 if (module == NULL)
54 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
55
56 module->nir = NULL;
57 module->size = pCreateInfo->codeSize;
58 memcpy(module->data, pCreateInfo->pCode, module->size);
59
60 *pShaderModule = anv_shader_module_to_handle(module);
61
62 return VK_SUCCESS;
63 }
64
65 void anv_DestroyShaderModule(
66 VkDevice _device,
67 VkShaderModule _module)
68 {
69 ANV_FROM_HANDLE(anv_device, device, _device);
70 ANV_FROM_HANDLE(anv_shader_module, module, _module);
71
72 anv_device_free(device, module);
73 }
74
75 VkResult anv_CreateShader(
76 VkDevice _device,
77 const VkShaderCreateInfo* pCreateInfo,
78 VkShader* pShader)
79 {
80 ANV_FROM_HANDLE(anv_device, device, _device);
81 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->module);
82 struct anv_shader *shader;
83
84 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_CREATE_INFO);
85 assert(pCreateInfo->flags == 0);
86
87 const char *name = pCreateInfo->pName ? pCreateInfo->pName : "main";
88 size_t name_len = strlen(name);
89
90 shader = anv_device_alloc(device, sizeof(*shader) + name_len + 1, 8,
91 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
92 if (shader == NULL)
93 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
94
95 shader->module = module,
96 memcpy(shader->entrypoint, name, name_len + 1);
97
98 *pShader = anv_shader_to_handle(shader);
99
100 return VK_SUCCESS;
101 }
102
103 void anv_DestroyShader(
104 VkDevice _device,
105 VkShader _shader)
106 {
107 ANV_FROM_HANDLE(anv_device, device, _device);
108 ANV_FROM_HANDLE(anv_shader, shader, _shader);
109
110 anv_device_free(device, shader);
111 }
112
113 #define SPIR_V_MAGIC_NUMBER 0x07230203
114
115 static const gl_shader_stage vk_shader_stage_to_mesa_stage[] = {
116 [VK_SHADER_STAGE_VERTEX] = MESA_SHADER_VERTEX,
117 [VK_SHADER_STAGE_TESS_CONTROL] = -1,
118 [VK_SHADER_STAGE_TESS_EVALUATION] = -1,
119 [VK_SHADER_STAGE_GEOMETRY] = MESA_SHADER_GEOMETRY,
120 [VK_SHADER_STAGE_FRAGMENT] = MESA_SHADER_FRAGMENT,
121 [VK_SHADER_STAGE_COMPUTE] = MESA_SHADER_COMPUTE,
122 };
123
124 static bool
125 is_scalar_shader_stage(const struct brw_compiler *compiler, VkShaderStage stage)
126 {
127 switch (stage) {
128 case VK_SHADER_STAGE_VERTEX:
129 return compiler->scalar_vs;
130 case VK_SHADER_STAGE_GEOMETRY:
131 return false;
132 case VK_SHADER_STAGE_FRAGMENT:
133 case VK_SHADER_STAGE_COMPUTE:
134 return true;
135 default:
136 unreachable("Unsupported shader stage");
137 }
138 }
139
140 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
141 * we can't do that yet because we don't have the ability to copy nir.
142 */
143 static nir_shader *
144 anv_shader_compile_to_nir(struct anv_device *device,
145 struct anv_shader *shader, VkShaderStage vk_stage)
146 {
147 if (strcmp(shader->entrypoint, "main") != 0) {
148 anv_finishme("Multiple shaders per module not really supported");
149 }
150
151 gl_shader_stage stage = vk_shader_stage_to_mesa_stage[vk_stage];
152 const struct brw_compiler *compiler =
153 device->instance->physicalDevice.compiler;
154 const nir_shader_compiler_options *nir_options =
155 compiler->glsl_compiler_options[stage].NirOptions;
156
157 nir_shader *nir;
158 if (shader->module->nir) {
159 /* Some things such as our meta clear/blit code will give us a NIR
160 * shader directly. In that case, we just ignore the SPIR-V entirely
161 * and just use the NIR shader */
162 nir = shader->module->nir;
163 nir->options = nir_options;
164 } else {
165 uint32_t *spirv = (uint32_t *) shader->module->data;
166 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
167 assert(shader->module->size % 4 == 0);
168
169 nir = spirv_to_nir(spirv, shader->module->size / 4, stage, nir_options);
170 }
171 nir_validate_shader(nir);
172
173 /* Vulkan uses the separate-shader linking model */
174 nir->info.separate_shader = true;
175
176 /* Make sure the provided shader has exactly one entrypoint and that the
177 * name matches the name that came in from the VkShader.
178 */
179 nir_function_impl *entrypoint = NULL;
180 nir_foreach_overload(nir, overload) {
181 if (strcmp(shader->entrypoint, overload->function->name) == 0 &&
182 overload->impl) {
183 assert(entrypoint == NULL);
184 entrypoint = overload->impl;
185 }
186 }
187 assert(entrypoint != NULL);
188
189 brw_preprocess_nir(nir, &device->info,
190 is_scalar_shader_stage(compiler, vk_stage));
191
192 nir_shader_gather_info(nir, entrypoint);
193
194 return nir;
195 }
196
197 VkResult anv_CreatePipelineCache(
198 VkDevice device,
199 const VkPipelineCacheCreateInfo* pCreateInfo,
200 VkPipelineCache* pPipelineCache)
201 {
202 pPipelineCache->handle = 1;
203
204 stub_return(VK_SUCCESS);
205 }
206
207 void anv_DestroyPipelineCache(
208 VkDevice _device,
209 VkPipelineCache _cache)
210 {
211 }
212
213 size_t anv_GetPipelineCacheSize(
214 VkDevice device,
215 VkPipelineCache pipelineCache)
216 {
217 stub_return(0);
218 }
219
220 VkResult anv_GetPipelineCacheData(
221 VkDevice device,
222 VkPipelineCache pipelineCache,
223 void* pData)
224 {
225 stub_return(VK_UNSUPPORTED);
226 }
227
228 VkResult anv_MergePipelineCaches(
229 VkDevice device,
230 VkPipelineCache destCache,
231 uint32_t srcCacheCount,
232 const VkPipelineCache* pSrcCaches)
233 {
234 stub_return(VK_UNSUPPORTED);
235 }
236
237 void anv_DestroyPipeline(
238 VkDevice _device,
239 VkPipeline _pipeline)
240 {
241 ANV_FROM_HANDLE(anv_device, device, _device);
242 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
243
244 anv_reloc_list_finish(&pipeline->batch_relocs, pipeline->device);
245 anv_state_stream_finish(&pipeline->program_stream);
246 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
247 anv_device_free(pipeline->device, pipeline);
248 }
249
250 static const uint32_t vk_to_gen_primitive_type[] = {
251 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
252 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
253 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
254 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
255 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
257 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ,
258 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LINESTRIP_ADJ,
259 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ,
260 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ,
261 [VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1
262 };
263
264 static void
265 populate_sampler_prog_key(const struct brw_device_info *devinfo,
266 struct brw_sampler_prog_key_data *key)
267 {
268 /* XXX: Handle texture swizzle on HSW- */
269 for (int i = 0; i < MAX_SAMPLERS; i++) {
270 /* Assume color sampler, no swizzling. (Works for BDW+) */
271 key->swizzles[i] = SWIZZLE_XYZW;
272 }
273 }
274
275 static void
276 populate_vs_prog_key(const struct brw_device_info *devinfo,
277 struct brw_vs_prog_key *key)
278 {
279 memset(key, 0, sizeof(*key));
280
281 populate_sampler_prog_key(devinfo, &key->tex);
282
283 /* XXX: Handle vertex input work-arounds */
284
285 /* XXX: Handle sampler_prog_key */
286 }
287
288 static void
289 populate_gs_prog_key(const struct brw_device_info *devinfo,
290 struct brw_gs_prog_key *key)
291 {
292 memset(key, 0, sizeof(*key));
293
294 populate_sampler_prog_key(devinfo, &key->tex);
295 }
296
297 static void
298 populate_wm_prog_key(const struct brw_device_info *devinfo,
299 const VkGraphicsPipelineCreateInfo *info,
300 struct brw_wm_prog_key *key)
301 {
302 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
303
304 memset(key, 0, sizeof(*key));
305
306 populate_sampler_prog_key(devinfo, &key->tex);
307
308 /* Vulkan doesn't specify a default */
309 key->high_quality_derivatives = false;
310
311 /* XXX Vulkan doesn't appear to specify */
312 key->clamp_fragment_color = false;
313
314 /* Vulkan always specifies upper-left coordinates */
315 key->drawable_height = 0;
316 key->render_to_fbo = false;
317
318 key->nr_color_regions = render_pass->subpasses[info->subpass].color_count;
319
320 key->replicate_alpha = key->nr_color_regions > 1 &&
321 info->pColorBlendState->alphaToCoverageEnable;
322
323 if (info->pMultisampleState && info->pMultisampleState->rasterSamples > 1) {
324 /* We should probably pull this out of the shader, but it's fairly
325 * harmless to compute it and then let dead-code take care of it.
326 */
327 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
328 if (key->persample_shading)
329 key->persample_2x = info->pMultisampleState->rasterSamples == 2;
330
331 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
332 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
333 }
334 }
335
336 static void
337 populate_cs_prog_key(const struct brw_device_info *devinfo,
338 struct brw_cs_prog_key *key)
339 {
340 memset(key, 0, sizeof(*key));
341
342 populate_sampler_prog_key(devinfo, &key->tex);
343 }
344
345 static nir_shader *
346 anv_pipeline_compile(struct anv_pipeline *pipeline,
347 struct anv_shader *shader,
348 VkShaderStage stage,
349 struct brw_stage_prog_data *prog_data)
350 {
351 const struct brw_compiler *compiler =
352 pipeline->device->instance->physicalDevice.compiler;
353
354 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device, shader, stage);
355 if (nir == NULL)
356 return NULL;
357
358 bool have_push_constants = false;
359 nir_foreach_variable(var, &nir->uniforms) {
360 const struct glsl_type *type = var->type;
361 if (glsl_type_is_array(type))
362 type = glsl_get_array_element(type);
363
364 if (!glsl_type_is_sampler(type)) {
365 have_push_constants = true;
366 break;
367 }
368 }
369
370 /* Figure out the number of parameters */
371 prog_data->nr_params = 0;
372
373 if (have_push_constants) {
374 /* If the shader uses any push constants at all, we'll just give
375 * them the maximum possible number
376 */
377 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
378 }
379
380 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
381 prog_data->nr_params += MAX_DYNAMIC_BUFFERS;
382
383 if (prog_data->nr_params > 0) {
384 prog_data->param = (const gl_constant_value **)
385 anv_device_alloc(pipeline->device,
386 prog_data->nr_params * sizeof(gl_constant_value *),
387 8, VK_SYSTEM_ALLOC_TYPE_INTERNAL_SHADER);
388
389 /* We now set the param values to be offsets into a
390 * anv_push_constant_data structure. Since the compiler doesn't
391 * actually dereference any of the gl_constant_value pointers in the
392 * params array, it doesn't really matter what we put here.
393 */
394 struct anv_push_constants *null_data = NULL;
395 if (have_push_constants) {
396 /* Fill out the push constants section of the param array */
397 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
398 prog_data->param[i] = (const gl_constant_value *)
399 &null_data->client_data[i * sizeof(float)];
400 }
401 }
402
403 /* Set up dynamic offsets */
404 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
405
406 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
407 anv_nir_apply_pipeline_layout(nir, pipeline->layout);
408
409 /* All binding table offsets provided by apply_pipeline_layout() are
410 * relative to the start of the bindint table (plus MAX_RTS for VS).
411 */
412 unsigned bias = stage == VK_SHADER_STAGE_FRAGMENT ? MAX_RTS : 0;
413 prog_data->binding_table.size_bytes = 0;
414 prog_data->binding_table.texture_start = bias;
415 prog_data->binding_table.ubo_start = bias;
416 prog_data->binding_table.image_start = bias;
417
418 /* Finish the optimization and compilation process */
419 brw_postprocess_nir(nir, &pipeline->device->info,
420 is_scalar_shader_stage(compiler, stage));
421
422 /* nir_lower_io will only handle the push constants; we need to set this
423 * to the full number of possible uniforms.
424 */
425 nir->num_uniforms = prog_data->nr_params;
426
427 return nir;
428 }
429
430 static uint32_t
431 anv_pipeline_upload_kernel(struct anv_pipeline *pipeline,
432 const void *data, size_t size)
433 {
434 struct anv_state state =
435 anv_state_stream_alloc(&pipeline->program_stream, size, 64);
436
437 assert(size < pipeline->program_stream.block_pool->block_size);
438
439 memcpy(state.map, data, size);
440
441 return state.offset;
442 }
443 static void
444 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
445 VkShaderStage stage,
446 struct brw_stage_prog_data *prog_data)
447 {
448 struct brw_device_info *devinfo = &pipeline->device->info;
449 uint32_t max_threads[] = {
450 [VK_SHADER_STAGE_VERTEX] = devinfo->max_vs_threads,
451 [VK_SHADER_STAGE_TESS_CONTROL] = 0,
452 [VK_SHADER_STAGE_TESS_EVALUATION] = 0,
453 [VK_SHADER_STAGE_GEOMETRY] = devinfo->max_gs_threads,
454 [VK_SHADER_STAGE_FRAGMENT] = devinfo->max_wm_threads,
455 [VK_SHADER_STAGE_COMPUTE] = devinfo->max_cs_threads,
456 };
457
458 pipeline->prog_data[stage] = prog_data;
459 pipeline->active_stages |= 1 << stage;
460 pipeline->scratch_start[stage] = pipeline->total_scratch;
461 pipeline->total_scratch =
462 align_u32(pipeline->total_scratch, 1024) +
463 prog_data->total_scratch * max_threads[stage];
464 }
465
466 static VkResult
467 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
468 const VkGraphicsPipelineCreateInfo *info,
469 struct anv_shader *shader)
470 {
471 const struct brw_compiler *compiler =
472 pipeline->device->instance->physicalDevice.compiler;
473 struct brw_vs_prog_data *prog_data = &pipeline->vs_prog_data;
474 struct brw_vs_prog_key key;
475
476 populate_vs_prog_key(&pipeline->device->info, &key);
477
478 /* TODO: Look up shader in cache */
479
480 memset(prog_data, 0, sizeof(*prog_data));
481
482 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
483 VK_SHADER_STAGE_VERTEX,
484 &prog_data->base.base);
485 if (nir == NULL)
486 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
487
488 void *mem_ctx = ralloc_context(NULL);
489
490 if (shader->module->nir == NULL)
491 ralloc_steal(mem_ctx, nir);
492
493 prog_data->inputs_read = nir->info.inputs_read;
494 pipeline->writes_point_size = nir->info.outputs_written & VARYING_SLOT_PSIZ;
495
496 brw_compute_vue_map(&pipeline->device->info,
497 &prog_data->base.vue_map,
498 nir->info.outputs_written,
499 nir->info.separate_shader);
500
501 unsigned code_size;
502 const unsigned *shader_code =
503 brw_compile_vs(compiler, NULL, mem_ctx, &key, prog_data, nir,
504 NULL, false, -1, &code_size, NULL);
505 if (shader_code == NULL) {
506 ralloc_free(mem_ctx);
507 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
508 }
509
510 const uint32_t offset =
511 anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
512 if (prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
513 pipeline->vs_simd8 = offset;
514 pipeline->vs_vec4 = NO_KERNEL;
515 } else {
516 pipeline->vs_simd8 = NO_KERNEL;
517 pipeline->vs_vec4 = offset;
518 }
519
520 ralloc_free(mem_ctx);
521
522 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_VERTEX,
523 &prog_data->base.base);
524
525 return VK_SUCCESS;
526 }
527
528 static VkResult
529 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
530 const VkGraphicsPipelineCreateInfo *info,
531 struct anv_shader *shader)
532 {
533 const struct brw_compiler *compiler =
534 pipeline->device->instance->physicalDevice.compiler;
535 struct brw_gs_prog_data *prog_data = &pipeline->gs_prog_data;
536 struct brw_gs_prog_key key;
537
538 populate_gs_prog_key(&pipeline->device->info, &key);
539
540 /* TODO: Look up shader in cache */
541
542 memset(prog_data, 0, sizeof(*prog_data));
543
544 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
545 VK_SHADER_STAGE_GEOMETRY,
546 &prog_data->base.base);
547 if (nir == NULL)
548 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
549
550 void *mem_ctx = ralloc_context(NULL);
551
552 if (shader->module->nir == NULL)
553 ralloc_steal(mem_ctx, nir);
554
555 brw_compute_vue_map(&pipeline->device->info,
556 &prog_data->base.vue_map,
557 nir->info.outputs_written,
558 nir->info.separate_shader);
559
560 unsigned code_size;
561 const unsigned *shader_code =
562 brw_compile_gs(compiler, NULL, mem_ctx, &key, prog_data, nir,
563 NULL, -1, &code_size, NULL);
564 if (shader_code == NULL) {
565 ralloc_free(mem_ctx);
566 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
567 }
568
569 /* TODO: SIMD8 GS */
570 pipeline->gs_vec4 =
571 anv_pipeline_upload_kernel(pipeline, shader_code, code_size);
572 pipeline->gs_vertex_count = nir->info.gs.vertices_in;
573
574 ralloc_free(mem_ctx);
575
576 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_GEOMETRY,
577 &prog_data->base.base);
578
579 return VK_SUCCESS;
580 }
581
582 static VkResult
583 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
584 const VkGraphicsPipelineCreateInfo *info,
585 struct anv_shader *shader)
586 {
587 const struct brw_compiler *compiler =
588 pipeline->device->instance->physicalDevice.compiler;
589 struct brw_wm_prog_data *prog_data = &pipeline->wm_prog_data;
590 struct brw_wm_prog_key key;
591
592 populate_wm_prog_key(&pipeline->device->info, info, &key);
593
594 if (pipeline->use_repclear)
595 key.nr_color_regions = 1;
596
597 /* TODO: Look up shader in cache */
598
599 memset(prog_data, 0, sizeof(*prog_data));
600
601 prog_data->binding_table.render_target_start = 0;
602
603 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
604 VK_SHADER_STAGE_FRAGMENT,
605 &prog_data->base);
606 if (nir == NULL)
607 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
608
609 void *mem_ctx = ralloc_context(NULL);
610
611 if (shader->module->nir == NULL)
612 ralloc_steal(mem_ctx, nir);
613
614 unsigned code_size;
615 const unsigned *shader_code =
616 brw_compile_fs(compiler, NULL, mem_ctx, &key, prog_data, nir,
617 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
618 if (shader_code == NULL) {
619 ralloc_free(mem_ctx);
620 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
621 }
622
623 uint32_t offset = anv_pipeline_upload_kernel(pipeline,
624 shader_code, code_size);
625 if (prog_data->no_8)
626 pipeline->ps_simd8 = NO_KERNEL;
627 else
628 pipeline->ps_simd8 = offset;
629
630 if (prog_data->no_8 || prog_data->prog_offset_16) {
631 pipeline->ps_simd16 = offset + prog_data->prog_offset_16;
632 } else {
633 pipeline->ps_simd16 = NO_KERNEL;
634 }
635
636 pipeline->ps_ksp2 = 0;
637 pipeline->ps_grf_start2 = 0;
638 if (pipeline->ps_simd8 != NO_KERNEL) {
639 pipeline->ps_ksp0 = pipeline->ps_simd8;
640 pipeline->ps_grf_start0 = prog_data->base.dispatch_grf_start_reg;
641 if (pipeline->ps_simd16 != NO_KERNEL) {
642 pipeline->ps_ksp2 = pipeline->ps_simd16;
643 pipeline->ps_grf_start2 = prog_data->dispatch_grf_start_reg_16;
644 }
645 } else if (pipeline->ps_simd16 != NO_KERNEL) {
646 pipeline->ps_ksp0 = pipeline->ps_simd16;
647 pipeline->ps_grf_start0 = prog_data->dispatch_grf_start_reg_16;
648 }
649
650 ralloc_free(mem_ctx);
651
652 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_FRAGMENT,
653 &prog_data->base);
654
655 return VK_SUCCESS;
656 }
657
658 VkResult
659 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
660 const VkComputePipelineCreateInfo *info,
661 struct anv_shader *shader)
662 {
663 const struct brw_compiler *compiler =
664 pipeline->device->instance->physicalDevice.compiler;
665 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
666 struct brw_cs_prog_key key;
667
668 populate_cs_prog_key(&pipeline->device->info, &key);
669
670 /* TODO: Look up shader in cache */
671
672 memset(prog_data, 0, sizeof(*prog_data));
673
674 nir_shader *nir = anv_pipeline_compile(pipeline, shader,
675 VK_SHADER_STAGE_COMPUTE,
676 &prog_data->base);
677 if (nir == NULL)
678 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
679
680 void *mem_ctx = ralloc_context(NULL);
681
682 if (shader->module->nir == NULL)
683 ralloc_steal(mem_ctx, nir);
684
685 unsigned code_size;
686 const unsigned *shader_code =
687 brw_compile_cs(compiler, NULL, mem_ctx, &key, prog_data, nir,
688 -1, &code_size, NULL);
689 if (shader_code == NULL) {
690 ralloc_free(mem_ctx);
691 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
692 }
693
694 pipeline->cs_simd = anv_pipeline_upload_kernel(pipeline,
695 shader_code, code_size);
696 ralloc_free(mem_ctx);
697
698 anv_pipeline_add_compiled_stage(pipeline, VK_SHADER_STAGE_COMPUTE,
699 &prog_data->base);
700
701 return VK_SUCCESS;
702 }
703
704 static const int gen8_push_size = 32 * 1024;
705
706 static void
707 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
708 {
709 const struct brw_device_info *devinfo = &pipeline->device->info;
710 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
711 unsigned vs_size = vs_present ? pipeline->vs_prog_data.base.urb_entry_size : 1;
712 unsigned vs_entry_size_bytes = vs_size * 64;
713 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
714 unsigned gs_size = gs_present ? pipeline->gs_prog_data.base.urb_entry_size : 1;
715 unsigned gs_entry_size_bytes = gs_size * 64;
716
717 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
718 *
719 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
720 * Allocation Size is less than 9 512-bit URB entries.
721 *
722 * Similar text exists for GS.
723 */
724 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
725 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
726
727 /* URB allocations must be done in 8k chunks. */
728 unsigned chunk_size_bytes = 8192;
729
730 /* Determine the size of the URB in chunks. */
731 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
732
733 /* Reserve space for push constants */
734 unsigned push_constant_bytes = gen8_push_size;
735 unsigned push_constant_chunks =
736 push_constant_bytes / chunk_size_bytes;
737
738 /* Initially, assign each stage the minimum amount of URB space it needs,
739 * and make a note of how much additional space it "wants" (the amount of
740 * additional space it could actually make use of).
741 */
742
743 /* VS has a lower limit on the number of URB entries */
744 unsigned vs_chunks =
745 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
746 chunk_size_bytes) / chunk_size_bytes;
747 unsigned vs_wants =
748 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
749 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
750
751 unsigned gs_chunks = 0;
752 unsigned gs_wants = 0;
753 if (gs_present) {
754 /* There are two constraints on the minimum amount of URB space we can
755 * allocate:
756 *
757 * (1) We need room for at least 2 URB entries, since we always operate
758 * the GS in DUAL_OBJECT mode.
759 *
760 * (2) We can't allocate less than nr_gs_entries_granularity.
761 */
762 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
763 chunk_size_bytes) / chunk_size_bytes;
764 gs_wants =
765 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
766 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
767 }
768
769 /* There should always be enough URB space to satisfy the minimum
770 * requirements of each stage.
771 */
772 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
773 assert(total_needs <= urb_chunks);
774
775 /* Mete out remaining space (if any) in proportion to "wants". */
776 unsigned total_wants = vs_wants + gs_wants;
777 unsigned remaining_space = urb_chunks - total_needs;
778 if (remaining_space > total_wants)
779 remaining_space = total_wants;
780 if (remaining_space > 0) {
781 unsigned vs_additional = (unsigned)
782 round(vs_wants * (((double) remaining_space) / total_wants));
783 vs_chunks += vs_additional;
784 remaining_space -= vs_additional;
785 gs_chunks += remaining_space;
786 }
787
788 /* Sanity check that we haven't over-allocated. */
789 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
790
791 /* Finally, compute the number of entries that can fit in the space
792 * allocated to each stage.
793 */
794 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
795 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
796
797 /* Since we rounded up when computing *_wants, this may be slightly more
798 * than the maximum allowed amount, so correct for that.
799 */
800 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
801 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
802
803 /* Ensure that we program a multiple of the granularity. */
804 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
805 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
806
807 /* Finally, sanity check to make sure we have at least the minimum number
808 * of entries needed for each stage.
809 */
810 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
811 if (gs_present)
812 assert(nr_gs_entries >= 2);
813
814 /* Lay out the URB in the following order:
815 * - push constants
816 * - VS
817 * - GS
818 */
819 pipeline->urb.vs_start = push_constant_chunks;
820 pipeline->urb.vs_size = vs_size;
821 pipeline->urb.nr_vs_entries = nr_vs_entries;
822
823 pipeline->urb.gs_start = push_constant_chunks + vs_chunks;
824 pipeline->urb.gs_size = gs_size;
825 pipeline->urb.nr_gs_entries = nr_gs_entries;
826 }
827
828 static void
829 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
830 const VkGraphicsPipelineCreateInfo *pCreateInfo)
831 {
832 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
833 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
834 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
835
836 pipeline->dynamic_state = default_dynamic_state;
837
838 if (pCreateInfo->pDynamicState) {
839 /* Remove all of the states that are marked as dynamic */
840 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
841 for (uint32_t s = 0; s < count; s++)
842 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
843 }
844
845 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
846
847 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
848 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
849 typed_memcpy(dynamic->viewport.viewports,
850 pCreateInfo->pViewportState->pViewports,
851 pCreateInfo->pViewportState->viewportCount);
852 }
853
854 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
855 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
856 typed_memcpy(dynamic->scissor.scissors,
857 pCreateInfo->pViewportState->pScissors,
858 pCreateInfo->pViewportState->scissorCount);
859 }
860
861 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
862 assert(pCreateInfo->pRasterState);
863 dynamic->line_width = pCreateInfo->pRasterState->lineWidth;
864 }
865
866 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
867 assert(pCreateInfo->pRasterState);
868 dynamic->depth_bias.bias = pCreateInfo->pRasterState->depthBias;
869 dynamic->depth_bias.clamp = pCreateInfo->pRasterState->depthBiasClamp;
870 dynamic->depth_bias.slope_scaled =
871 pCreateInfo->pRasterState->slopeScaledDepthBias;
872 }
873
874 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
875 assert(pCreateInfo->pColorBlendState);
876 typed_memcpy(dynamic->blend_constants,
877 pCreateInfo->pColorBlendState->blendConst, 4);
878 }
879
880 /* If there is no depthstencil attachment, then don't read
881 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
882 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
883 * no need to override the depthstencil defaults in
884 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
885 *
886 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
887 *
888 * pDepthStencilState [...] may only be NULL if renderPass and subpass
889 * specify a subpass that has no depth/stencil attachment.
890 */
891 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
892 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
893 assert(pCreateInfo->pDepthStencilState);
894 dynamic->depth_bounds.min =
895 pCreateInfo->pDepthStencilState->minDepthBounds;
896 dynamic->depth_bounds.max =
897 pCreateInfo->pDepthStencilState->maxDepthBounds;
898 }
899
900 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
901 assert(pCreateInfo->pDepthStencilState);
902 dynamic->stencil_compare_mask.front =
903 pCreateInfo->pDepthStencilState->front.stencilCompareMask;
904 dynamic->stencil_compare_mask.back =
905 pCreateInfo->pDepthStencilState->back.stencilCompareMask;
906 }
907
908 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
909 assert(pCreateInfo->pDepthStencilState);
910 dynamic->stencil_write_mask.front =
911 pCreateInfo->pDepthStencilState->front.stencilWriteMask;
912 dynamic->stencil_write_mask.back =
913 pCreateInfo->pDepthStencilState->back.stencilWriteMask;
914 }
915
916 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
917 assert(pCreateInfo->pDepthStencilState);
918 dynamic->stencil_reference.front =
919 pCreateInfo->pDepthStencilState->front.stencilReference;
920 dynamic->stencil_reference.back =
921 pCreateInfo->pDepthStencilState->back.stencilReference;
922 }
923 }
924
925 pipeline->dynamic_state_mask = states;
926 }
927
928 static void
929 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
930 {
931 struct anv_render_pass *renderpass = NULL;
932 struct anv_subpass *subpass = NULL;
933
934 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
935 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
936 * 4.2 Graphics Pipeline.
937 */
938 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
939
940 renderpass = anv_render_pass_from_handle(info->renderPass);
941 assert(renderpass);
942
943 if (renderpass != &anv_meta_dummy_renderpass) {
944 assert(info->subpass < renderpass->subpass_count);
945 subpass = &renderpass->subpasses[info->subpass];
946 }
947
948 assert(info->stageCount >= 1);
949 assert(info->pVertexInputState);
950 assert(info->pInputAssemblyState);
951 assert(info->pViewportState);
952 assert(info->pRasterState);
953 assert(info->pMultisampleState);
954
955 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
956 assert(info->pDepthStencilState);
957
958 if (subpass && subpass->color_count > 0)
959 assert(info->pColorBlendState);
960
961 for (uint32_t i = 0; i < info->stageCount; ++i) {
962 switch (info->pStages[i].stage) {
963 case VK_SHADER_STAGE_TESS_CONTROL:
964 case VK_SHADER_STAGE_TESS_EVALUATION:
965 assert(info->pTessellationState);
966 break;
967 default:
968 break;
969 }
970 }
971 }
972
973 VkResult
974 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
975 const VkGraphicsPipelineCreateInfo *pCreateInfo,
976 const struct anv_graphics_pipeline_create_info *extra)
977 {
978 VkResult result;
979
980 anv_validate {
981 anv_pipeline_validate_create_info(pCreateInfo);
982 }
983
984 pipeline->device = device;
985 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
986
987 result = anv_reloc_list_init(&pipeline->batch_relocs, device);
988 if (result != VK_SUCCESS) {
989 anv_device_free(device, pipeline);
990 return result;
991 }
992 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
993 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
994 pipeline->batch.relocs = &pipeline->batch_relocs;
995
996 anv_state_stream_init(&pipeline->program_stream,
997 &device->instruction_block_pool);
998
999 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1000
1001 if (pCreateInfo->pTessellationState)
1002 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
1003 if (pCreateInfo->pMultisampleState &&
1004 pCreateInfo->pMultisampleState->rasterSamples > 1)
1005 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
1006
1007 pipeline->use_repclear = extra && extra->use_repclear;
1008 pipeline->writes_point_size = false;
1009
1010 /* When we free the pipeline, we detect stages based on the NULL status
1011 * of various prog_data pointers. Make them NULL by default.
1012 */
1013 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1014 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1015
1016 pipeline->vs_simd8 = NO_KERNEL;
1017 pipeline->vs_vec4 = NO_KERNEL;
1018 pipeline->gs_vec4 = NO_KERNEL;
1019
1020 pipeline->active_stages = 0;
1021 pipeline->total_scratch = 0;
1022
1023 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1024 ANV_FROM_HANDLE(anv_shader, shader, pCreateInfo->pStages[i].shader);
1025
1026 switch (pCreateInfo->pStages[i].stage) {
1027 case VK_SHADER_STAGE_VERTEX:
1028 anv_pipeline_compile_vs(pipeline, pCreateInfo, shader);
1029 break;
1030 case VK_SHADER_STAGE_GEOMETRY:
1031 anv_pipeline_compile_gs(pipeline, pCreateInfo, shader);
1032 break;
1033 case VK_SHADER_STAGE_FRAGMENT:
1034 anv_pipeline_compile_fs(pipeline, pCreateInfo, shader);
1035 break;
1036 default:
1037 anv_finishme("Unsupported shader stage");
1038 }
1039 }
1040
1041 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1042 /* Vertex is only optional if disable_vs is set */
1043 assert(extra->disable_vs);
1044 memset(&pipeline->vs_prog_data, 0, sizeof(pipeline->vs_prog_data));
1045 }
1046
1047 gen7_compute_urb_partition(pipeline);
1048
1049 const VkPipelineVertexInputStateCreateInfo *vi_info =
1050 pCreateInfo->pVertexInputState;
1051 pipeline->vb_used = 0;
1052 for (uint32_t i = 0; i < vi_info->bindingCount; i++) {
1053 const VkVertexInputBindingDescription *desc =
1054 &vi_info->pVertexBindingDescriptions[i];
1055
1056 pipeline->vb_used |= 1 << desc->binding;
1057 pipeline->binding_stride[desc->binding] = desc->strideInBytes;
1058
1059 /* Step rate is programmed per vertex element (attribute), not
1060 * binding. Set up a map of which bindings step per instance, for
1061 * reference by vertex element setup. */
1062 switch (desc->stepRate) {
1063 default:
1064 case VK_VERTEX_INPUT_STEP_RATE_VERTEX:
1065 pipeline->instancing_enable[desc->binding] = false;
1066 break;
1067 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE:
1068 pipeline->instancing_enable[desc->binding] = true;
1069 break;
1070 }
1071 }
1072
1073 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1074 pCreateInfo->pInputAssemblyState;
1075 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1076 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1077
1078 if (extra && extra->use_rectlist)
1079 pipeline->topology = _3DPRIM_RECTLIST;
1080
1081 return VK_SUCCESS;
1082 }
1083
1084 VkResult
1085 anv_graphics_pipeline_create(
1086 VkDevice _device,
1087 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1088 const struct anv_graphics_pipeline_create_info *extra,
1089 VkPipeline *pPipeline)
1090 {
1091 ANV_FROM_HANDLE(anv_device, device, _device);
1092
1093 switch (device->info.gen) {
1094 case 7:
1095 return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
1096 case 8:
1097 return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
1098 default:
1099 unreachable("unsupported gen\n");
1100 }
1101 }
1102
1103 VkResult anv_CreateGraphicsPipelines(
1104 VkDevice _device,
1105 VkPipelineCache pipelineCache,
1106 uint32_t count,
1107 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1108 VkPipeline* pPipelines)
1109 {
1110 VkResult result = VK_SUCCESS;
1111
1112 unsigned i = 0;
1113 for (; i < count; i++) {
1114 result = anv_graphics_pipeline_create(_device, &pCreateInfos[i],
1115 NULL, &pPipelines[i]);
1116 if (result != VK_SUCCESS) {
1117 for (unsigned j = 0; j < i; j++) {
1118 anv_DestroyPipeline(_device, pPipelines[j]);
1119 }
1120
1121 return result;
1122 }
1123 }
1124
1125 return VK_SUCCESS;
1126 }
1127
1128 static VkResult anv_compute_pipeline_create(
1129 VkDevice _device,
1130 const VkComputePipelineCreateInfo* pCreateInfo,
1131 VkPipeline* pPipeline)
1132 {
1133 ANV_FROM_HANDLE(anv_device, device, _device);
1134
1135 switch (device->info.gen) {
1136 case 7:
1137 return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline);
1138 case 8:
1139 return gen8_compute_pipeline_create(_device, pCreateInfo, pPipeline);
1140 default:
1141 unreachable("unsupported gen\n");
1142 }
1143 }
1144
1145 VkResult anv_CreateComputePipelines(
1146 VkDevice _device,
1147 VkPipelineCache pipelineCache,
1148 uint32_t count,
1149 const VkComputePipelineCreateInfo* pCreateInfos,
1150 VkPipeline* pPipelines)
1151 {
1152 VkResult result = VK_SUCCESS;
1153
1154 unsigned i = 0;
1155 for (; i < count; i++) {
1156 result = anv_compute_pipeline_create(_device, &pCreateInfos[i],
1157 &pPipelines[i]);
1158 if (result != VK_SUCCESS) {
1159 for (unsigned j = 0; j < i; j++) {
1160 anv_DestroyPipeline(_device, pPipelines[j]);
1161 }
1162
1163 return result;
1164 }
1165 }
1166
1167 return VK_SUCCESS;
1168 }
1169
1170 // Pipeline layout functions
1171
1172 VkResult anv_CreatePipelineLayout(
1173 VkDevice _device,
1174 const VkPipelineLayoutCreateInfo* pCreateInfo,
1175 VkPipelineLayout* pPipelineLayout)
1176 {
1177 ANV_FROM_HANDLE(anv_device, device, _device);
1178 struct anv_pipeline_layout l, *layout;
1179
1180 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO);
1181
1182 l.num_sets = pCreateInfo->descriptorSetCount;
1183
1184 unsigned dynamic_offset_count = 0;
1185
1186 memset(l.stage, 0, sizeof(l.stage));
1187 for (uint32_t set = 0; set < pCreateInfo->descriptorSetCount; set++) {
1188 ANV_FROM_HANDLE(anv_descriptor_set_layout, set_layout,
1189 pCreateInfo->pSetLayouts[set]);
1190 l.set[set].layout = set_layout;
1191
1192 l.set[set].dynamic_offset_start = dynamic_offset_count;
1193 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1194 if (set_layout->binding[b].dynamic_offset_index >= 0)
1195 dynamic_offset_count += set_layout->binding[b].array_size;
1196 }
1197
1198 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++) {
1199 l.set[set].stage[s].surface_start = l.stage[s].surface_count;
1200 l.set[set].stage[s].sampler_start = l.stage[s].sampler_count;
1201
1202 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1203 unsigned array_size = set_layout->binding[b].array_size;
1204
1205 if (set_layout->binding[b].stage[s].surface_index >= 0) {
1206 l.stage[s].surface_count += array_size;
1207
1208 if (set_layout->binding[b].dynamic_offset_index >= 0)
1209 l.stage[s].has_dynamic_offsets = true;
1210 }
1211
1212 if (set_layout->binding[b].stage[s].sampler_index >= 0)
1213 l.stage[s].sampler_count += array_size;
1214 }
1215 }
1216 }
1217
1218 unsigned num_bindings = 0;
1219 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++)
1220 num_bindings += l.stage[s].surface_count + l.stage[s].sampler_count;
1221
1222 size_t size = sizeof(*layout) + num_bindings * sizeof(layout->entries[0]);
1223
1224 layout = anv_device_alloc(device, size, 8, VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
1225 if (layout == NULL)
1226 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1227
1228 /* Now we can actually build our surface and sampler maps */
1229 struct anv_pipeline_binding *entry = layout->entries;
1230 for (VkShaderStage s = 0; s < VK_SHADER_STAGE_NUM; s++) {
1231 l.stage[s].surface_to_descriptor = entry;
1232 entry += l.stage[s].surface_count;
1233 l.stage[s].sampler_to_descriptor = entry;
1234 entry += l.stage[s].sampler_count;
1235
1236 int surface = 0;
1237 int sampler = 0;
1238 for (uint32_t set = 0; set < pCreateInfo->descriptorSetCount; set++) {
1239 struct anv_descriptor_set_layout *set_layout = l.set[set].layout;
1240
1241 unsigned set_offset = 0;
1242 for (uint32_t b = 0; b < set_layout->binding_count; b++) {
1243 unsigned array_size = set_layout->binding[b].array_size;
1244
1245 if (set_layout->binding[b].stage[s].surface_index >= 0) {
1246 assert(surface == l.set[set].stage[s].surface_start +
1247 set_layout->binding[b].stage[s].surface_index);
1248 for (unsigned i = 0; i < array_size; i++) {
1249 l.stage[s].surface_to_descriptor[surface + i].set = set;
1250 l.stage[s].surface_to_descriptor[surface + i].offset = set_offset + i;
1251 }
1252 surface += array_size;
1253 }
1254
1255 if (set_layout->binding[b].stage[s].sampler_index >= 0) {
1256 assert(sampler == l.set[set].stage[s].sampler_start +
1257 set_layout->binding[b].stage[s].sampler_index);
1258 for (unsigned i = 0; i < array_size; i++) {
1259 l.stage[s].sampler_to_descriptor[sampler + i].set = set;
1260 l.stage[s].sampler_to_descriptor[sampler + i].offset = set_offset + i;
1261 }
1262 sampler += array_size;
1263 }
1264
1265 set_offset += array_size;
1266 }
1267 }
1268 }
1269
1270 /* Finally, we're done setting it up, copy into the allocated version */
1271 *layout = l;
1272
1273 *pPipelineLayout = anv_pipeline_layout_to_handle(layout);
1274
1275 return VK_SUCCESS;
1276 }
1277
1278 void anv_DestroyPipelineLayout(
1279 VkDevice _device,
1280 VkPipelineLayout _pipelineLayout)
1281 {
1282 ANV_FROM_HANDLE(anv_device, device, _device);
1283 ANV_FROM_HANDLE(anv_pipeline_layout, pipeline_layout, _pipelineLayout);
1284
1285 anv_device_free(device, pipeline_layout);
1286 }