2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 #include "glsl/nir/nir_spirv.h"
35 /* Needed for SWIZZLE macros */
36 #include "program/prog_instruction.h"
40 VkResult
anv_CreateShaderModule(
42 const VkShaderModuleCreateInfo
* pCreateInfo
,
43 VkShaderModule
* pShaderModule
)
45 ANV_FROM_HANDLE(anv_device
, device
, _device
);
46 struct anv_shader_module
*module
;
48 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
49 assert(pCreateInfo
->flags
== 0);
51 module
= anv_device_alloc(device
, sizeof(*module
) + pCreateInfo
->codeSize
, 8,
52 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
54 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
57 module
->size
= pCreateInfo
->codeSize
;
58 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
60 *pShaderModule
= anv_shader_module_to_handle(module
);
65 void anv_DestroyShaderModule(
67 VkShaderModule _module
)
69 ANV_FROM_HANDLE(anv_device
, device
, _device
);
70 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
72 anv_device_free(device
, module
);
75 VkResult
anv_CreateShader(
77 const VkShaderCreateInfo
* pCreateInfo
,
80 ANV_FROM_HANDLE(anv_device
, device
, _device
);
81 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->module
);
82 struct anv_shader
*shader
;
84 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_CREATE_INFO
);
85 assert(pCreateInfo
->flags
== 0);
87 const char *name
= pCreateInfo
->pName
? pCreateInfo
->pName
: "main";
88 size_t name_len
= strlen(name
);
90 shader
= anv_device_alloc(device
, sizeof(*shader
) + name_len
+ 1, 8,
91 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
93 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
95 shader
->module
= module
,
96 memcpy(shader
->entrypoint
, name
, name_len
+ 1);
98 *pShader
= anv_shader_to_handle(shader
);
103 void anv_DestroyShader(
107 ANV_FROM_HANDLE(anv_device
, device
, _device
);
108 ANV_FROM_HANDLE(anv_shader
, shader
, _shader
);
110 anv_device_free(device
, shader
);
113 #define SPIR_V_MAGIC_NUMBER 0x07230203
115 static const gl_shader_stage vk_shader_stage_to_mesa_stage
[] = {
116 [VK_SHADER_STAGE_VERTEX
] = MESA_SHADER_VERTEX
,
117 [VK_SHADER_STAGE_TESS_CONTROL
] = -1,
118 [VK_SHADER_STAGE_TESS_EVALUATION
] = -1,
119 [VK_SHADER_STAGE_GEOMETRY
] = MESA_SHADER_GEOMETRY
,
120 [VK_SHADER_STAGE_FRAGMENT
] = MESA_SHADER_FRAGMENT
,
121 [VK_SHADER_STAGE_COMPUTE
] = MESA_SHADER_COMPUTE
,
125 is_scalar_shader_stage(const struct brw_compiler
*compiler
, VkShaderStage stage
)
128 case VK_SHADER_STAGE_VERTEX
:
129 return compiler
->scalar_vs
;
130 case VK_SHADER_STAGE_GEOMETRY
:
132 case VK_SHADER_STAGE_FRAGMENT
:
133 case VK_SHADER_STAGE_COMPUTE
:
136 unreachable("Unsupported shader stage");
140 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
141 * we can't do that yet because we don't have the ability to copy nir.
144 anv_shader_compile_to_nir(struct anv_device
*device
,
145 struct anv_shader
*shader
, VkShaderStage vk_stage
)
147 if (strcmp(shader
->entrypoint
, "main") != 0) {
148 anv_finishme("Multiple shaders per module not really supported");
151 gl_shader_stage stage
= vk_shader_stage_to_mesa_stage
[vk_stage
];
152 const struct brw_compiler
*compiler
=
153 device
->instance
->physicalDevice
.compiler
;
154 const nir_shader_compiler_options
*nir_options
=
155 compiler
->glsl_compiler_options
[stage
].NirOptions
;
158 if (shader
->module
->nir
) {
159 /* Some things such as our meta clear/blit code will give us a NIR
160 * shader directly. In that case, we just ignore the SPIR-V entirely
161 * and just use the NIR shader */
162 nir
= shader
->module
->nir
;
163 nir
->options
= nir_options
;
165 uint32_t *spirv
= (uint32_t *) shader
->module
->data
;
166 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
167 assert(shader
->module
->size
% 4 == 0);
169 nir
= spirv_to_nir(spirv
, shader
->module
->size
/ 4, stage
, nir_options
);
171 nir_validate_shader(nir
);
173 /* Make sure the provided shader has exactly one entrypoint and that the
174 * name matches the name that came in from the VkShader.
176 nir_function_impl
*entrypoint
= NULL
;
177 nir_foreach_overload(nir
, overload
) {
178 if (strcmp(shader
->entrypoint
, overload
->function
->name
) == 0 &&
180 assert(entrypoint
== NULL
);
181 entrypoint
= overload
->impl
;
184 assert(entrypoint
!= NULL
);
186 brw_preprocess_nir(nir
, &device
->info
,
187 is_scalar_shader_stage(compiler
, vk_stage
));
189 nir_shader_gather_info(nir
, entrypoint
);
194 VkResult
anv_CreatePipelineCache(
196 const VkPipelineCacheCreateInfo
* pCreateInfo
,
197 VkPipelineCache
* pPipelineCache
)
199 pPipelineCache
->handle
= 1;
201 stub_return(VK_SUCCESS
);
204 void anv_DestroyPipelineCache(
206 VkPipelineCache _cache
)
210 size_t anv_GetPipelineCacheSize(
212 VkPipelineCache pipelineCache
)
217 VkResult
anv_GetPipelineCacheData(
219 VkPipelineCache pipelineCache
,
222 stub_return(VK_UNSUPPORTED
);
225 VkResult
anv_MergePipelineCaches(
227 VkPipelineCache destCache
,
228 uint32_t srcCacheCount
,
229 const VkPipelineCache
* pSrcCaches
)
231 stub_return(VK_UNSUPPORTED
);
234 void anv_DestroyPipeline(
236 VkPipeline _pipeline
)
238 ANV_FROM_HANDLE(anv_device
, device
, _device
);
239 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
241 anv_reloc_list_finish(&pipeline
->batch_relocs
, pipeline
->device
);
242 anv_state_stream_finish(&pipeline
->program_stream
);
243 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
244 anv_device_free(pipeline
->device
, pipeline
);
247 static const uint32_t vk_to_gen_primitive_type
[] = {
248 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
249 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
250 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
251 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
252 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
253 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
254 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ
] = _3DPRIM_LINELIST_ADJ
,
255 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ
] = _3DPRIM_LINESTRIP_ADJ
,
256 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ
] = _3DPRIM_TRILIST_ADJ
,
257 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ
] = _3DPRIM_TRISTRIP_ADJ
,
258 [VK_PRIMITIVE_TOPOLOGY_PATCH
] = _3DPRIM_PATCHLIST_1
262 populate_sampler_prog_key(const struct brw_device_info
*devinfo
,
263 struct brw_sampler_prog_key_data
*key
)
265 /* XXX: Handle texture swizzle on HSW- */
266 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
267 /* Assume color sampler, no swizzling. (Works for BDW+) */
268 key
->swizzles
[i
] = SWIZZLE_XYZW
;
273 populate_vs_prog_key(const struct brw_device_info
*devinfo
,
274 struct brw_vs_prog_key
*key
)
276 memset(key
, 0, sizeof(*key
));
278 populate_sampler_prog_key(devinfo
, &key
->tex
);
280 /* XXX: Handle vertex input work-arounds */
282 /* XXX: Handle sampler_prog_key */
286 populate_wm_prog_key(const struct brw_device_info
*devinfo
,
287 const VkGraphicsPipelineCreateInfo
*info
,
288 struct brw_wm_prog_key
*key
)
290 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, info
->renderPass
);
292 memset(key
, 0, sizeof(*key
));
294 populate_sampler_prog_key(devinfo
, &key
->tex
);
296 /* Vulkan doesn't specify a default */
297 key
->high_quality_derivatives
= false;
299 /* XXX Vulkan doesn't appear to specify */
300 key
->clamp_fragment_color
= false;
302 /* Vulkan always specifies upper-left coordinates */
303 key
->drawable_height
= 0;
304 key
->render_to_fbo
= false;
306 key
->nr_color_regions
= render_pass
->subpasses
[info
->subpass
].color_count
;
308 key
->replicate_alpha
= key
->nr_color_regions
> 1 &&
309 info
->pColorBlendState
->alphaToCoverageEnable
;
311 if (info
->pMultisampleState
&& info
->pMultisampleState
->rasterSamples
> 1) {
312 /* We should probably pull this out of the shader, but it's fairly
313 * harmless to compute it and then let dead-code take care of it.
315 key
->persample_shading
= info
->pMultisampleState
->sampleShadingEnable
;
316 if (key
->persample_shading
)
317 key
->persample_2x
= info
->pMultisampleState
->rasterSamples
== 2;
319 key
->compute_pos_offset
= info
->pMultisampleState
->sampleShadingEnable
;
320 key
->compute_sample_id
= info
->pMultisampleState
->sampleShadingEnable
;
325 populate_cs_prog_key(const struct brw_device_info
*devinfo
,
326 struct brw_cs_prog_key
*key
)
328 memset(key
, 0, sizeof(*key
));
330 populate_sampler_prog_key(devinfo
, &key
->tex
);
334 anv_pipeline_compile(struct anv_pipeline
*pipeline
,
335 struct anv_shader
*shader
,
337 struct brw_stage_prog_data
*prog_data
)
339 const struct brw_compiler
*compiler
=
340 pipeline
->device
->instance
->physicalDevice
.compiler
;
342 nir_shader
*nir
= anv_shader_compile_to_nir(pipeline
->device
, shader
, stage
);
346 bool have_push_constants
= false;
347 nir_foreach_variable(var
, &nir
->uniforms
) {
348 if (!glsl_type_is_sampler(var
->type
)) {
349 have_push_constants
= true;
354 /* Figure out the number of parameters */
355 prog_data
->nr_params
= 0;
357 if (have_push_constants
) {
358 /* If the shader uses any push constants at all, we'll just give
359 * them the maximum possible number
361 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
364 if (pipeline
->layout
&& pipeline
->layout
->stage
[stage
].has_dynamic_offsets
)
365 prog_data
->nr_params
+= MAX_DYNAMIC_BUFFERS
;
367 if (prog_data
->nr_params
> 0) {
368 prog_data
->param
= (const gl_constant_value
**)
369 anv_device_alloc(pipeline
->device
,
370 prog_data
->nr_params
* sizeof(gl_constant_value
*),
371 8, VK_SYSTEM_ALLOC_TYPE_INTERNAL_SHADER
);
373 /* We now set the param values to be offsets into a
374 * anv_push_constant_data structure. Since the compiler doesn't
375 * actually dereference any of the gl_constant_value pointers in the
376 * params array, it doesn't really matter what we put here.
378 struct anv_push_constants
*null_data
= NULL
;
379 if (have_push_constants
) {
380 /* Fill out the push constants section of the param array */
381 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++)
382 prog_data
->param
[i
] = (const gl_constant_value
*)
383 &null_data
->client_data
[i
* sizeof(float)];
387 /* Set up dynamic offsets */
388 anv_nir_apply_dynamic_offsets(pipeline
, nir
, prog_data
);
390 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
391 anv_nir_apply_pipeline_layout(nir
, pipeline
->layout
);
393 /* All binding table offsets provided by apply_pipeline_layout() are
394 * relative to the start of the bindint table (plus MAX_RTS for VS).
396 unsigned bias
= stage
== VK_SHADER_STAGE_FRAGMENT
? MAX_RTS
: 0;
397 prog_data
->binding_table
.size_bytes
= 0;
398 prog_data
->binding_table
.texture_start
= bias
;
399 prog_data
->binding_table
.ubo_start
= bias
;
400 prog_data
->binding_table
.image_start
= bias
;
402 /* Finish the optimization and compilation process */
403 brw_postprocess_nir(nir
, &pipeline
->device
->info
,
404 is_scalar_shader_stage(compiler
, stage
));
406 /* nir_lower_io will only handle the push constants; we need to set this
407 * to the full number of possible uniforms.
409 nir
->num_uniforms
= prog_data
->nr_params
;
415 anv_pipeline_upload_kernel(struct anv_pipeline
*pipeline
,
416 const void *data
, size_t size
)
418 struct anv_state state
=
419 anv_state_stream_alloc(&pipeline
->program_stream
, size
, 64);
421 assert(size
< pipeline
->program_stream
.block_pool
->block_size
);
423 memcpy(state
.map
, data
, size
);
428 anv_pipeline_add_compiled_stage(struct anv_pipeline
*pipeline
,
430 struct brw_stage_prog_data
*prog_data
)
432 struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
433 uint32_t max_threads
[] = {
434 [VK_SHADER_STAGE_VERTEX
] = devinfo
->max_vs_threads
,
435 [VK_SHADER_STAGE_TESS_CONTROL
] = 0,
436 [VK_SHADER_STAGE_TESS_EVALUATION
] = 0,
437 [VK_SHADER_STAGE_GEOMETRY
] = devinfo
->max_gs_threads
,
438 [VK_SHADER_STAGE_FRAGMENT
] = devinfo
->max_wm_threads
,
439 [VK_SHADER_STAGE_COMPUTE
] = devinfo
->max_cs_threads
,
442 pipeline
->prog_data
[stage
] = prog_data
;
443 pipeline
->active_stages
|= 1 << stage
;
444 pipeline
->scratch_start
[stage
] = pipeline
->total_scratch
;
445 pipeline
->total_scratch
=
446 align_u32(pipeline
->total_scratch
, 1024) +
447 prog_data
->total_scratch
* max_threads
[stage
];
451 anv_pipeline_compile_vs(struct anv_pipeline
*pipeline
,
452 const VkGraphicsPipelineCreateInfo
*info
,
453 struct anv_shader
*shader
)
455 const struct brw_compiler
*compiler
=
456 pipeline
->device
->instance
->physicalDevice
.compiler
;
457 struct brw_vs_prog_data
*prog_data
= &pipeline
->vs_prog_data
;
458 struct brw_vs_prog_key key
;
460 populate_vs_prog_key(&pipeline
->device
->info
, &key
);
462 /* TODO: Look up shader in cache */
464 memset(prog_data
, 0, sizeof(*prog_data
));
466 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
467 VK_SHADER_STAGE_VERTEX
,
468 &prog_data
->base
.base
);
470 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
472 void *mem_ctx
= ralloc_context(NULL
);
474 if (shader
->module
->nir
== NULL
)
475 ralloc_steal(mem_ctx
, nir
);
477 prog_data
->inputs_read
= nir
->info
.inputs_read
;
478 pipeline
->writes_point_size
= nir
->info
.outputs_written
& VARYING_SLOT_PSIZ
;
480 brw_compute_vue_map(&pipeline
->device
->info
,
481 &prog_data
->base
.vue_map
,
482 nir
->info
.outputs_written
,
483 false /* XXX: Do SSO? */);
486 const unsigned *shader_code
=
487 brw_compile_vs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
488 NULL
, false, -1, &code_size
, NULL
);
489 if (shader_code
== NULL
) {
490 ralloc_free(mem_ctx
);
491 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
494 const uint32_t offset
=
495 anv_pipeline_upload_kernel(pipeline
, shader_code
, code_size
);
496 if (prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
) {
497 pipeline
->vs_simd8
= offset
;
498 pipeline
->vs_vec4
= NO_KERNEL
;
500 pipeline
->vs_simd8
= NO_KERNEL
;
501 pipeline
->vs_vec4
= offset
;
504 ralloc_free(mem_ctx
);
506 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_VERTEX
,
507 &prog_data
->base
.base
);
513 anv_pipeline_compile_fs(struct anv_pipeline
*pipeline
,
514 const VkGraphicsPipelineCreateInfo
*info
,
515 struct anv_shader
*shader
)
517 const struct brw_compiler
*compiler
=
518 pipeline
->device
->instance
->physicalDevice
.compiler
;
519 struct brw_wm_prog_data
*prog_data
= &pipeline
->wm_prog_data
;
520 struct brw_wm_prog_key key
;
522 populate_wm_prog_key(&pipeline
->device
->info
, info
, &key
);
524 if (pipeline
->use_repclear
)
525 key
.nr_color_regions
= 1;
527 /* TODO: Look up shader in cache */
529 memset(prog_data
, 0, sizeof(*prog_data
));
531 prog_data
->binding_table
.render_target_start
= 0;
533 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
534 VK_SHADER_STAGE_FRAGMENT
,
537 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
539 void *mem_ctx
= ralloc_context(NULL
);
541 if (shader
->module
->nir
== NULL
)
542 ralloc_steal(mem_ctx
, nir
);
545 const unsigned *shader_code
=
546 brw_compile_fs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
547 NULL
, -1, -1, pipeline
->use_repclear
, &code_size
, NULL
);
548 if (shader_code
== NULL
) {
549 ralloc_free(mem_ctx
);
550 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
553 uint32_t offset
= anv_pipeline_upload_kernel(pipeline
,
554 shader_code
, code_size
);
556 pipeline
->ps_simd8
= NO_KERNEL
;
558 pipeline
->ps_simd8
= offset
;
560 if (prog_data
->no_8
|| prog_data
->prog_offset_16
) {
561 pipeline
->ps_simd16
= offset
+ prog_data
->prog_offset_16
;
563 pipeline
->ps_simd16
= NO_KERNEL
;
566 pipeline
->ps_ksp2
= 0;
567 pipeline
->ps_grf_start2
= 0;
568 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
569 pipeline
->ps_ksp0
= pipeline
->ps_simd8
;
570 pipeline
->ps_grf_start0
= prog_data
->base
.dispatch_grf_start_reg
;
571 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
572 pipeline
->ps_ksp2
= pipeline
->ps_simd16
;
573 pipeline
->ps_grf_start2
= prog_data
->dispatch_grf_start_reg_16
;
575 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
576 pipeline
->ps_ksp0
= pipeline
->ps_simd16
;
577 pipeline
->ps_grf_start0
= prog_data
->dispatch_grf_start_reg_16
;
580 ralloc_free(mem_ctx
);
582 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_FRAGMENT
,
589 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
590 const VkComputePipelineCreateInfo
*info
,
591 struct anv_shader
*shader
)
593 const struct brw_compiler
*compiler
=
594 pipeline
->device
->instance
->physicalDevice
.compiler
;
595 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
596 struct brw_cs_prog_key key
;
598 populate_cs_prog_key(&pipeline
->device
->info
, &key
);
600 /* TODO: Look up shader in cache */
602 memset(prog_data
, 0, sizeof(*prog_data
));
604 nir_shader
*nir
= anv_pipeline_compile(pipeline
, shader
,
605 VK_SHADER_STAGE_COMPUTE
,
608 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
610 void *mem_ctx
= ralloc_context(NULL
);
612 if (shader
->module
->nir
== NULL
)
613 ralloc_steal(mem_ctx
, nir
);
616 const unsigned *shader_code
=
617 brw_compile_cs(compiler
, NULL
, mem_ctx
, &key
, prog_data
, nir
,
618 -1, &code_size
, NULL
);
619 if (shader_code
== NULL
) {
620 ralloc_free(mem_ctx
);
621 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
624 pipeline
->cs_simd
= anv_pipeline_upload_kernel(pipeline
,
625 shader_code
, code_size
);
626 ralloc_free(mem_ctx
);
628 anv_pipeline_add_compiled_stage(pipeline
, VK_SHADER_STAGE_COMPUTE
,
634 static const int gen8_push_size
= 32 * 1024;
637 gen7_compute_urb_partition(struct anv_pipeline
*pipeline
)
639 const struct brw_device_info
*devinfo
= &pipeline
->device
->info
;
640 bool vs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
;
641 unsigned vs_size
= vs_present
? pipeline
->vs_prog_data
.base
.urb_entry_size
: 1;
642 unsigned vs_entry_size_bytes
= vs_size
* 64;
643 bool gs_present
= pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
;
644 unsigned gs_size
= gs_present
? pipeline
->gs_prog_data
.base
.urb_entry_size
: 1;
645 unsigned gs_entry_size_bytes
= gs_size
* 64;
647 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
649 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
650 * Allocation Size is less than 9 512-bit URB entries.
652 * Similar text exists for GS.
654 unsigned vs_granularity
= (vs_size
< 9) ? 8 : 1;
655 unsigned gs_granularity
= (gs_size
< 9) ? 8 : 1;
657 /* URB allocations must be done in 8k chunks. */
658 unsigned chunk_size_bytes
= 8192;
660 /* Determine the size of the URB in chunks. */
661 unsigned urb_chunks
= devinfo
->urb
.size
* 1024 / chunk_size_bytes
;
663 /* Reserve space for push constants */
664 unsigned push_constant_bytes
= gen8_push_size
;
665 unsigned push_constant_chunks
=
666 push_constant_bytes
/ chunk_size_bytes
;
668 /* Initially, assign each stage the minimum amount of URB space it needs,
669 * and make a note of how much additional space it "wants" (the amount of
670 * additional space it could actually make use of).
673 /* VS has a lower limit on the number of URB entries */
675 ALIGN(devinfo
->urb
.min_vs_entries
* vs_entry_size_bytes
,
676 chunk_size_bytes
) / chunk_size_bytes
;
678 ALIGN(devinfo
->urb
.max_vs_entries
* vs_entry_size_bytes
,
679 chunk_size_bytes
) / chunk_size_bytes
- vs_chunks
;
681 unsigned gs_chunks
= 0;
682 unsigned gs_wants
= 0;
684 /* There are two constraints on the minimum amount of URB space we can
687 * (1) We need room for at least 2 URB entries, since we always operate
688 * the GS in DUAL_OBJECT mode.
690 * (2) We can't allocate less than nr_gs_entries_granularity.
692 gs_chunks
= ALIGN(MAX2(gs_granularity
, 2) * gs_entry_size_bytes
,
693 chunk_size_bytes
) / chunk_size_bytes
;
695 ALIGN(devinfo
->urb
.max_gs_entries
* gs_entry_size_bytes
,
696 chunk_size_bytes
) / chunk_size_bytes
- gs_chunks
;
699 /* There should always be enough URB space to satisfy the minimum
700 * requirements of each stage.
702 unsigned total_needs
= push_constant_chunks
+ vs_chunks
+ gs_chunks
;
703 assert(total_needs
<= urb_chunks
);
705 /* Mete out remaining space (if any) in proportion to "wants". */
706 unsigned total_wants
= vs_wants
+ gs_wants
;
707 unsigned remaining_space
= urb_chunks
- total_needs
;
708 if (remaining_space
> total_wants
)
709 remaining_space
= total_wants
;
710 if (remaining_space
> 0) {
711 unsigned vs_additional
= (unsigned)
712 round(vs_wants
* (((double) remaining_space
) / total_wants
));
713 vs_chunks
+= vs_additional
;
714 remaining_space
-= vs_additional
;
715 gs_chunks
+= remaining_space
;
718 /* Sanity check that we haven't over-allocated. */
719 assert(push_constant_chunks
+ vs_chunks
+ gs_chunks
<= urb_chunks
);
721 /* Finally, compute the number of entries that can fit in the space
722 * allocated to each stage.
724 unsigned nr_vs_entries
= vs_chunks
* chunk_size_bytes
/ vs_entry_size_bytes
;
725 unsigned nr_gs_entries
= gs_chunks
* chunk_size_bytes
/ gs_entry_size_bytes
;
727 /* Since we rounded up when computing *_wants, this may be slightly more
728 * than the maximum allowed amount, so correct for that.
730 nr_vs_entries
= MIN2(nr_vs_entries
, devinfo
->urb
.max_vs_entries
);
731 nr_gs_entries
= MIN2(nr_gs_entries
, devinfo
->urb
.max_gs_entries
);
733 /* Ensure that we program a multiple of the granularity. */
734 nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, vs_granularity
);
735 nr_gs_entries
= ROUND_DOWN_TO(nr_gs_entries
, gs_granularity
);
737 /* Finally, sanity check to make sure we have at least the minimum number
738 * of entries needed for each stage.
740 assert(nr_vs_entries
>= devinfo
->urb
.min_vs_entries
);
742 assert(nr_gs_entries
>= 2);
744 /* Lay out the URB in the following order:
749 pipeline
->urb
.vs_start
= push_constant_chunks
;
750 pipeline
->urb
.vs_size
= vs_size
;
751 pipeline
->urb
.nr_vs_entries
= nr_vs_entries
;
753 pipeline
->urb
.gs_start
= push_constant_chunks
+ vs_chunks
;
754 pipeline
->urb
.gs_size
= gs_size
;
755 pipeline
->urb
.nr_gs_entries
= nr_gs_entries
;
759 anv_pipeline_init_dynamic_state(struct anv_pipeline
*pipeline
,
760 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
762 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
763 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
764 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
766 pipeline
->dynamic_state
= default_dynamic_state
;
768 if (pCreateInfo
->pDynamicState
) {
769 /* Remove all of the states that are marked as dynamic */
770 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
771 for (uint32_t s
= 0; s
< count
; s
++)
772 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
775 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
777 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
778 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
779 typed_memcpy(dynamic
->viewport
.viewports
,
780 pCreateInfo
->pViewportState
->pViewports
,
781 pCreateInfo
->pViewportState
->viewportCount
);
784 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
785 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
786 typed_memcpy(dynamic
->scissor
.scissors
,
787 pCreateInfo
->pViewportState
->pScissors
,
788 pCreateInfo
->pViewportState
->scissorCount
);
791 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
792 assert(pCreateInfo
->pRasterState
);
793 dynamic
->line_width
= pCreateInfo
->pRasterState
->lineWidth
;
796 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
797 assert(pCreateInfo
->pRasterState
);
798 dynamic
->depth_bias
.bias
= pCreateInfo
->pRasterState
->depthBias
;
799 dynamic
->depth_bias
.clamp
= pCreateInfo
->pRasterState
->depthBiasClamp
;
800 dynamic
->depth_bias
.slope_scaled
=
801 pCreateInfo
->pRasterState
->slopeScaledDepthBias
;
804 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
)) {
805 assert(pCreateInfo
->pColorBlendState
);
806 typed_memcpy(dynamic
->blend_constants
,
807 pCreateInfo
->pColorBlendState
->blendConst
, 4);
810 /* If there is no depthstencil attachment, then don't read
811 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
812 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
813 * no need to override the depthstencil defaults in
814 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
816 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
818 * pDepthStencilState [...] may only be NULL if renderPass and subpass
819 * specify a subpass that has no depth/stencil attachment.
821 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
822 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
823 assert(pCreateInfo
->pDepthStencilState
);
824 dynamic
->depth_bounds
.min
=
825 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
826 dynamic
->depth_bounds
.max
=
827 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
830 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
831 assert(pCreateInfo
->pDepthStencilState
);
832 dynamic
->stencil_compare_mask
.front
=
833 pCreateInfo
->pDepthStencilState
->front
.stencilCompareMask
;
834 dynamic
->stencil_compare_mask
.back
=
835 pCreateInfo
->pDepthStencilState
->back
.stencilCompareMask
;
838 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
839 assert(pCreateInfo
->pDepthStencilState
);
840 dynamic
->stencil_write_mask
.front
=
841 pCreateInfo
->pDepthStencilState
->front
.stencilWriteMask
;
842 dynamic
->stencil_write_mask
.back
=
843 pCreateInfo
->pDepthStencilState
->back
.stencilWriteMask
;
846 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
847 assert(pCreateInfo
->pDepthStencilState
);
848 dynamic
->stencil_reference
.front
=
849 pCreateInfo
->pDepthStencilState
->front
.stencilReference
;
850 dynamic
->stencil_reference
.back
=
851 pCreateInfo
->pDepthStencilState
->back
.stencilReference
;
855 pipeline
->dynamic_state_mask
= states
;
859 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
861 struct anv_render_pass
*renderpass
= NULL
;
862 struct anv_subpass
*subpass
= NULL
;
864 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
865 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
866 * 4.2 Graphics Pipeline.
868 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
870 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
873 if (renderpass
!= &anv_meta_dummy_renderpass
) {
874 assert(info
->subpass
< renderpass
->subpass_count
);
875 subpass
= &renderpass
->subpasses
[info
->subpass
];
878 assert(info
->stageCount
>= 1);
879 assert(info
->pVertexInputState
);
880 assert(info
->pInputAssemblyState
);
881 assert(info
->pViewportState
);
882 assert(info
->pRasterState
);
883 assert(info
->pMultisampleState
);
885 if (subpass
&& subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
)
886 assert(info
->pDepthStencilState
);
888 if (subpass
&& subpass
->color_count
> 0)
889 assert(info
->pColorBlendState
);
891 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
892 switch (info
->pStages
[i
].stage
) {
893 case VK_SHADER_STAGE_TESS_CONTROL
:
894 case VK_SHADER_STAGE_TESS_EVALUATION
:
895 assert(info
->pTessellationState
);
904 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
905 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
906 const struct anv_graphics_pipeline_create_info
*extra
)
911 anv_pipeline_validate_create_info(pCreateInfo
);
914 pipeline
->device
= device
;
915 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
917 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
918 if (result
!= VK_SUCCESS
) {
919 anv_device_free(device
, pipeline
);
922 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
923 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
924 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
926 anv_state_stream_init(&pipeline
->program_stream
,
927 &device
->instruction_block_pool
);
929 anv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
931 if (pCreateInfo
->pTessellationState
)
932 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
933 if (pCreateInfo
->pMultisampleState
&&
934 pCreateInfo
->pMultisampleState
->rasterSamples
> 1)
935 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
937 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
938 pipeline
->writes_point_size
= false;
940 /* When we free the pipeline, we detect stages based on the NULL status
941 * of various prog_data pointers. Make them NULL by default.
943 memset(pipeline
->prog_data
, 0, sizeof(pipeline
->prog_data
));
944 memset(pipeline
->scratch_start
, 0, sizeof(pipeline
->scratch_start
));
946 pipeline
->vs_simd8
= NO_KERNEL
;
947 pipeline
->vs_vec4
= NO_KERNEL
;
948 pipeline
->gs_vec4
= NO_KERNEL
;
950 pipeline
->active_stages
= 0;
951 pipeline
->total_scratch
= 0;
953 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
954 ANV_FROM_HANDLE(anv_shader
, shader
, pCreateInfo
->pStages
[i
].shader
);
956 switch (pCreateInfo
->pStages
[i
].stage
) {
957 case VK_SHADER_STAGE_VERTEX
:
958 anv_pipeline_compile_vs(pipeline
, pCreateInfo
, shader
);
960 case VK_SHADER_STAGE_FRAGMENT
:
961 anv_pipeline_compile_fs(pipeline
, pCreateInfo
, shader
);
964 anv_finishme("Unsupported shader stage");
968 if (!(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
)) {
969 /* Vertex is only optional if disable_vs is set */
970 assert(extra
->disable_vs
);
971 memset(&pipeline
->vs_prog_data
, 0, sizeof(pipeline
->vs_prog_data
));
974 gen7_compute_urb_partition(pipeline
);
976 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
977 pCreateInfo
->pVertexInputState
;
978 pipeline
->vb_used
= 0;
979 for (uint32_t i
= 0; i
< vi_info
->bindingCount
; i
++) {
980 const VkVertexInputBindingDescription
*desc
=
981 &vi_info
->pVertexBindingDescriptions
[i
];
983 pipeline
->vb_used
|= 1 << desc
->binding
;
984 pipeline
->binding_stride
[desc
->binding
] = desc
->strideInBytes
;
986 /* Step rate is programmed per vertex element (attribute), not
987 * binding. Set up a map of which bindings step per instance, for
988 * reference by vertex element setup. */
989 switch (desc
->stepRate
) {
991 case VK_VERTEX_INPUT_STEP_RATE_VERTEX
:
992 pipeline
->instancing_enable
[desc
->binding
] = false;
994 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE
:
995 pipeline
->instancing_enable
[desc
->binding
] = true;
1000 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1001 pCreateInfo
->pInputAssemblyState
;
1002 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1003 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1005 if (extra
&& extra
->use_rectlist
)
1006 pipeline
->topology
= _3DPRIM_RECTLIST
;
1012 anv_graphics_pipeline_create(
1014 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1015 const struct anv_graphics_pipeline_create_info
*extra
,
1016 VkPipeline
*pPipeline
)
1018 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1020 switch (device
->info
.gen
) {
1022 return gen7_graphics_pipeline_create(_device
, pCreateInfo
, extra
, pPipeline
);
1024 return gen8_graphics_pipeline_create(_device
, pCreateInfo
, extra
, pPipeline
);
1026 unreachable("unsupported gen\n");
1030 VkResult
anv_CreateGraphicsPipelines(
1032 VkPipelineCache pipelineCache
,
1034 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1035 VkPipeline
* pPipelines
)
1037 VkResult result
= VK_SUCCESS
;
1040 for (; i
< count
; i
++) {
1041 result
= anv_graphics_pipeline_create(_device
, &pCreateInfos
[i
],
1042 NULL
, &pPipelines
[i
]);
1043 if (result
!= VK_SUCCESS
) {
1044 for (unsigned j
= 0; j
< i
; j
++) {
1045 anv_DestroyPipeline(_device
, pPipelines
[j
]);
1055 static VkResult
anv_compute_pipeline_create(
1057 const VkComputePipelineCreateInfo
* pCreateInfo
,
1058 VkPipeline
* pPipeline
)
1060 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1062 switch (device
->info
.gen
) {
1064 return gen7_compute_pipeline_create(_device
, pCreateInfo
, pPipeline
);
1066 return gen8_compute_pipeline_create(_device
, pCreateInfo
, pPipeline
);
1068 unreachable("unsupported gen\n");
1072 VkResult
anv_CreateComputePipelines(
1074 VkPipelineCache pipelineCache
,
1076 const VkComputePipelineCreateInfo
* pCreateInfos
,
1077 VkPipeline
* pPipelines
)
1079 VkResult result
= VK_SUCCESS
;
1082 for (; i
< count
; i
++) {
1083 result
= anv_compute_pipeline_create(_device
, &pCreateInfos
[i
],
1085 if (result
!= VK_SUCCESS
) {
1086 for (unsigned j
= 0; j
< i
; j
++) {
1087 anv_DestroyPipeline(_device
, pPipelines
[j
]);
1097 // Pipeline layout functions
1099 VkResult
anv_CreatePipelineLayout(
1101 const VkPipelineLayoutCreateInfo
* pCreateInfo
,
1102 VkPipelineLayout
* pPipelineLayout
)
1104 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1105 struct anv_pipeline_layout l
, *layout
;
1107 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
);
1109 l
.num_sets
= pCreateInfo
->descriptorSetCount
;
1111 unsigned dynamic_offset_count
= 0;
1113 memset(l
.stage
, 0, sizeof(l
.stage
));
1114 for (uint32_t set
= 0; set
< pCreateInfo
->descriptorSetCount
; set
++) {
1115 ANV_FROM_HANDLE(anv_descriptor_set_layout
, set_layout
,
1116 pCreateInfo
->pSetLayouts
[set
]);
1117 l
.set
[set
].layout
= set_layout
;
1119 l
.set
[set
].dynamic_offset_start
= dynamic_offset_count
;
1120 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1121 if (set_layout
->binding
[b
].dynamic_offset_index
>= 0)
1122 dynamic_offset_count
+= set_layout
->binding
[b
].array_size
;
1125 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
1126 l
.set
[set
].stage
[s
].surface_start
= l
.stage
[s
].surface_count
;
1127 l
.set
[set
].stage
[s
].sampler_start
= l
.stage
[s
].sampler_count
;
1129 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1130 unsigned array_size
= set_layout
->binding
[b
].array_size
;
1132 if (set_layout
->binding
[b
].stage
[s
].surface_index
>= 0) {
1133 l
.stage
[s
].surface_count
+= array_size
;
1135 if (set_layout
->binding
[b
].dynamic_offset_index
>= 0)
1136 l
.stage
[s
].has_dynamic_offsets
= true;
1139 if (set_layout
->binding
[b
].stage
[s
].sampler_index
>= 0)
1140 l
.stage
[s
].sampler_count
+= array_size
;
1145 unsigned num_bindings
= 0;
1146 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++)
1147 num_bindings
+= l
.stage
[s
].surface_count
+ l
.stage
[s
].sampler_count
;
1149 size_t size
= sizeof(*layout
) + num_bindings
* sizeof(layout
->entries
[0]);
1151 layout
= anv_device_alloc(device
, size
, 8, VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
1153 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1155 /* Now we can actually build our surface and sampler maps */
1156 struct anv_pipeline_binding
*entry
= layout
->entries
;
1157 for (VkShaderStage s
= 0; s
< VK_SHADER_STAGE_NUM
; s
++) {
1158 l
.stage
[s
].surface_to_descriptor
= entry
;
1159 entry
+= l
.stage
[s
].surface_count
;
1160 l
.stage
[s
].sampler_to_descriptor
= entry
;
1161 entry
+= l
.stage
[s
].sampler_count
;
1165 for (uint32_t set
= 0; set
< pCreateInfo
->descriptorSetCount
; set
++) {
1166 struct anv_descriptor_set_layout
*set_layout
= l
.set
[set
].layout
;
1168 unsigned set_offset
= 0;
1169 for (uint32_t b
= 0; b
< set_layout
->binding_count
; b
++) {
1170 unsigned array_size
= set_layout
->binding
[b
].array_size
;
1172 if (set_layout
->binding
[b
].stage
[s
].surface_index
>= 0) {
1173 assert(surface
== l
.set
[set
].stage
[s
].surface_start
+
1174 set_layout
->binding
[b
].stage
[s
].surface_index
);
1175 for (unsigned i
= 0; i
< array_size
; i
++) {
1176 l
.stage
[s
].surface_to_descriptor
[surface
+ i
].set
= set
;
1177 l
.stage
[s
].surface_to_descriptor
[surface
+ i
].offset
= set_offset
+ i
;
1179 surface
+= array_size
;
1182 if (set_layout
->binding
[b
].stage
[s
].sampler_index
>= 0) {
1183 assert(sampler
== l
.set
[set
].stage
[s
].sampler_start
+
1184 set_layout
->binding
[b
].stage
[s
].sampler_index
);
1185 for (unsigned i
= 0; i
< array_size
; i
++) {
1186 l
.stage
[s
].sampler_to_descriptor
[sampler
+ i
].set
= set
;
1187 l
.stage
[s
].sampler_to_descriptor
[sampler
+ i
].offset
= set_offset
+ i
;
1189 sampler
+= array_size
;
1192 set_offset
+= array_size
;
1197 /* Finally, we're done setting it up, copy into the allocated version */
1200 *pPipelineLayout
= anv_pipeline_layout_to_handle(layout
);
1205 void anv_DestroyPipelineLayout(
1207 VkPipelineLayout _pipelineLayout
)
1209 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1210 ANV_FROM_HANDLE(anv_pipeline_layout
, pipeline_layout
, _pipelineLayout
);
1212 anv_device_free(device
, pipeline_layout
);