anv: clflush is only orderered against mfence
[mesa.git] / src / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdlib.h>
27 #include <stdio.h>
28 #include <stdbool.h>
29 #include <pthread.h>
30 #include <assert.h>
31 #include <stdint.h>
32 #include <i915_drm.h>
33
34 #ifdef HAVE_VALGRIND
35 #include <valgrind.h>
36 #include <memcheck.h>
37 #define VG(x) x
38 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
39 #else
40 #define VG(x)
41 #endif
42
43 #include "brw_device_info.h"
44 #include "util/macros.h"
45 #include "util/list.h"
46
47 /* Pre-declarations needed for WSI entrypoints */
48 struct wl_surface;
49 struct wl_display;
50 typedef struct xcb_connection_t xcb_connection_t;
51 typedef uint32_t xcb_visualid_t;
52 typedef uint32_t xcb_window_t;
53
54 #define VK_USE_PLATFORM_XCB_KHR
55 #define VK_USE_PLATFORM_WAYLAND_KHR
56
57 #define VK_PROTOTYPES
58 #include <vulkan/vulkan.h>
59 #include <vulkan/vulkan_intel.h>
60
61 #include "anv_entrypoints.h"
62 #include "anv_gen_macros.h"
63 #include "brw_context.h"
64 #include "isl.h"
65
66 #ifdef __cplusplus
67 extern "C" {
68 #endif
69
70 #define MAX_VBS 32
71 #define MAX_SETS 8
72 #define MAX_RTS 8
73 #define MAX_VIEWPORTS 16
74 #define MAX_SCISSORS 16
75 #define MAX_PUSH_CONSTANTS_SIZE 128
76 #define MAX_DYNAMIC_BUFFERS 16
77 #define MAX_IMAGES 8
78 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
79
80 #define ICD_LOADER_MAGIC 0x01CDC0DE
81
82 typedef union _VK_LOADER_DATA {
83 uintptr_t loaderMagic;
84 void *loaderData;
85 } VK_LOADER_DATA;
86
87 #define anv_noreturn __attribute__((__noreturn__))
88 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
89
90 #define MIN(a, b) ((a) < (b) ? (a) : (b))
91 #define MAX(a, b) ((a) > (b) ? (a) : (b))
92
93 static inline uint32_t
94 align_u32(uint32_t v, uint32_t a)
95 {
96 assert(a != 0 && a == (a & -a));
97 return (v + a - 1) & ~(a - 1);
98 }
99
100 static inline uint64_t
101 align_u64(uint64_t v, uint64_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline int32_t
108 align_i32(int32_t v, int32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 /** Alignment must be a power of 2. */
115 static inline bool
116 anv_is_aligned(uintmax_t n, uintmax_t a)
117 {
118 assert(a == (a & -a));
119 return (n & (a - 1)) == 0;
120 }
121
122 static inline uint32_t
123 anv_minify(uint32_t n, uint32_t levels)
124 {
125 if (unlikely(n == 0))
126 return 0;
127 else
128 return MAX(n >> levels, 1);
129 }
130
131 static inline float
132 anv_clamp_f(float f, float min, float max)
133 {
134 assert(min < max);
135
136 if (f > max)
137 return max;
138 else if (f < min)
139 return min;
140 else
141 return f;
142 }
143
144 static inline bool
145 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
146 {
147 if (*inout_mask & clear_mask) {
148 *inout_mask &= ~clear_mask;
149 return true;
150 } else {
151 return false;
152 }
153 }
154
155 #define for_each_bit(b, dword) \
156 for (uint32_t __dword = (dword); \
157 (b) = __builtin_ffs(__dword) - 1, __dword; \
158 __dword &= ~(1 << (b)))
159
160 #define typed_memcpy(dest, src, count) ({ \
161 static_assert(sizeof(*src) == sizeof(*dest), ""); \
162 memcpy((dest), (src), (count) * sizeof(*(src))); \
163 })
164
165 #define zero(x) (memset(&(x), 0, sizeof(x)))
166
167 /* Define no kernel as 1, since that's an illegal offset for a kernel */
168 #define NO_KERNEL 1
169
170 struct anv_common {
171 VkStructureType sType;
172 const void* pNext;
173 };
174
175 /* Whenever we generate an error, pass it through this function. Useful for
176 * debugging, where we can break on it. Only call at error site, not when
177 * propagating errors. Might be useful to plug in a stack trace here.
178 */
179
180 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
181
182 #ifdef DEBUG
183 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
184 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
185 #else
186 #define vk_error(error) error
187 #define vk_errorf(error, format, ...) error
188 #endif
189
190 void __anv_finishme(const char *file, int line, const char *format, ...)
191 anv_printflike(3, 4);
192 void anv_loge(const char *format, ...) anv_printflike(1, 2);
193 void anv_loge_v(const char *format, va_list va);
194
195 /**
196 * Print a FINISHME message, including its source location.
197 */
198 #define anv_finishme(format, ...) \
199 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__);
200
201 /* A non-fatal assert. Useful for debugging. */
202 #ifdef DEBUG
203 #define anv_assert(x) ({ \
204 if (unlikely(!(x))) \
205 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
206 })
207 #else
208 #define anv_assert(x)
209 #endif
210
211 /**
212 * If a block of code is annotated with anv_validate, then the block runs only
213 * in debug builds.
214 */
215 #ifdef DEBUG
216 #define anv_validate if (1)
217 #else
218 #define anv_validate if (0)
219 #endif
220
221 void anv_abortf(const char *format, ...) anv_noreturn anv_printflike(1, 2);
222 void anv_abortfv(const char *format, va_list va) anv_noreturn;
223
224 #define stub_return(v) \
225 do { \
226 anv_finishme("stub %s", __func__); \
227 return (v); \
228 } while (0)
229
230 #define stub() \
231 do { \
232 anv_finishme("stub %s", __func__); \
233 return; \
234 } while (0)
235
236 /**
237 * A dynamically growable, circular buffer. Elements are added at head and
238 * removed from tail. head and tail are free-running uint32_t indices and we
239 * only compute the modulo with size when accessing the array. This way,
240 * number of bytes in the queue is always head - tail, even in case of
241 * wraparound.
242 */
243
244 struct anv_vector {
245 uint32_t head;
246 uint32_t tail;
247 uint32_t element_size;
248 uint32_t size;
249 void *data;
250 };
251
252 int anv_vector_init(struct anv_vector *queue, uint32_t element_size, uint32_t size);
253 void *anv_vector_add(struct anv_vector *queue);
254 void *anv_vector_remove(struct anv_vector *queue);
255
256 static inline int
257 anv_vector_length(struct anv_vector *queue)
258 {
259 return (queue->head - queue->tail) / queue->element_size;
260 }
261
262 static inline void *
263 anv_vector_head(struct anv_vector *vector)
264 {
265 assert(vector->tail < vector->head);
266 return (void *)((char *)vector->data +
267 ((vector->head - vector->element_size) &
268 (vector->size - 1)));
269 }
270
271 static inline void *
272 anv_vector_tail(struct anv_vector *vector)
273 {
274 return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
275 }
276
277 static inline void
278 anv_vector_finish(struct anv_vector *queue)
279 {
280 free(queue->data);
281 }
282
283 #define anv_vector_foreach(elem, queue) \
284 static_assert(__builtin_types_compatible_p(__typeof__(queue), struct anv_vector *), ""); \
285 for (uint32_t __anv_vector_offset = (queue)->tail; \
286 elem = (queue)->data + (__anv_vector_offset & ((queue)->size - 1)), __anv_vector_offset < (queue)->head; \
287 __anv_vector_offset += (queue)->element_size)
288
289 struct anv_bo {
290 uint32_t gem_handle;
291
292 /* Index into the current validation list. This is used by the
293 * validation list building alrogithm to track which buffers are already
294 * in the validation list so that we can ensure uniqueness.
295 */
296 uint32_t index;
297
298 /* Last known offset. This value is provided by the kernel when we
299 * execbuf and is used as the presumed offset for the next bunch of
300 * relocations.
301 */
302 uint64_t offset;
303
304 uint64_t size;
305 void *map;
306 };
307
308 /* Represents a lock-free linked list of "free" things. This is used by
309 * both the block pool and the state pools. Unfortunately, in order to
310 * solve the ABA problem, we can't use a single uint32_t head.
311 */
312 union anv_free_list {
313 struct {
314 int32_t offset;
315
316 /* A simple count that is incremented every time the head changes. */
317 uint32_t count;
318 };
319 uint64_t u64;
320 };
321
322 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
323
324 struct anv_block_state {
325 union {
326 struct {
327 uint32_t next;
328 uint32_t end;
329 };
330 uint64_t u64;
331 };
332 };
333
334 struct anv_block_pool {
335 struct anv_device *device;
336
337 struct anv_bo bo;
338
339 /* The offset from the start of the bo to the "center" of the block
340 * pool. Pointers to allocated blocks are given by
341 * bo.map + center_bo_offset + offsets.
342 */
343 uint32_t center_bo_offset;
344
345 /* Current memory map of the block pool. This pointer may or may not
346 * point to the actual beginning of the block pool memory. If
347 * anv_block_pool_alloc_back has ever been called, then this pointer
348 * will point to the "center" position of the buffer and all offsets
349 * (negative or positive) given out by the block pool alloc functions
350 * will be valid relative to this pointer.
351 *
352 * In particular, map == bo.map + center_offset
353 */
354 void *map;
355 int fd;
356
357 /**
358 * Array of mmaps and gem handles owned by the block pool, reclaimed when
359 * the block pool is destroyed.
360 */
361 struct anv_vector mmap_cleanups;
362
363 uint32_t block_size;
364
365 union anv_free_list free_list;
366 struct anv_block_state state;
367
368 union anv_free_list back_free_list;
369 struct anv_block_state back_state;
370 };
371
372 /* Block pools are backed by a fixed-size 2GB memfd */
373 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
374
375 /* The center of the block pool is also the middle of the memfd. This may
376 * change in the future if we decide differently for some reason.
377 */
378 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
379
380 static inline uint32_t
381 anv_block_pool_size(struct anv_block_pool *pool)
382 {
383 return pool->state.end + pool->back_state.end;
384 }
385
386 struct anv_state {
387 int32_t offset;
388 uint32_t alloc_size;
389 void *map;
390 };
391
392 struct anv_fixed_size_state_pool {
393 size_t state_size;
394 union anv_free_list free_list;
395 struct anv_block_state block;
396 };
397
398 #define ANV_MIN_STATE_SIZE_LOG2 6
399 #define ANV_MAX_STATE_SIZE_LOG2 10
400
401 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2)
402
403 struct anv_state_pool {
404 struct anv_block_pool *block_pool;
405 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
406 };
407
408 struct anv_state_stream_block;
409
410 struct anv_state_stream {
411 struct anv_block_pool *block_pool;
412
413 /* The current working block */
414 struct anv_state_stream_block *block;
415
416 /* Offset at which the current block starts */
417 uint32_t start;
418 /* Offset at which to allocate the next state */
419 uint32_t next;
420 /* Offset at which the current block ends */
421 uint32_t end;
422 };
423
424 #define CACHELINE_SIZE 64
425 #define CACHELINE_MASK 63
426
427 static void inline
428 anv_state_clflush(struct anv_state state)
429 {
430 /* state.map may not be cacheline aligned, so round down the start pointer
431 * to a cacheline boundary so we flush all pages that contain the state.
432 */
433 void *end = state.map + state.alloc_size;
434 void *p = (void *) (((uintptr_t) state.map) & ~CACHELINE_MASK);
435
436 __builtin_ia32_mfence();
437 while (p < end) {
438 __builtin_ia32_clflush(p);
439 p += CACHELINE_SIZE;
440 }
441 }
442
443 void anv_block_pool_init(struct anv_block_pool *pool,
444 struct anv_device *device, uint32_t block_size);
445 void anv_block_pool_finish(struct anv_block_pool *pool);
446 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
447 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
448 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
449 void anv_state_pool_init(struct anv_state_pool *pool,
450 struct anv_block_pool *block_pool);
451 void anv_state_pool_finish(struct anv_state_pool *pool);
452 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
453 size_t state_size, size_t alignment);
454 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
455 void anv_state_stream_init(struct anv_state_stream *stream,
456 struct anv_block_pool *block_pool);
457 void anv_state_stream_finish(struct anv_state_stream *stream);
458 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
459 uint32_t size, uint32_t alignment);
460
461 /**
462 * Implements a pool of re-usable BOs. The interface is identical to that
463 * of block_pool except that each block is its own BO.
464 */
465 struct anv_bo_pool {
466 struct anv_device *device;
467
468 uint32_t bo_size;
469
470 void *free_list;
471 };
472
473 void anv_bo_pool_init(struct anv_bo_pool *pool,
474 struct anv_device *device, uint32_t block_size);
475 void anv_bo_pool_finish(struct anv_bo_pool *pool);
476 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo);
477 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
478
479
480 void *anv_resolve_entrypoint(uint32_t index);
481
482 extern struct anv_dispatch_table dtable;
483
484 #define ANV_CALL(func) ({ \
485 if (dtable.func == NULL) { \
486 size_t idx = offsetof(struct anv_dispatch_table, func) / sizeof(void *); \
487 dtable.entrypoints[idx] = anv_resolve_entrypoint(idx); \
488 } \
489 dtable.func; \
490 })
491
492 static inline void *
493 anv_alloc(const VkAllocationCallbacks *alloc,
494 size_t size, size_t align,
495 VkSystemAllocationScope scope)
496 {
497 return alloc->pfnAllocation(alloc->pUserData, size, align, scope);
498 }
499
500 static inline void *
501 anv_realloc(const VkAllocationCallbacks *alloc,
502 void *ptr, size_t size, size_t align,
503 VkSystemAllocationScope scope)
504 {
505 return alloc->pfnReallocation(alloc->pUserData, ptr, size, align, scope);
506 }
507
508 static inline void
509 anv_free(const VkAllocationCallbacks *alloc, void *data)
510 {
511 alloc->pfnFree(alloc->pUserData, data);
512 }
513
514 static inline void *
515 anv_alloc2(const VkAllocationCallbacks *parent_alloc,
516 const VkAllocationCallbacks *alloc,
517 size_t size, size_t align,
518 VkSystemAllocationScope scope)
519 {
520 if (alloc)
521 return anv_alloc(alloc, size, align, scope);
522 else
523 return anv_alloc(parent_alloc, size, align, scope);
524 }
525
526 static inline void
527 anv_free2(const VkAllocationCallbacks *parent_alloc,
528 const VkAllocationCallbacks *alloc,
529 void *data)
530 {
531 if (alloc)
532 anv_free(alloc, data);
533 else
534 anv_free(parent_alloc, data);
535 }
536
537 struct anv_physical_device {
538 VK_LOADER_DATA _loader_data;
539
540 struct anv_instance * instance;
541 uint32_t chipset_id;
542 const char * path;
543 const char * name;
544 const struct brw_device_info * info;
545 uint64_t aperture_size;
546 struct brw_compiler * compiler;
547 struct isl_device isl_dev;
548 };
549
550 struct anv_instance {
551 VK_LOADER_DATA _loader_data;
552
553 VkAllocationCallbacks alloc;
554
555 uint32_t apiVersion;
556 int physicalDeviceCount;
557 struct anv_physical_device physicalDevice;
558
559 void * wayland_wsi;
560 };
561
562 VkResult anv_init_wsi(struct anv_instance *instance);
563 void anv_finish_wsi(struct anv_instance *instance);
564
565 struct anv_meta_state {
566 VkAllocationCallbacks alloc;
567
568 /**
569 * Use array element `i` for images with `2^i` samples.
570 */
571 struct {
572 /**
573 * Pipeline N is used to clear color attachment N of the current
574 * subpass.
575 *
576 * HACK: We use one pipeline per color attachment to work around the
577 * compiler's inability to dynamically set the render target index of
578 * the render target write message.
579 */
580 struct anv_pipeline *color_pipelines[MAX_RTS];
581
582 struct anv_pipeline *depth_only_pipeline;
583 struct anv_pipeline *stencil_only_pipeline;
584 struct anv_pipeline *depthstencil_pipeline;
585 } clear[1 + MAX_SAMPLES_LOG2];
586
587 struct {
588 VkRenderPass render_pass;
589
590 /** Pipeline that blits from a 1D image. */
591 VkPipeline pipeline_1d_src;
592
593 /** Pipeline that blits from a 2D image. */
594 VkPipeline pipeline_2d_src;
595
596 /** Pipeline that blits from a 3D image. */
597 VkPipeline pipeline_3d_src;
598
599 VkPipelineLayout pipeline_layout;
600 VkDescriptorSetLayout ds_layout;
601 } blit;
602
603 struct {
604 /** Pipeline [i] resolves an image with 2^(i+1) samples. */
605 VkPipeline pipelines[MAX_SAMPLES_LOG2];
606
607 VkRenderPass pass;
608 VkPipelineLayout pipeline_layout;
609 VkDescriptorSetLayout ds_layout;
610 } resolve;
611 };
612
613 struct anv_queue {
614 VK_LOADER_DATA _loader_data;
615
616 struct anv_device * device;
617
618 struct anv_state_pool * pool;
619 };
620
621 struct anv_pipeline_cache {
622 struct anv_device * device;
623 struct anv_state_stream program_stream;
624 pthread_mutex_t mutex;
625 };
626
627 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
628 struct anv_device *device);
629 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
630
631 struct anv_device {
632 VK_LOADER_DATA _loader_data;
633
634 VkAllocationCallbacks alloc;
635
636 struct anv_instance * instance;
637 uint32_t chipset_id;
638 struct brw_device_info info;
639 struct isl_device isl_dev;
640 int context_id;
641 int fd;
642
643 struct anv_bo_pool batch_bo_pool;
644
645 struct anv_block_pool dynamic_state_block_pool;
646 struct anv_state_pool dynamic_state_pool;
647
648 struct anv_block_pool instruction_block_pool;
649 struct anv_pipeline_cache default_pipeline_cache;
650
651 struct anv_block_pool surface_state_block_pool;
652 struct anv_state_pool surface_state_pool;
653
654 struct anv_bo workaround_bo;
655
656 struct anv_meta_state meta_state;
657
658 struct anv_state border_colors;
659
660 struct anv_queue queue;
661
662 struct anv_block_pool scratch_block_pool;
663
664 pthread_mutex_t mutex;
665 };
666
667 void* anv_gem_mmap(struct anv_device *device,
668 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
669 void anv_gem_munmap(void *p, uint64_t size);
670 uint32_t anv_gem_create(struct anv_device *device, size_t size);
671 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
672 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
673 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
674 int anv_gem_execbuffer(struct anv_device *device,
675 struct drm_i915_gem_execbuffer2 *execbuf);
676 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
677 uint32_t stride, uint32_t tiling);
678 int anv_gem_create_context(struct anv_device *device);
679 int anv_gem_destroy_context(struct anv_device *device, int context);
680 int anv_gem_get_param(int fd, uint32_t param);
681 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
682 int anv_gem_get_aperture(int fd, uint64_t *size);
683 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
684 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
685 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
686 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
687 uint32_t read_domains, uint32_t write_domain);
688
689 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
690
691 struct anv_reloc_list {
692 size_t num_relocs;
693 size_t array_length;
694 struct drm_i915_gem_relocation_entry * relocs;
695 struct anv_bo ** reloc_bos;
696 };
697
698 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
699 const VkAllocationCallbacks *alloc);
700 void anv_reloc_list_finish(struct anv_reloc_list *list,
701 const VkAllocationCallbacks *alloc);
702
703 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
704 const VkAllocationCallbacks *alloc,
705 uint32_t offset, struct anv_bo *target_bo,
706 uint32_t delta);
707
708 struct anv_batch_bo {
709 /* Link in the anv_cmd_buffer.owned_batch_bos list */
710 struct list_head link;
711
712 struct anv_bo bo;
713
714 /* Bytes actually consumed in this batch BO */
715 size_t length;
716
717 /* Last seen surface state block pool bo offset */
718 uint32_t last_ss_pool_bo_offset;
719
720 struct anv_reloc_list relocs;
721 };
722
723 struct anv_batch {
724 const VkAllocationCallbacks * alloc;
725
726 void * start;
727 void * end;
728 void * next;
729
730 struct anv_reloc_list * relocs;
731
732 /* This callback is called (with the associated user data) in the event
733 * that the batch runs out of space.
734 */
735 VkResult (*extend_cb)(struct anv_batch *, void *);
736 void * user_data;
737 };
738
739 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
740 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
741 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
742 void *location, struct anv_bo *bo, uint32_t offset);
743
744 struct anv_address {
745 struct anv_bo *bo;
746 uint32_t offset;
747 };
748
749 #define __gen_address_type struct anv_address
750 #define __gen_user_data struct anv_batch
751
752 static inline uint64_t
753 __gen_combine_address(struct anv_batch *batch, void *location,
754 const struct anv_address address, uint32_t delta)
755 {
756 if (address.bo == NULL) {
757 return address.offset + delta;
758 } else {
759 assert(batch->start <= location && location < batch->end);
760
761 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
762 }
763 }
764
765 /* Wrapper macros needed to work around preprocessor argument issues. In
766 * particular, arguments don't get pre-evaluated if they are concatenated.
767 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
768 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
769 * We can work around this easily enough with these helpers.
770 */
771 #define __anv_cmd_length(cmd) cmd ## _length
772 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
773 #define __anv_cmd_header(cmd) cmd ## _header
774 #define __anv_cmd_pack(cmd) cmd ## _pack
775
776 #define anv_batch_emit(batch, cmd, ...) do { \
777 void *__dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
778 struct cmd __template = { \
779 __anv_cmd_header(cmd), \
780 __VA_ARGS__ \
781 }; \
782 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
783 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__dst, __anv_cmd_length(cmd) * 4)); \
784 } while (0)
785
786 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
787 void *__dst = anv_batch_emit_dwords(batch, n); \
788 struct cmd __template = { \
789 __anv_cmd_header(cmd), \
790 .DwordLength = n - __anv_cmd_length_bias(cmd), \
791 __VA_ARGS__ \
792 }; \
793 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
794 __dst; \
795 })
796
797 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
798 do { \
799 uint32_t *dw; \
800 \
801 static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
802 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
803 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
804 dw[i] = (dwords0)[i] | (dwords1)[i]; \
805 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
806 } while (0)
807
808 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
809 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
810 struct anv_state __state = \
811 anv_state_pool_alloc((pool), __size, align); \
812 struct cmd __template = { \
813 __VA_ARGS__ \
814 }; \
815 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
816 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
817 if (!(pool)->block_pool->device->info.has_llc) \
818 anv_state_clflush(__state); \
819 __state; \
820 })
821
822 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
823 .GraphicsDataTypeGFDT = 0, \
824 .LLCCacheabilityControlLLCCC = 0, \
825 .L3CacheabilityControlL3CC = 1, \
826 }
827
828 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
829 .LLCeLLCCacheabilityControlLLCCC = 0, \
830 .L3CacheabilityControlL3CC = 1, \
831 }
832
833 #define GEN8_MOCS { \
834 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
835 .TargetCache = L3DefertoPATforLLCeLLCselection, \
836 .AgeforQUADLRU = 0 \
837 }
838
839 /* Skylake: MOCS is now an index into an array of 62 different caching
840 * configurations programmed by the kernel.
841 */
842
843 #define GEN9_MOCS { \
844 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
845 .IndextoMOCSTables = 2 \
846 }
847
848 #define GEN9_MOCS_PTE { \
849 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
850 .IndextoMOCSTables = 1 \
851 }
852
853 struct anv_device_memory {
854 struct anv_bo bo;
855 uint32_t type_index;
856 VkDeviceSize map_size;
857 void * map;
858 };
859
860 /**
861 * Header for Vertex URB Entry (VUE)
862 */
863 struct anv_vue_header {
864 uint32_t Reserved;
865 uint32_t RTAIndex; /* RenderTargetArrayIndex */
866 uint32_t ViewportIndex;
867 float PointWidth;
868 };
869
870 struct anv_descriptor_set_binding_layout {
871 /* Number of array elements in this binding */
872 uint16_t array_size;
873
874 /* Index into the flattend descriptor set */
875 uint16_t descriptor_index;
876
877 /* Index into the dynamic state array for a dynamic buffer */
878 int16_t dynamic_offset_index;
879
880 /* Index into the descriptor set buffer views */
881 int16_t buffer_index;
882
883 struct {
884 /* Index into the binding table for the associated surface */
885 int16_t surface_index;
886
887 /* Index into the sampler table for the associated sampler */
888 int16_t sampler_index;
889
890 /* Index into the image table for the associated image */
891 int16_t image_index;
892 } stage[MESA_SHADER_STAGES];
893
894 /* Immutable samplers (or NULL if no immutable samplers) */
895 struct anv_sampler **immutable_samplers;
896 };
897
898 struct anv_descriptor_set_layout {
899 /* Number of bindings in this descriptor set */
900 uint16_t binding_count;
901
902 /* Total size of the descriptor set with room for all array entries */
903 uint16_t size;
904
905 /* Shader stages affected by this descriptor set */
906 uint16_t shader_stages;
907
908 /* Number of buffers in this descriptor set */
909 uint16_t buffer_count;
910
911 /* Number of dynamic offsets used by this descriptor set */
912 uint16_t dynamic_offset_count;
913
914 /* Bindings in this descriptor set */
915 struct anv_descriptor_set_binding_layout binding[0];
916 };
917
918 struct anv_descriptor {
919 VkDescriptorType type;
920
921 union {
922 struct {
923 union {
924 struct anv_image_view *image_view;
925 };
926 struct anv_sampler *sampler;
927 };
928
929 struct anv_buffer_view *buffer_view;
930 };
931 };
932
933 struct anv_descriptor_set {
934 const struct anv_descriptor_set_layout *layout;
935 struct anv_buffer_view *buffer_views;
936 struct anv_descriptor descriptors[0];
937 };
938
939 VkResult
940 anv_descriptor_set_create(struct anv_device *device,
941 const struct anv_descriptor_set_layout *layout,
942 struct anv_descriptor_set **out_set);
943
944 void
945 anv_descriptor_set_destroy(struct anv_device *device,
946 struct anv_descriptor_set *set);
947
948 struct anv_pipeline_binding {
949 /* The descriptor set this surface corresponds to */
950 uint16_t set;
951
952 /* Offset into the descriptor set */
953 uint16_t offset;
954 };
955
956 struct anv_pipeline_layout {
957 struct {
958 struct anv_descriptor_set_layout *layout;
959 uint32_t dynamic_offset_start;
960 struct {
961 uint32_t surface_start;
962 uint32_t sampler_start;
963 uint32_t image_start;
964 } stage[MESA_SHADER_STAGES];
965 } set[MAX_SETS];
966
967 uint32_t num_sets;
968
969 struct {
970 bool has_dynamic_offsets;
971 uint32_t surface_count;
972 struct anv_pipeline_binding *surface_to_descriptor;
973 uint32_t sampler_count;
974 struct anv_pipeline_binding *sampler_to_descriptor;
975 uint32_t image_count;
976 } stage[MESA_SHADER_STAGES];
977
978 struct anv_pipeline_binding entries[0];
979 };
980
981 struct anv_buffer {
982 struct anv_device * device;
983 VkDeviceSize size;
984
985 VkBufferUsageFlags usage;
986
987 /* Set when bound */
988 struct anv_bo * bo;
989 VkDeviceSize offset;
990 };
991
992 enum anv_cmd_dirty_bits {
993 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
994 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
995 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
996 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
997 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
998 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
999 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1000 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1001 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1002 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1003 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1004 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1005 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1006 };
1007 typedef uint32_t anv_cmd_dirty_mask_t;
1008
1009 struct anv_vertex_binding {
1010 struct anv_buffer * buffer;
1011 VkDeviceSize offset;
1012 };
1013
1014 struct anv_push_constants {
1015 /* Current allocated size of this push constants data structure.
1016 * Because a decent chunk of it may not be used (images on SKL, for
1017 * instance), we won't actually allocate the entire structure up-front.
1018 */
1019 uint32_t size;
1020
1021 /* Push constant data provided by the client through vkPushConstants */
1022 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1023
1024 /* Our hardware only provides zero-based vertex and instance id so, in
1025 * order to satisfy the vulkan requirements, we may have to push one or
1026 * both of these into the shader.
1027 */
1028 uint32_t base_vertex;
1029 uint32_t base_instance;
1030
1031 /* Offsets and ranges for dynamically bound buffers */
1032 struct {
1033 uint32_t offset;
1034 uint32_t range;
1035 } dynamic[MAX_DYNAMIC_BUFFERS];
1036
1037 /* Image data for image_load_store on pre-SKL */
1038 struct brw_image_param images[MAX_IMAGES];
1039 };
1040
1041 struct anv_dynamic_state {
1042 struct {
1043 uint32_t count;
1044 VkViewport viewports[MAX_VIEWPORTS];
1045 } viewport;
1046
1047 struct {
1048 uint32_t count;
1049 VkRect2D scissors[MAX_SCISSORS];
1050 } scissor;
1051
1052 float line_width;
1053
1054 struct {
1055 float bias;
1056 float clamp;
1057 float slope;
1058 } depth_bias;
1059
1060 float blend_constants[4];
1061
1062 struct {
1063 float min;
1064 float max;
1065 } depth_bounds;
1066
1067 struct {
1068 uint32_t front;
1069 uint32_t back;
1070 } stencil_compare_mask;
1071
1072 struct {
1073 uint32_t front;
1074 uint32_t back;
1075 } stencil_write_mask;
1076
1077 struct {
1078 uint32_t front;
1079 uint32_t back;
1080 } stencil_reference;
1081 };
1082
1083 extern const struct anv_dynamic_state default_dynamic_state;
1084
1085 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1086 const struct anv_dynamic_state *src,
1087 uint32_t copy_mask);
1088
1089 /**
1090 * Attachment state when recording a renderpass instance.
1091 *
1092 * The clear value is valid only if there exists a pending clear.
1093 */
1094 struct anv_attachment_state {
1095 VkImageAspectFlags pending_clear_aspects;
1096 VkClearValue clear_value;
1097 };
1098
1099 /** State required while building cmd buffer */
1100 struct anv_cmd_state {
1101 /* PIPELINE_SELECT.PipelineSelection */
1102 uint32_t current_pipeline;
1103 uint32_t current_l3_config;
1104 uint32_t vb_dirty;
1105 anv_cmd_dirty_mask_t dirty;
1106 anv_cmd_dirty_mask_t compute_dirty;
1107 uint32_t num_workgroups_offset;
1108 struct anv_bo *num_workgroups_bo;
1109 VkShaderStageFlags descriptors_dirty;
1110 VkShaderStageFlags push_constants_dirty;
1111 uint32_t scratch_size;
1112 struct anv_pipeline * pipeline;
1113 struct anv_pipeline * compute_pipeline;
1114 struct anv_framebuffer * framebuffer;
1115 struct anv_render_pass * pass;
1116 struct anv_subpass * subpass;
1117 uint32_t restart_index;
1118 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1119 struct anv_descriptor_set * descriptors[MAX_SETS];
1120 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1121 struct anv_state binding_tables[MESA_SHADER_STAGES];
1122 struct anv_state samplers[MESA_SHADER_STAGES];
1123 struct anv_dynamic_state dynamic;
1124 bool need_query_wa;
1125
1126 /**
1127 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1128 * valid only when recording a render pass instance.
1129 */
1130 struct anv_attachment_state * attachments;
1131
1132 struct {
1133 struct anv_buffer * index_buffer;
1134 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1135 uint32_t index_offset;
1136 } gen7;
1137 };
1138
1139 struct anv_cmd_pool {
1140 VkAllocationCallbacks alloc;
1141 struct list_head cmd_buffers;
1142 };
1143
1144 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1145
1146 enum anv_cmd_buffer_exec_mode {
1147 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1148 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1149 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1150 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1151 };
1152
1153 struct anv_cmd_buffer {
1154 VK_LOADER_DATA _loader_data;
1155
1156 struct anv_device * device;
1157
1158 struct anv_cmd_pool * pool;
1159 struct list_head pool_link;
1160
1161 struct anv_batch batch;
1162
1163 /* Fields required for the actual chain of anv_batch_bo's.
1164 *
1165 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1166 */
1167 struct list_head batch_bos;
1168 enum anv_cmd_buffer_exec_mode exec_mode;
1169
1170 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1171 * referenced by this command buffer
1172 *
1173 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1174 */
1175 struct anv_vector seen_bbos;
1176
1177 /* A vector of int32_t's for every block of binding tables.
1178 *
1179 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1180 */
1181 struct anv_vector bt_blocks;
1182 uint32_t bt_next;
1183 struct anv_reloc_list surface_relocs;
1184
1185 /* Information needed for execbuf
1186 *
1187 * These fields are generated by anv_cmd_buffer_prepare_execbuf().
1188 */
1189 struct {
1190 struct drm_i915_gem_execbuffer2 execbuf;
1191
1192 struct drm_i915_gem_exec_object2 * objects;
1193 uint32_t bo_count;
1194 struct anv_bo ** bos;
1195
1196 /* Allocated length of the 'objects' and 'bos' arrays */
1197 uint32_t array_length;
1198
1199 bool need_reloc;
1200 } execbuf2;
1201
1202 /* Serial for tracking buffer completion */
1203 uint32_t serial;
1204
1205 /* Stream objects for storing temporary data */
1206 struct anv_state_stream surface_state_stream;
1207 struct anv_state_stream dynamic_state_stream;
1208
1209 VkCommandBufferUsageFlags usage_flags;
1210 VkCommandBufferLevel level;
1211
1212 struct anv_cmd_state state;
1213 };
1214
1215 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1216 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1217 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1218 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1219 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1220 struct anv_cmd_buffer *secondary);
1221 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1222
1223 VkResult anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
1224 unsigned stage, struct anv_state *bt_state);
1225 VkResult anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
1226 unsigned stage, struct anv_state *state);
1227 uint32_t gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer);
1228 void gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
1229 uint32_t stages);
1230
1231 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1232 const void *data, uint32_t size, uint32_t alignment);
1233 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1234 uint32_t *a, uint32_t *b,
1235 uint32_t dwords, uint32_t alignment);
1236
1237 struct anv_address
1238 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1239 struct anv_state
1240 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1241 uint32_t entries, uint32_t *state_offset);
1242 struct anv_state
1243 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1244 struct anv_state
1245 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1246 uint32_t size, uint32_t alignment);
1247
1248 VkResult
1249 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1250
1251 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1252 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1253
1254 void gen7_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1255 void gen75_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1256 void gen8_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1257 void gen9_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1258
1259 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1260
1261 void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1262 const VkRenderPassBeginInfo *info);
1263
1264 void gen7_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1265 struct anv_subpass *subpass);
1266 void gen8_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1267 struct anv_subpass *subpass);
1268 void gen9_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1269 struct anv_subpass *subpass);
1270 void anv_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
1271 struct anv_subpass *subpass);
1272
1273 struct anv_state
1274 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1275 gl_shader_stage stage);
1276 struct anv_state
1277 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1278
1279 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1280 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1281
1282 const struct anv_image_view *
1283 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1284
1285 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1286
1287 struct anv_fence {
1288 struct anv_bo bo;
1289 struct drm_i915_gem_execbuffer2 execbuf;
1290 struct drm_i915_gem_exec_object2 exec2_objects[1];
1291 bool ready;
1292 };
1293
1294 struct anv_event {
1295 uint32_t semaphore;
1296 struct anv_state state;
1297 };
1298
1299 struct nir_shader;
1300
1301 struct anv_shader_module {
1302 struct nir_shader * nir;
1303
1304 uint32_t size;
1305 char data[0];
1306 };
1307
1308 static inline gl_shader_stage
1309 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1310 {
1311 assert(__builtin_popcount(vk_stage) == 1);
1312 return ffs(vk_stage) - 1;
1313 }
1314
1315 static inline VkShaderStageFlagBits
1316 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1317 {
1318 return (1 << mesa_stage);
1319 }
1320
1321 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1322
1323 #define anv_foreach_stage(stage, stage_bits) \
1324 for (gl_shader_stage stage, \
1325 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1326 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1327 __tmp &= ~(1 << (stage)))
1328
1329 struct anv_pipeline {
1330 struct anv_device * device;
1331 struct anv_batch batch;
1332 uint32_t batch_data[512];
1333 struct anv_reloc_list batch_relocs;
1334 uint32_t dynamic_state_mask;
1335 struct anv_dynamic_state dynamic_state;
1336
1337 struct anv_pipeline_layout * layout;
1338 bool use_repclear;
1339
1340 struct brw_vs_prog_data vs_prog_data;
1341 struct brw_wm_prog_data wm_prog_data;
1342 struct brw_gs_prog_data gs_prog_data;
1343 struct brw_cs_prog_data cs_prog_data;
1344 bool writes_point_size;
1345 struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
1346 uint32_t scratch_start[MESA_SHADER_STAGES];
1347 uint32_t total_scratch;
1348 struct {
1349 uint32_t vs_start;
1350 uint32_t vs_size;
1351 uint32_t nr_vs_entries;
1352 uint32_t gs_start;
1353 uint32_t gs_size;
1354 uint32_t nr_gs_entries;
1355 } urb;
1356
1357 VkShaderStageFlags active_stages;
1358 struct anv_state blend_state;
1359 uint32_t vs_simd8;
1360 uint32_t vs_vec4;
1361 uint32_t ps_simd8;
1362 uint32_t ps_simd16;
1363 uint32_t ps_ksp0;
1364 uint32_t ps_ksp2;
1365 uint32_t ps_grf_start0;
1366 uint32_t ps_grf_start2;
1367 uint32_t gs_kernel;
1368 uint32_t gs_vertex_count;
1369 uint32_t cs_simd;
1370
1371 uint32_t vb_used;
1372 uint32_t binding_stride[MAX_VBS];
1373 bool instancing_enable[MAX_VBS];
1374 bool primitive_restart;
1375 uint32_t topology;
1376
1377 uint32_t cs_thread_width_max;
1378 uint32_t cs_right_mask;
1379
1380 struct {
1381 uint32_t sf[7];
1382 uint32_t depth_stencil_state[3];
1383 } gen7;
1384
1385 struct {
1386 uint32_t sf[4];
1387 uint32_t raster[5];
1388 uint32_t wm_depth_stencil[3];
1389 } gen8;
1390
1391 struct {
1392 uint32_t wm_depth_stencil[4];
1393 } gen9;
1394 };
1395
1396 struct anv_graphics_pipeline_create_info {
1397 /**
1398 * If non-negative, overrides the color attachment count of the pipeline's
1399 * subpass.
1400 */
1401 int8_t color_attachment_count;
1402
1403 bool use_repclear;
1404 bool disable_viewport;
1405 bool disable_scissor;
1406 bool disable_vs;
1407 bool use_rectlist;
1408 };
1409
1410 VkResult
1411 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1412 struct anv_pipeline_cache *cache,
1413 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1414 const struct anv_graphics_pipeline_create_info *extra,
1415 const VkAllocationCallbacks *alloc);
1416
1417 VkResult
1418 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1419 struct anv_pipeline_cache *cache,
1420 const VkComputePipelineCreateInfo *info,
1421 struct anv_shader_module *module,
1422 const char *entrypoint,
1423 const VkSpecializationInfo *spec_info);
1424
1425 VkResult
1426 anv_graphics_pipeline_create(VkDevice device,
1427 VkPipelineCache cache,
1428 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1429 const struct anv_graphics_pipeline_create_info *extra,
1430 const VkAllocationCallbacks *alloc,
1431 VkPipeline *pPipeline);
1432
1433 VkResult
1434 gen7_graphics_pipeline_create(VkDevice _device,
1435 struct anv_pipeline_cache *cache,
1436 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1437 const struct anv_graphics_pipeline_create_info *extra,
1438 const VkAllocationCallbacks *alloc,
1439 VkPipeline *pPipeline);
1440
1441 VkResult
1442 gen75_graphics_pipeline_create(VkDevice _device,
1443 struct anv_pipeline_cache *cache,
1444 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1445 const struct anv_graphics_pipeline_create_info *extra,
1446 const VkAllocationCallbacks *alloc,
1447 VkPipeline *pPipeline);
1448
1449 VkResult
1450 gen8_graphics_pipeline_create(VkDevice _device,
1451 struct anv_pipeline_cache *cache,
1452 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1453 const struct anv_graphics_pipeline_create_info *extra,
1454 const VkAllocationCallbacks *alloc,
1455 VkPipeline *pPipeline);
1456 VkResult
1457 gen9_graphics_pipeline_create(VkDevice _device,
1458 struct anv_pipeline_cache *cache,
1459 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1460 const struct anv_graphics_pipeline_create_info *extra,
1461 const VkAllocationCallbacks *alloc,
1462 VkPipeline *pPipeline);
1463 VkResult
1464 gen7_compute_pipeline_create(VkDevice _device,
1465 struct anv_pipeline_cache *cache,
1466 const VkComputePipelineCreateInfo *pCreateInfo,
1467 const VkAllocationCallbacks *alloc,
1468 VkPipeline *pPipeline);
1469 VkResult
1470 gen75_compute_pipeline_create(VkDevice _device,
1471 struct anv_pipeline_cache *cache,
1472 const VkComputePipelineCreateInfo *pCreateInfo,
1473 const VkAllocationCallbacks *alloc,
1474 VkPipeline *pPipeline);
1475
1476 VkResult
1477 gen8_compute_pipeline_create(VkDevice _device,
1478 struct anv_pipeline_cache *cache,
1479 const VkComputePipelineCreateInfo *pCreateInfo,
1480 const VkAllocationCallbacks *alloc,
1481 VkPipeline *pPipeline);
1482 VkResult
1483 gen9_compute_pipeline_create(VkDevice _device,
1484 struct anv_pipeline_cache *cache,
1485 const VkComputePipelineCreateInfo *pCreateInfo,
1486 const VkAllocationCallbacks *alloc,
1487 VkPipeline *pPipeline);
1488
1489 struct anv_format_swizzle {
1490 unsigned r:2;
1491 unsigned g:2;
1492 unsigned b:2;
1493 unsigned a:2;
1494 };
1495
1496 struct anv_format {
1497 const VkFormat vk_format;
1498 const char *name;
1499 enum isl_format surface_format; /**< RENDER_SURFACE_STATE.SurfaceFormat */
1500 const struct isl_format_layout *isl_layout;
1501 uint16_t depth_format; /**< 3DSTATE_DEPTH_BUFFER.SurfaceFormat */
1502 struct anv_format_swizzle swizzle;
1503 bool has_stencil;
1504 };
1505
1506 const struct anv_format *
1507 anv_format_for_vk_format(VkFormat format);
1508
1509 enum isl_format
1510 anv_get_isl_format(VkFormat format, VkImageAspectFlags aspect,
1511 VkImageTiling tiling, struct anv_format_swizzle *swizzle);
1512
1513 static inline bool
1514 anv_format_is_color(const struct anv_format *format)
1515 {
1516 return !format->depth_format && !format->has_stencil;
1517 }
1518
1519 static inline bool
1520 anv_format_is_depth_or_stencil(const struct anv_format *format)
1521 {
1522 return format->depth_format || format->has_stencil;
1523 }
1524
1525 /**
1526 * Subsurface of an anv_image.
1527 */
1528 struct anv_surface {
1529 struct isl_surf isl;
1530
1531 /**
1532 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1533 */
1534 uint32_t offset;
1535 };
1536
1537 struct anv_image {
1538 VkImageType type;
1539 /* The original VkFormat provided by the client. This may not match any
1540 * of the actual surface formats.
1541 */
1542 VkFormat vk_format;
1543 const struct anv_format *format;
1544 VkExtent3D extent;
1545 uint32_t levels;
1546 uint32_t array_size;
1547 uint32_t samples; /**< VkImageCreateInfo::samples */
1548 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1549 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1550
1551 VkDeviceSize size;
1552 uint32_t alignment;
1553
1554 /* Set when bound */
1555 struct anv_bo *bo;
1556 VkDeviceSize offset;
1557
1558 bool needs_nonrt_surface_state:1;
1559 bool needs_color_rt_surface_state:1;
1560 bool needs_storage_surface_state:1;
1561
1562 /**
1563 * Image subsurfaces
1564 *
1565 * For each foo, anv_image::foo_surface is valid if and only if
1566 * anv_image::format has a foo aspect.
1567 *
1568 * The hardware requires that the depth buffer and stencil buffer be
1569 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1570 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1571 * allocate the depth and stencil buffers as separate surfaces in the same
1572 * bo.
1573 */
1574 union {
1575 struct anv_surface color_surface;
1576
1577 struct {
1578 struct anv_surface depth_surface;
1579 struct anv_surface stencil_surface;
1580 };
1581 };
1582 };
1583
1584 struct anv_image_view {
1585 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1586 struct anv_bo *bo;
1587 uint32_t offset; /**< Offset into bo. */
1588
1589 VkImageAspectFlags aspect_mask;
1590 VkFormat vk_format;
1591 VkComponentMapping swizzle;
1592 enum isl_format format;
1593 uint32_t base_layer;
1594 uint32_t base_mip;
1595 VkExtent3D level_0_extent; /**< Extent of ::image's level 0 adjusted for ::vk_format. */
1596 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1597
1598 /** RENDER_SURFACE_STATE when using image as a color render target. */
1599 struct anv_state color_rt_surface_state;
1600
1601 /** RENDER_SURFACE_STATE when using image as a non render target. */
1602 struct anv_state nonrt_surface_state;
1603
1604 /** RENDER_SURFACE_STATE when using image as a storage image. */
1605 struct anv_state storage_surface_state;
1606 };
1607
1608 struct anv_image_create_info {
1609 const VkImageCreateInfo *vk_info;
1610 isl_tiling_flags_t isl_tiling_flags;
1611 uint32_t stride;
1612 };
1613
1614 VkResult anv_image_create(VkDevice _device,
1615 const struct anv_image_create_info *info,
1616 const VkAllocationCallbacks* alloc,
1617 VkImage *pImage);
1618
1619 struct anv_surface *
1620 anv_image_get_surface_for_aspect_mask(struct anv_image *image,
1621 VkImageAspectFlags aspect_mask);
1622
1623 void anv_image_view_init(struct anv_image_view *view,
1624 struct anv_device *device,
1625 const VkImageViewCreateInfo* pCreateInfo,
1626 struct anv_cmd_buffer *cmd_buffer,
1627 uint32_t offset);
1628
1629 void
1630 anv_fill_image_surface_state(struct anv_device *device, struct anv_state state,
1631 struct anv_image_view *iview,
1632 const VkImageViewCreateInfo *pCreateInfo,
1633 VkImageUsageFlagBits usage);
1634 void
1635 gen7_fill_image_surface_state(struct anv_device *device, void *state_map,
1636 struct anv_image_view *iview,
1637 const VkImageViewCreateInfo *pCreateInfo,
1638 VkImageUsageFlagBits usage);
1639 void
1640 gen75_fill_image_surface_state(struct anv_device *device, void *state_map,
1641 struct anv_image_view *iview,
1642 const VkImageViewCreateInfo *pCreateInfo,
1643 VkImageUsageFlagBits usage);
1644 void
1645 gen8_fill_image_surface_state(struct anv_device *device, void *state_map,
1646 struct anv_image_view *iview,
1647 const VkImageViewCreateInfo *pCreateInfo,
1648 VkImageUsageFlagBits usage);
1649 void
1650 gen9_fill_image_surface_state(struct anv_device *device, void *state_map,
1651 struct anv_image_view *iview,
1652 const VkImageViewCreateInfo *pCreateInfo,
1653 VkImageUsageFlagBits usage);
1654
1655 struct anv_buffer_view {
1656 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1657 struct anv_bo *bo;
1658 uint32_t offset; /**< Offset into bo. */
1659 uint64_t range; /**< VkBufferViewCreateInfo::range */
1660
1661 struct anv_state surface_state;
1662 struct anv_state storage_surface_state;
1663 };
1664
1665 const struct anv_format *
1666 anv_format_for_descriptor_type(VkDescriptorType type);
1667
1668 void anv_fill_buffer_surface_state(struct anv_device *device,
1669 struct anv_state state,
1670 enum isl_format format,
1671 uint32_t offset, uint32_t range,
1672 uint32_t stride);
1673
1674 void gen7_fill_buffer_surface_state(void *state, enum isl_format format,
1675 uint32_t offset, uint32_t range,
1676 uint32_t stride);
1677 void gen75_fill_buffer_surface_state(void *state, enum isl_format format,
1678 uint32_t offset, uint32_t range,
1679 uint32_t stride);
1680 void gen8_fill_buffer_surface_state(void *state, enum isl_format format,
1681 uint32_t offset, uint32_t range,
1682 uint32_t stride);
1683 void gen9_fill_buffer_surface_state(void *state, enum isl_format format,
1684 uint32_t offset, uint32_t range,
1685 uint32_t stride);
1686
1687 void anv_image_view_fill_image_param(struct anv_device *device,
1688 struct anv_image_view *view,
1689 struct brw_image_param *param);
1690 void anv_buffer_view_fill_image_param(struct anv_device *device,
1691 struct anv_buffer_view *view,
1692 struct brw_image_param *param);
1693
1694 struct anv_sampler {
1695 uint32_t state[4];
1696 };
1697
1698 struct anv_framebuffer {
1699 uint32_t width;
1700 uint32_t height;
1701 uint32_t layers;
1702
1703 uint32_t attachment_count;
1704 struct anv_image_view * attachments[0];
1705 };
1706
1707 struct anv_subpass {
1708 uint32_t input_count;
1709 uint32_t * input_attachments;
1710 uint32_t color_count;
1711 uint32_t * color_attachments;
1712 uint32_t * resolve_attachments;
1713 uint32_t depth_stencil_attachment;
1714
1715 /** Subpass has at least one resolve attachment */
1716 bool has_resolve;
1717 };
1718
1719 struct anv_render_pass_attachment {
1720 const struct anv_format *format;
1721 uint32_t samples;
1722 VkAttachmentLoadOp load_op;
1723 VkAttachmentLoadOp stencil_load_op;
1724 };
1725
1726 struct anv_render_pass {
1727 uint32_t attachment_count;
1728 uint32_t subpass_count;
1729 uint32_t * subpass_attachments;
1730 struct anv_render_pass_attachment * attachments;
1731 struct anv_subpass subpasses[0];
1732 };
1733
1734 extern struct anv_render_pass anv_meta_dummy_renderpass;
1735
1736 struct anv_query_pool_slot {
1737 uint64_t begin;
1738 uint64_t end;
1739 uint64_t available;
1740 };
1741
1742 struct anv_query_pool {
1743 VkQueryType type;
1744 uint32_t slots;
1745 struct anv_bo bo;
1746 };
1747
1748 VkResult anv_device_init_meta(struct anv_device *device);
1749 void anv_device_finish_meta(struct anv_device *device);
1750
1751 void *anv_lookup_entrypoint(const char *name);
1752
1753 void anv_dump_image_to_ppm(struct anv_device *device,
1754 struct anv_image *image, unsigned miplevel,
1755 unsigned array_layer, const char *filename);
1756
1757 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1758 \
1759 static inline struct __anv_type * \
1760 __anv_type ## _from_handle(__VkType _handle) \
1761 { \
1762 return (struct __anv_type *) _handle; \
1763 } \
1764 \
1765 static inline __VkType \
1766 __anv_type ## _to_handle(struct __anv_type *_obj) \
1767 { \
1768 return (__VkType) _obj; \
1769 }
1770
1771 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1772 \
1773 static inline struct __anv_type * \
1774 __anv_type ## _from_handle(__VkType _handle) \
1775 { \
1776 return (struct __anv_type *)(uintptr_t) _handle; \
1777 } \
1778 \
1779 static inline __VkType \
1780 __anv_type ## _to_handle(struct __anv_type *_obj) \
1781 { \
1782 return (__VkType)(uintptr_t) _obj; \
1783 }
1784
1785 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1786 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1787
1788 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1789 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1790 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1791 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1792 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1793
1794 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1795 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1796 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1797 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1798 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1799 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1800 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1801 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1802 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1803 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1804 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1805 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1806 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1807 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1808 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1809 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1810 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1811 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1812
1813 #define ANV_DEFINE_STRUCT_CASTS(__anv_type, __VkType) \
1814 \
1815 static inline const __VkType * \
1816 __anv_type ## _to_ ## __VkType(const struct __anv_type *__anv_obj) \
1817 { \
1818 return (const __VkType *) __anv_obj; \
1819 }
1820
1821 #define ANV_COMMON_TO_STRUCT(__VkType, __vk_name, __common_name) \
1822 const __VkType *__vk_name = anv_common_to_ ## __VkType(__common_name)
1823
1824 ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
1825 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
1826 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
1827
1828 #ifdef __cplusplus
1829 }
1830 #endif