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vk: Set binding table layout for CS
[mesa.git] / src / vulkan / gen75_pack.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 /* Instructions, enums and structures for HSW.
26 *
27 * This file has been generated, do not hand edit.
28 */
29
30 #pragma once
31
32 #include <stdio.h>
33 #include <assert.h>
34
35 #ifndef __gen_validate_value
36 #define __gen_validate_value(x)
37 #endif
38
39 #ifndef __gen_field_functions
40 #define __gen_field_functions
41
42 union __gen_value {
43 float f;
44 uint32_t dw;
45 };
46
47 static inline uint64_t
48 __gen_field(uint64_t v, uint32_t start, uint32_t end)
49 {
50 __gen_validate_value(v);
51 #if DEBUG
52 if (end - start + 1 < 64)
53 assert(v < 1ul << (end - start + 1));
54 #endif
55
56 return v << start;
57 }
58
59 static inline uint64_t
60 __gen_offset(uint64_t v, uint32_t start, uint32_t end)
61 {
62 __gen_validate_value(v);
63 #if DEBUG
64 uint64_t mask = (~0ul >> (64 - (end - start + 1))) << start;
65
66 assert((v & ~mask) == 0);
67 #endif
68
69 return v;
70 }
71
72 static inline uint32_t
73 __gen_float(float v)
74 {
75 __gen_validate_value(v);
76 return ((union __gen_value) { .f = (v) }).dw;
77 }
78
79 #ifndef __gen_address_type
80 #error #define __gen_address_type before including this file
81 #endif
82
83 #ifndef __gen_user_data
84 #error #define __gen_combine_address before including this file
85 #endif
86
87 #endif
88
89 #define GEN75_3DSTATE_URB_VS_length 0x00000002
90 #define GEN75_3DSTATE_URB_VS_length_bias 0x00000002
91 #define GEN75_3DSTATE_URB_VS_header \
92 .CommandType = 3, \
93 .CommandSubType = 3, \
94 ._3DCommandOpcode = 0, \
95 ._3DCommandSubOpcode = 48, \
96 .DwordLength = 0
97
98 struct GEN75_3DSTATE_URB_VS {
99 uint32_t CommandType;
100 uint32_t CommandSubType;
101 uint32_t _3DCommandOpcode;
102 uint32_t _3DCommandSubOpcode;
103 uint32_t DwordLength;
104 uint32_t VSURBStartingAddress;
105 uint32_t VSURBEntryAllocationSize;
106 uint32_t VSNumberofURBEntries;
107 };
108
109 static inline void
110 GEN75_3DSTATE_URB_VS_pack(__gen_user_data *data, void * restrict dst,
111 const struct GEN75_3DSTATE_URB_VS * restrict values)
112 {
113 uint32_t *dw = (uint32_t * restrict) dst;
114
115 dw[0] =
116 __gen_field(values->CommandType, 29, 31) |
117 __gen_field(values->CommandSubType, 27, 28) |
118 __gen_field(values->_3DCommandOpcode, 24, 26) |
119 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
120 __gen_field(values->DwordLength, 0, 7) |
121 0;
122
123 dw[1] =
124 __gen_field(values->VSURBStartingAddress, 25, 30) |
125 __gen_field(values->VSURBEntryAllocationSize, 16, 24) |
126 __gen_field(values->VSNumberofURBEntries, 0, 15) |
127 0;
128
129 }
130
131 #define GEN75_GPGPU_CSR_BASE_ADDRESS_length 0x00000002
132 #define GEN75_GPGPU_CSR_BASE_ADDRESS_length_bias 0x00000002
133 #define GEN75_GPGPU_CSR_BASE_ADDRESS_header \
134 .CommandType = 3, \
135 .CommandSubType = 0, \
136 ._3DCommandOpcode = 1, \
137 ._3DCommandSubOpcode = 4, \
138 .DwordLength = 0
139
140 struct GEN75_GPGPU_CSR_BASE_ADDRESS {
141 uint32_t CommandType;
142 uint32_t CommandSubType;
143 uint32_t _3DCommandOpcode;
144 uint32_t _3DCommandSubOpcode;
145 uint32_t DwordLength;
146 __gen_address_type GPGPUCSRBaseAddress;
147 };
148
149 static inline void
150 GEN75_GPGPU_CSR_BASE_ADDRESS_pack(__gen_user_data *data, void * restrict dst,
151 const struct GEN75_GPGPU_CSR_BASE_ADDRESS * restrict values)
152 {
153 uint32_t *dw = (uint32_t * restrict) dst;
154
155 dw[0] =
156 __gen_field(values->CommandType, 29, 31) |
157 __gen_field(values->CommandSubType, 27, 28) |
158 __gen_field(values->_3DCommandOpcode, 24, 26) |
159 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
160 __gen_field(values->DwordLength, 0, 7) |
161 0;
162
163 uint32_t dw1 =
164 0;
165
166 dw[1] =
167 __gen_combine_address(data, &dw[1], values->GPGPUCSRBaseAddress, dw1);
168
169 }
170
171 #define GEN75_MI_STORE_REGISTER_MEM_length 0x00000003
172 #define GEN75_MI_STORE_REGISTER_MEM_length_bias 0x00000002
173 #define GEN75_MI_STORE_REGISTER_MEM_header \
174 .CommandType = 0, \
175 .MICommandOpcode = 36, \
176 .DwordLength = 1
177
178 struct GEN75_MI_STORE_REGISTER_MEM {
179 uint32_t CommandType;
180 uint32_t MICommandOpcode;
181 uint32_t UseGlobalGTT;
182 uint32_t PredicateEnable;
183 uint32_t DwordLength;
184 uint32_t RegisterAddress;
185 __gen_address_type MemoryAddress;
186 };
187
188 static inline void
189 GEN75_MI_STORE_REGISTER_MEM_pack(__gen_user_data *data, void * restrict dst,
190 const struct GEN75_MI_STORE_REGISTER_MEM * restrict values)
191 {
192 uint32_t *dw = (uint32_t * restrict) dst;
193
194 dw[0] =
195 __gen_field(values->CommandType, 29, 31) |
196 __gen_field(values->MICommandOpcode, 23, 28) |
197 __gen_field(values->UseGlobalGTT, 22, 22) |
198 __gen_field(values->PredicateEnable, 21, 21) |
199 __gen_field(values->DwordLength, 0, 7) |
200 0;
201
202 dw[1] =
203 __gen_offset(values->RegisterAddress, 2, 22) |
204 0;
205
206 uint32_t dw2 =
207 0;
208
209 dw[2] =
210 __gen_combine_address(data, &dw[2], values->MemoryAddress, dw2);
211
212 }
213
214 #define GEN75_PIPELINE_SELECT_length 0x00000001
215 #define GEN75_PIPELINE_SELECT_length_bias 0x00000001
216 #define GEN75_PIPELINE_SELECT_header \
217 .CommandType = 3, \
218 .CommandSubType = 1, \
219 ._3DCommandOpcode = 1, \
220 ._3DCommandSubOpcode = 4
221
222 struct GEN75_PIPELINE_SELECT {
223 uint32_t CommandType;
224 uint32_t CommandSubType;
225 uint32_t _3DCommandOpcode;
226 uint32_t _3DCommandSubOpcode;
227 #define _3D 0
228 #define Media 1
229 #define GPGPU 2
230 uint32_t PipelineSelection;
231 };
232
233 static inline void
234 GEN75_PIPELINE_SELECT_pack(__gen_user_data *data, void * restrict dst,
235 const struct GEN75_PIPELINE_SELECT * restrict values)
236 {
237 uint32_t *dw = (uint32_t * restrict) dst;
238
239 dw[0] =
240 __gen_field(values->CommandType, 29, 31) |
241 __gen_field(values->CommandSubType, 27, 28) |
242 __gen_field(values->_3DCommandOpcode, 24, 26) |
243 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
244 __gen_field(values->PipelineSelection, 0, 1) |
245 0;
246
247 }
248
249 #define GEN75_STATE_BASE_ADDRESS_length 0x0000000a
250 #define GEN75_STATE_BASE_ADDRESS_length_bias 0x00000002
251 #define GEN75_STATE_BASE_ADDRESS_header \
252 .CommandType = 3, \
253 .CommandSubType = 0, \
254 ._3DCommandOpcode = 1, \
255 ._3DCommandSubOpcode = 1, \
256 .DwordLength = 8
257
258 struct GEN75_MEMORY_OBJECT_CONTROL_STATE {
259 uint32_t LLCeLLCCacheabilityControlLLCCC;
260 uint32_t L3CacheabilityControlL3CC;
261 };
262
263 static inline void
264 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(__gen_user_data *data, void * restrict dst,
265 const struct GEN75_MEMORY_OBJECT_CONTROL_STATE * restrict values)
266 {
267 uint32_t *dw = (uint32_t * restrict) dst;
268
269 dw[0] =
270 __gen_field(values->LLCeLLCCacheabilityControlLLCCC, 1, 2) |
271 __gen_field(values->L3CacheabilityControlL3CC, 0, 0) |
272 0;
273
274 }
275
276 struct GEN75_STATE_BASE_ADDRESS {
277 uint32_t CommandType;
278 uint32_t CommandSubType;
279 uint32_t _3DCommandOpcode;
280 uint32_t _3DCommandSubOpcode;
281 uint32_t DwordLength;
282 __gen_address_type GeneralStateBaseAddress;
283 struct GEN75_MEMORY_OBJECT_CONTROL_STATE GeneralStateMemoryObjectControlState;
284 struct GEN75_MEMORY_OBJECT_CONTROL_STATE StatelessDataPortAccessMemoryObjectControlState;
285 uint32_t GeneralStateBaseAddressModifyEnable;
286 __gen_address_type SurfaceStateBaseAddress;
287 struct GEN75_MEMORY_OBJECT_CONTROL_STATE SurfaceStateMemoryObjectControlState;
288 uint32_t SurfaceStateBaseAddressModifyEnable;
289 __gen_address_type DynamicStateBaseAddress;
290 struct GEN75_MEMORY_OBJECT_CONTROL_STATE DynamicStateMemoryObjectControlState;
291 uint32_t DynamicStateBaseAddressModifyEnable;
292 __gen_address_type IndirectObjectBaseAddress;
293 struct GEN75_MEMORY_OBJECT_CONTROL_STATE IndirectObjectMemoryObjectControlState;
294 uint32_t IndirectObjectBaseAddressModifyEnable;
295 __gen_address_type InstructionBaseAddress;
296 struct GEN75_MEMORY_OBJECT_CONTROL_STATE InstructionMemoryObjectControlState;
297 uint32_t InstructionBaseAddressModifyEnable;
298 __gen_address_type GeneralStateAccessUpperBound;
299 uint32_t GeneralStateAccessUpperBoundModifyEnable;
300 __gen_address_type DynamicStateAccessUpperBound;
301 uint32_t DynamicStateAccessUpperBoundModifyEnable;
302 __gen_address_type IndirectObjectAccessUpperBound;
303 uint32_t IndirectObjectAccessUpperBoundModifyEnable;
304 __gen_address_type InstructionAccessUpperBound;
305 uint32_t InstructionAccessUpperBoundModifyEnable;
306 };
307
308 static inline void
309 GEN75_STATE_BASE_ADDRESS_pack(__gen_user_data *data, void * restrict dst,
310 const struct GEN75_STATE_BASE_ADDRESS * restrict values)
311 {
312 uint32_t *dw = (uint32_t * restrict) dst;
313
314 dw[0] =
315 __gen_field(values->CommandType, 29, 31) |
316 __gen_field(values->CommandSubType, 27, 28) |
317 __gen_field(values->_3DCommandOpcode, 24, 26) |
318 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
319 __gen_field(values->DwordLength, 0, 7) |
320 0;
321
322 uint32_t dw_GeneralStateMemoryObjectControlState;
323 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_GeneralStateMemoryObjectControlState, &values->GeneralStateMemoryObjectControlState);
324 uint32_t dw_StatelessDataPortAccessMemoryObjectControlState;
325 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_StatelessDataPortAccessMemoryObjectControlState, &values->StatelessDataPortAccessMemoryObjectControlState);
326 uint32_t dw1 =
327 __gen_field(dw_GeneralStateMemoryObjectControlState, 8, 11) |
328 __gen_field(dw_StatelessDataPortAccessMemoryObjectControlState, 4, 7) |
329 __gen_field(values->GeneralStateBaseAddressModifyEnable, 0, 0) |
330 0;
331
332 dw[1] =
333 __gen_combine_address(data, &dw[1], values->GeneralStateBaseAddress, dw1);
334
335 uint32_t dw_SurfaceStateMemoryObjectControlState;
336 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_SurfaceStateMemoryObjectControlState, &values->SurfaceStateMemoryObjectControlState);
337 uint32_t dw2 =
338 __gen_field(dw_SurfaceStateMemoryObjectControlState, 8, 11) |
339 __gen_field(values->SurfaceStateBaseAddressModifyEnable, 0, 0) |
340 0;
341
342 dw[2] =
343 __gen_combine_address(data, &dw[2], values->SurfaceStateBaseAddress, dw2);
344
345 uint32_t dw_DynamicStateMemoryObjectControlState;
346 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_DynamicStateMemoryObjectControlState, &values->DynamicStateMemoryObjectControlState);
347 uint32_t dw3 =
348 __gen_field(dw_DynamicStateMemoryObjectControlState, 8, 11) |
349 __gen_field(values->DynamicStateBaseAddressModifyEnable, 0, 0) |
350 0;
351
352 dw[3] =
353 __gen_combine_address(data, &dw[3], values->DynamicStateBaseAddress, dw3);
354
355 uint32_t dw_IndirectObjectMemoryObjectControlState;
356 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_IndirectObjectMemoryObjectControlState, &values->IndirectObjectMemoryObjectControlState);
357 uint32_t dw4 =
358 __gen_field(dw_IndirectObjectMemoryObjectControlState, 8, 11) |
359 __gen_field(values->IndirectObjectBaseAddressModifyEnable, 0, 0) |
360 0;
361
362 dw[4] =
363 __gen_combine_address(data, &dw[4], values->IndirectObjectBaseAddress, dw4);
364
365 uint32_t dw_InstructionMemoryObjectControlState;
366 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_InstructionMemoryObjectControlState, &values->InstructionMemoryObjectControlState);
367 uint32_t dw5 =
368 __gen_field(dw_InstructionMemoryObjectControlState, 8, 11) |
369 __gen_field(values->InstructionBaseAddressModifyEnable, 0, 0) |
370 0;
371
372 dw[5] =
373 __gen_combine_address(data, &dw[5], values->InstructionBaseAddress, dw5);
374
375 uint32_t dw6 =
376 __gen_field(values->GeneralStateAccessUpperBoundModifyEnable, 0, 0) |
377 0;
378
379 dw[6] =
380 __gen_combine_address(data, &dw[6], values->GeneralStateAccessUpperBound, dw6);
381
382 uint32_t dw7 =
383 __gen_field(values->DynamicStateAccessUpperBoundModifyEnable, 0, 0) |
384 0;
385
386 dw[7] =
387 __gen_combine_address(data, &dw[7], values->DynamicStateAccessUpperBound, dw7);
388
389 uint32_t dw8 =
390 __gen_field(values->IndirectObjectAccessUpperBoundModifyEnable, 0, 0) |
391 0;
392
393 dw[8] =
394 __gen_combine_address(data, &dw[8], values->IndirectObjectAccessUpperBound, dw8);
395
396 uint32_t dw9 =
397 __gen_field(values->InstructionAccessUpperBoundModifyEnable, 0, 0) |
398 0;
399
400 dw[9] =
401 __gen_combine_address(data, &dw[9], values->InstructionAccessUpperBound, dw9);
402
403 }
404
405 #define GEN75_STATE_PREFETCH_length 0x00000002
406 #define GEN75_STATE_PREFETCH_length_bias 0x00000002
407 #define GEN75_STATE_PREFETCH_header \
408 .CommandType = 3, \
409 .CommandSubType = 0, \
410 ._3DCommandOpcode = 0, \
411 ._3DCommandSubOpcode = 3, \
412 .DwordLength = 0
413
414 struct GEN75_STATE_PREFETCH {
415 uint32_t CommandType;
416 uint32_t CommandSubType;
417 uint32_t _3DCommandOpcode;
418 uint32_t _3DCommandSubOpcode;
419 uint32_t DwordLength;
420 __gen_address_type PrefetchPointer;
421 uint32_t PrefetchCount;
422 };
423
424 static inline void
425 GEN75_STATE_PREFETCH_pack(__gen_user_data *data, void * restrict dst,
426 const struct GEN75_STATE_PREFETCH * restrict values)
427 {
428 uint32_t *dw = (uint32_t * restrict) dst;
429
430 dw[0] =
431 __gen_field(values->CommandType, 29, 31) |
432 __gen_field(values->CommandSubType, 27, 28) |
433 __gen_field(values->_3DCommandOpcode, 24, 26) |
434 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
435 __gen_field(values->DwordLength, 0, 7) |
436 0;
437
438 uint32_t dw1 =
439 __gen_field(values->PrefetchCount, 0, 2) |
440 0;
441
442 dw[1] =
443 __gen_combine_address(data, &dw[1], values->PrefetchPointer, dw1);
444
445 }
446
447 #define GEN75_STATE_SIP_length 0x00000002
448 #define GEN75_STATE_SIP_length_bias 0x00000002
449 #define GEN75_STATE_SIP_header \
450 .CommandType = 3, \
451 .CommandSubType = 0, \
452 ._3DCommandOpcode = 1, \
453 ._3DCommandSubOpcode = 2, \
454 .DwordLength = 0
455
456 struct GEN75_STATE_SIP {
457 uint32_t CommandType;
458 uint32_t CommandSubType;
459 uint32_t _3DCommandOpcode;
460 uint32_t _3DCommandSubOpcode;
461 uint32_t DwordLength;
462 uint32_t SystemInstructionPointer;
463 };
464
465 static inline void
466 GEN75_STATE_SIP_pack(__gen_user_data *data, void * restrict dst,
467 const struct GEN75_STATE_SIP * restrict values)
468 {
469 uint32_t *dw = (uint32_t * restrict) dst;
470
471 dw[0] =
472 __gen_field(values->CommandType, 29, 31) |
473 __gen_field(values->CommandSubType, 27, 28) |
474 __gen_field(values->_3DCommandOpcode, 24, 26) |
475 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
476 __gen_field(values->DwordLength, 0, 7) |
477 0;
478
479 dw[1] =
480 __gen_offset(values->SystemInstructionPointer, 4, 31) |
481 0;
482
483 }
484
485 #define GEN75_SWTESS_BASE_ADDRESS_length 0x00000002
486 #define GEN75_SWTESS_BASE_ADDRESS_length_bias 0x00000002
487 #define GEN75_SWTESS_BASE_ADDRESS_header \
488 .CommandType = 3, \
489 .CommandSubType = 0, \
490 ._3DCommandOpcode = 1, \
491 ._3DCommandSubOpcode = 3, \
492 .DwordLength = 0
493
494 struct GEN75_SWTESS_BASE_ADDRESS {
495 uint32_t CommandType;
496 uint32_t CommandSubType;
497 uint32_t _3DCommandOpcode;
498 uint32_t _3DCommandSubOpcode;
499 uint32_t DwordLength;
500 __gen_address_type SWTessellationBaseAddress;
501 struct GEN75_MEMORY_OBJECT_CONTROL_STATE SWTessellationMemoryObjectControlState;
502 };
503
504 static inline void
505 GEN75_SWTESS_BASE_ADDRESS_pack(__gen_user_data *data, void * restrict dst,
506 const struct GEN75_SWTESS_BASE_ADDRESS * restrict values)
507 {
508 uint32_t *dw = (uint32_t * restrict) dst;
509
510 dw[0] =
511 __gen_field(values->CommandType, 29, 31) |
512 __gen_field(values->CommandSubType, 27, 28) |
513 __gen_field(values->_3DCommandOpcode, 24, 26) |
514 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
515 __gen_field(values->DwordLength, 0, 7) |
516 0;
517
518 uint32_t dw_SWTessellationMemoryObjectControlState;
519 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_SWTessellationMemoryObjectControlState, &values->SWTessellationMemoryObjectControlState);
520 uint32_t dw1 =
521 __gen_field(dw_SWTessellationMemoryObjectControlState, 8, 11) |
522 0;
523
524 dw[1] =
525 __gen_combine_address(data, &dw[1], values->SWTessellationBaseAddress, dw1);
526
527 }
528
529 #define GEN75_3DPRIMITIVE_length 0x00000007
530 #define GEN75_3DPRIMITIVE_length_bias 0x00000002
531 #define GEN75_3DPRIMITIVE_header \
532 .CommandType = 3, \
533 .CommandSubType = 3, \
534 ._3DCommandOpcode = 3, \
535 ._3DCommandSubOpcode = 0, \
536 .DwordLength = 5
537
538 struct GEN75_3DPRIMITIVE {
539 uint32_t CommandType;
540 uint32_t CommandSubType;
541 uint32_t _3DCommandOpcode;
542 uint32_t _3DCommandSubOpcode;
543 uint32_t IndirectParameterEnable;
544 uint32_t UAVCoherencyRequired;
545 uint32_t PredicateEnable;
546 uint32_t DwordLength;
547 uint32_t EndOffsetEnable;
548 #define SEQUENTIAL 0
549 #define RANDOM 1
550 uint32_t VertexAccessType;
551 uint32_t PrimitiveTopologyType;
552 uint32_t VertexCountPerInstance;
553 uint32_t StartVertexLocation;
554 uint32_t InstanceCount;
555 uint32_t StartInstanceLocation;
556 uint32_t BaseVertexLocation;
557 };
558
559 static inline void
560 GEN75_3DPRIMITIVE_pack(__gen_user_data *data, void * restrict dst,
561 const struct GEN75_3DPRIMITIVE * restrict values)
562 {
563 uint32_t *dw = (uint32_t * restrict) dst;
564
565 dw[0] =
566 __gen_field(values->CommandType, 29, 31) |
567 __gen_field(values->CommandSubType, 27, 28) |
568 __gen_field(values->_3DCommandOpcode, 24, 26) |
569 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
570 __gen_field(values->IndirectParameterEnable, 10, 10) |
571 __gen_field(values->UAVCoherencyRequired, 9, 9) |
572 __gen_field(values->PredicateEnable, 8, 8) |
573 __gen_field(values->DwordLength, 0, 7) |
574 0;
575
576 dw[1] =
577 __gen_field(values->EndOffsetEnable, 9, 9) |
578 __gen_field(values->VertexAccessType, 8, 8) |
579 __gen_field(values->PrimitiveTopologyType, 0, 5) |
580 0;
581
582 dw[2] =
583 __gen_field(values->VertexCountPerInstance, 0, 31) |
584 0;
585
586 dw[3] =
587 __gen_field(values->StartVertexLocation, 0, 31) |
588 0;
589
590 dw[4] =
591 __gen_field(values->InstanceCount, 0, 31) |
592 0;
593
594 dw[5] =
595 __gen_field(values->StartInstanceLocation, 0, 31) |
596 0;
597
598 dw[6] =
599 __gen_field(values->BaseVertexLocation, 0, 31) |
600 0;
601
602 }
603
604 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_length 0x00000003
605 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_length_bias 0x00000002
606 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_header \
607 .CommandType = 3, \
608 .CommandSubType = 3, \
609 ._3DCommandOpcode = 1, \
610 ._3DCommandSubOpcode = 10, \
611 .DwordLength = 1
612
613 struct GEN75_3DSTATE_AA_LINE_PARAMETERS {
614 uint32_t CommandType;
615 uint32_t CommandSubType;
616 uint32_t _3DCommandOpcode;
617 uint32_t _3DCommandSubOpcode;
618 uint32_t DwordLength;
619 float AACoverageBias;
620 float AACoverageSlope;
621 float AACoverageEndCapBias;
622 float AACoverageEndCapSlope;
623 };
624
625 static inline void
626 GEN75_3DSTATE_AA_LINE_PARAMETERS_pack(__gen_user_data *data, void * restrict dst,
627 const struct GEN75_3DSTATE_AA_LINE_PARAMETERS * restrict values)
628 {
629 uint32_t *dw = (uint32_t * restrict) dst;
630
631 dw[0] =
632 __gen_field(values->CommandType, 29, 31) |
633 __gen_field(values->CommandSubType, 27, 28) |
634 __gen_field(values->_3DCommandOpcode, 24, 26) |
635 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
636 __gen_field(values->DwordLength, 0, 7) |
637 0;
638
639 dw[1] =
640 __gen_field(values->AACoverageBias * (1 << 8), 16, 23) |
641 __gen_field(values->AACoverageSlope * (1 << 8), 0, 7) |
642 0;
643
644 dw[2] =
645 __gen_field(values->AACoverageEndCapBias * (1 << 8), 16, 23) |
646 __gen_field(values->AACoverageEndCapSlope * (1 << 8), 0, 7) |
647 0;
648
649 }
650
651 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_length_bias 0x00000002
652 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_header\
653 .CommandType = 3, \
654 .CommandSubType = 3, \
655 ._3DCommandOpcode = 0, \
656 ._3DCommandSubOpcode = 70
657
658 struct GEN75_BINDING_TABLE_EDIT_ENTRY {
659 uint32_t BindingTableIndex;
660 uint32_t SurfaceStatePointer;
661 };
662
663 static inline void
664 GEN75_BINDING_TABLE_EDIT_ENTRY_pack(__gen_user_data *data, void * restrict dst,
665 const struct GEN75_BINDING_TABLE_EDIT_ENTRY * restrict values)
666 {
667 uint32_t *dw = (uint32_t * restrict) dst;
668
669 dw[0] =
670 __gen_field(values->BindingTableIndex, 16, 23) |
671 __gen_offset(values->SurfaceStatePointer, 0, 15) |
672 0;
673
674 }
675
676 struct GEN75_3DSTATE_BINDING_TABLE_EDIT_DS {
677 uint32_t CommandType;
678 uint32_t CommandSubType;
679 uint32_t _3DCommandOpcode;
680 uint32_t _3DCommandSubOpcode;
681 uint32_t DwordLength;
682 uint32_t BindingTableBlockClear;
683 #define AllCores 3
684 #define Core1 2
685 #define Core0 1
686 uint32_t BindingTableEditTarget;
687 /* variable length fields follow */
688 };
689
690 static inline void
691 GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_pack(__gen_user_data *data, void * restrict dst,
692 const struct GEN75_3DSTATE_BINDING_TABLE_EDIT_DS * restrict values)
693 {
694 uint32_t *dw = (uint32_t * restrict) dst;
695
696 dw[0] =
697 __gen_field(values->CommandType, 29, 31) |
698 __gen_field(values->CommandSubType, 27, 28) |
699 __gen_field(values->_3DCommandOpcode, 24, 26) |
700 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
701 __gen_field(values->DwordLength, 0, 8) |
702 0;
703
704 dw[1] =
705 __gen_field(values->BindingTableBlockClear, 16, 31) |
706 __gen_field(values->BindingTableEditTarget, 0, 1) |
707 0;
708
709 /* variable length fields follow */
710 }
711
712 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_length_bias 0x00000002
713 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_header\
714 .CommandType = 3, \
715 .CommandSubType = 3, \
716 ._3DCommandOpcode = 0, \
717 ._3DCommandSubOpcode = 68
718
719 struct GEN75_3DSTATE_BINDING_TABLE_EDIT_GS {
720 uint32_t CommandType;
721 uint32_t CommandSubType;
722 uint32_t _3DCommandOpcode;
723 uint32_t _3DCommandSubOpcode;
724 uint32_t DwordLength;
725 uint32_t BindingTableBlockClear;
726 #define AllCores 3
727 #define Core1 2
728 #define Core0 1
729 uint32_t BindingTableEditTarget;
730 /* variable length fields follow */
731 };
732
733 static inline void
734 GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_pack(__gen_user_data *data, void * restrict dst,
735 const struct GEN75_3DSTATE_BINDING_TABLE_EDIT_GS * restrict values)
736 {
737 uint32_t *dw = (uint32_t * restrict) dst;
738
739 dw[0] =
740 __gen_field(values->CommandType, 29, 31) |
741 __gen_field(values->CommandSubType, 27, 28) |
742 __gen_field(values->_3DCommandOpcode, 24, 26) |
743 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
744 __gen_field(values->DwordLength, 0, 8) |
745 0;
746
747 dw[1] =
748 __gen_field(values->BindingTableBlockClear, 16, 31) |
749 __gen_field(values->BindingTableEditTarget, 0, 1) |
750 0;
751
752 /* variable length fields follow */
753 }
754
755 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_length_bias 0x00000002
756 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_header\
757 .CommandType = 3, \
758 .CommandSubType = 3, \
759 ._3DCommandOpcode = 0, \
760 ._3DCommandSubOpcode = 69
761
762 struct GEN75_3DSTATE_BINDING_TABLE_EDIT_HS {
763 uint32_t CommandType;
764 uint32_t CommandSubType;
765 uint32_t _3DCommandOpcode;
766 uint32_t _3DCommandSubOpcode;
767 uint32_t DwordLength;
768 uint32_t BindingTableBlockClear;
769 #define AllCores 3
770 #define Core1 2
771 #define Core0 1
772 uint32_t BindingTableEditTarget;
773 /* variable length fields follow */
774 };
775
776 static inline void
777 GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_pack(__gen_user_data *data, void * restrict dst,
778 const struct GEN75_3DSTATE_BINDING_TABLE_EDIT_HS * restrict values)
779 {
780 uint32_t *dw = (uint32_t * restrict) dst;
781
782 dw[0] =
783 __gen_field(values->CommandType, 29, 31) |
784 __gen_field(values->CommandSubType, 27, 28) |
785 __gen_field(values->_3DCommandOpcode, 24, 26) |
786 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
787 __gen_field(values->DwordLength, 0, 8) |
788 0;
789
790 dw[1] =
791 __gen_field(values->BindingTableBlockClear, 16, 31) |
792 __gen_field(values->BindingTableEditTarget, 0, 1) |
793 0;
794
795 /* variable length fields follow */
796 }
797
798 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_length_bias 0x00000002
799 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_header\
800 .CommandType = 3, \
801 .CommandSubType = 3, \
802 ._3DCommandOpcode = 0, \
803 ._3DCommandSubOpcode = 71
804
805 struct GEN75_3DSTATE_BINDING_TABLE_EDIT_PS {
806 uint32_t CommandType;
807 uint32_t CommandSubType;
808 uint32_t _3DCommandOpcode;
809 uint32_t _3DCommandSubOpcode;
810 uint32_t DwordLength;
811 uint32_t BindingTableBlockClear;
812 #define AllCores 3
813 #define Core1 2
814 #define Core0 1
815 uint32_t BindingTableEditTarget;
816 /* variable length fields follow */
817 };
818
819 static inline void
820 GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_pack(__gen_user_data *data, void * restrict dst,
821 const struct GEN75_3DSTATE_BINDING_TABLE_EDIT_PS * restrict values)
822 {
823 uint32_t *dw = (uint32_t * restrict) dst;
824
825 dw[0] =
826 __gen_field(values->CommandType, 29, 31) |
827 __gen_field(values->CommandSubType, 27, 28) |
828 __gen_field(values->_3DCommandOpcode, 24, 26) |
829 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
830 __gen_field(values->DwordLength, 0, 8) |
831 0;
832
833 dw[1] =
834 __gen_field(values->BindingTableBlockClear, 16, 31) |
835 __gen_field(values->BindingTableEditTarget, 0, 1) |
836 0;
837
838 /* variable length fields follow */
839 }
840
841 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_length_bias 0x00000002
842 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_header\
843 .CommandType = 3, \
844 .CommandSubType = 3, \
845 ._3DCommandOpcode = 0, \
846 ._3DCommandSubOpcode = 67
847
848 struct GEN75_3DSTATE_BINDING_TABLE_EDIT_VS {
849 uint32_t CommandType;
850 uint32_t CommandSubType;
851 uint32_t _3DCommandOpcode;
852 uint32_t _3DCommandSubOpcode;
853 uint32_t DwordLength;
854 uint32_t BindingTableBlockClear;
855 #define AllCores 3
856 #define Core1 2
857 #define Core0 1
858 uint32_t BindingTableEditTarget;
859 /* variable length fields follow */
860 };
861
862 static inline void
863 GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_pack(__gen_user_data *data, void * restrict dst,
864 const struct GEN75_3DSTATE_BINDING_TABLE_EDIT_VS * restrict values)
865 {
866 uint32_t *dw = (uint32_t * restrict) dst;
867
868 dw[0] =
869 __gen_field(values->CommandType, 29, 31) |
870 __gen_field(values->CommandSubType, 27, 28) |
871 __gen_field(values->_3DCommandOpcode, 24, 26) |
872 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
873 __gen_field(values->DwordLength, 0, 8) |
874 0;
875
876 dw[1] =
877 __gen_field(values->BindingTableBlockClear, 16, 31) |
878 __gen_field(values->BindingTableEditTarget, 0, 1) |
879 0;
880
881 /* variable length fields follow */
882 }
883
884 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_length 0x00000002
885 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_length_bias 0x00000002
886 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_header\
887 .CommandType = 3, \
888 .CommandSubType = 3, \
889 ._3DCommandOpcode = 0, \
890 ._3DCommandSubOpcode = 40, \
891 .DwordLength = 0
892
893 struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS {
894 uint32_t CommandType;
895 uint32_t CommandSubType;
896 uint32_t _3DCommandOpcode;
897 uint32_t _3DCommandSubOpcode;
898 uint32_t DwordLength;
899 uint32_t PointertoDSBindingTable;
900 };
901
902 static inline void
903 GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_pack(__gen_user_data *data, void * restrict dst,
904 const struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS * restrict values)
905 {
906 uint32_t *dw = (uint32_t * restrict) dst;
907
908 dw[0] =
909 __gen_field(values->CommandType, 29, 31) |
910 __gen_field(values->CommandSubType, 27, 28) |
911 __gen_field(values->_3DCommandOpcode, 24, 26) |
912 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
913 __gen_field(values->DwordLength, 0, 7) |
914 0;
915
916 dw[1] =
917 __gen_offset(values->PointertoDSBindingTable, 5, 15) |
918 0;
919
920 }
921
922 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_length 0x00000002
923 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_length_bias 0x00000002
924 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_header\
925 .CommandType = 3, \
926 .CommandSubType = 3, \
927 ._3DCommandOpcode = 0, \
928 ._3DCommandSubOpcode = 41, \
929 .DwordLength = 0
930
931 struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS {
932 uint32_t CommandType;
933 uint32_t CommandSubType;
934 uint32_t _3DCommandOpcode;
935 uint32_t _3DCommandSubOpcode;
936 uint32_t DwordLength;
937 uint32_t PointertoGSBindingTable;
938 };
939
940 static inline void
941 GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_pack(__gen_user_data *data, void * restrict dst,
942 const struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS * restrict values)
943 {
944 uint32_t *dw = (uint32_t * restrict) dst;
945
946 dw[0] =
947 __gen_field(values->CommandType, 29, 31) |
948 __gen_field(values->CommandSubType, 27, 28) |
949 __gen_field(values->_3DCommandOpcode, 24, 26) |
950 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
951 __gen_field(values->DwordLength, 0, 7) |
952 0;
953
954 dw[1] =
955 __gen_offset(values->PointertoGSBindingTable, 5, 15) |
956 0;
957
958 }
959
960 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_length 0x00000002
961 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_length_bias 0x00000002
962 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_header\
963 .CommandType = 3, \
964 .CommandSubType = 3, \
965 ._3DCommandOpcode = 0, \
966 ._3DCommandSubOpcode = 39, \
967 .DwordLength = 0
968
969 struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS {
970 uint32_t CommandType;
971 uint32_t CommandSubType;
972 uint32_t _3DCommandOpcode;
973 uint32_t _3DCommandSubOpcode;
974 uint32_t DwordLength;
975 uint32_t PointertoHSBindingTable;
976 };
977
978 static inline void
979 GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_pack(__gen_user_data *data, void * restrict dst,
980 const struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS * restrict values)
981 {
982 uint32_t *dw = (uint32_t * restrict) dst;
983
984 dw[0] =
985 __gen_field(values->CommandType, 29, 31) |
986 __gen_field(values->CommandSubType, 27, 28) |
987 __gen_field(values->_3DCommandOpcode, 24, 26) |
988 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
989 __gen_field(values->DwordLength, 0, 7) |
990 0;
991
992 dw[1] =
993 __gen_offset(values->PointertoHSBindingTable, 5, 15) |
994 0;
995
996 }
997
998 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_length 0x00000002
999 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_length_bias 0x00000002
1000 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_header\
1001 .CommandType = 3, \
1002 .CommandSubType = 3, \
1003 ._3DCommandOpcode = 0, \
1004 ._3DCommandSubOpcode = 42, \
1005 .DwordLength = 0
1006
1007 struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS {
1008 uint32_t CommandType;
1009 uint32_t CommandSubType;
1010 uint32_t _3DCommandOpcode;
1011 uint32_t _3DCommandSubOpcode;
1012 uint32_t DwordLength;
1013 uint32_t PointertoPSBindingTable;
1014 };
1015
1016 static inline void
1017 GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_pack(__gen_user_data *data, void * restrict dst,
1018 const struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS * restrict values)
1019 {
1020 uint32_t *dw = (uint32_t * restrict) dst;
1021
1022 dw[0] =
1023 __gen_field(values->CommandType, 29, 31) |
1024 __gen_field(values->CommandSubType, 27, 28) |
1025 __gen_field(values->_3DCommandOpcode, 24, 26) |
1026 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1027 __gen_field(values->DwordLength, 0, 7) |
1028 0;
1029
1030 dw[1] =
1031 __gen_offset(values->PointertoPSBindingTable, 5, 15) |
1032 0;
1033
1034 }
1035
1036 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_length 0x00000002
1037 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_length_bias 0x00000002
1038 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_header\
1039 .CommandType = 3, \
1040 .CommandSubType = 3, \
1041 ._3DCommandOpcode = 0, \
1042 ._3DCommandSubOpcode = 38, \
1043 .DwordLength = 0
1044
1045 struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS {
1046 uint32_t CommandType;
1047 uint32_t CommandSubType;
1048 uint32_t _3DCommandOpcode;
1049 uint32_t _3DCommandSubOpcode;
1050 uint32_t DwordLength;
1051 uint32_t PointertoVSBindingTable;
1052 };
1053
1054 static inline void
1055 GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_pack(__gen_user_data *data, void * restrict dst,
1056 const struct GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS * restrict values)
1057 {
1058 uint32_t *dw = (uint32_t * restrict) dst;
1059
1060 dw[0] =
1061 __gen_field(values->CommandType, 29, 31) |
1062 __gen_field(values->CommandSubType, 27, 28) |
1063 __gen_field(values->_3DCommandOpcode, 24, 26) |
1064 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1065 __gen_field(values->DwordLength, 0, 7) |
1066 0;
1067
1068 dw[1] =
1069 __gen_offset(values->PointertoVSBindingTable, 5, 15) |
1070 0;
1071
1072 }
1073
1074 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 0x00000003
1075 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length_bias 0x00000002
1076 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_header\
1077 .CommandType = 3, \
1078 .CommandSubType = 3, \
1079 ._3DCommandOpcode = 1, \
1080 ._3DCommandSubOpcode = 25, \
1081 .DwordLength = 1
1082
1083 struct GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC {
1084 uint32_t CommandType;
1085 uint32_t CommandSubType;
1086 uint32_t _3DCommandOpcode;
1087 uint32_t _3DCommandSubOpcode;
1088 uint32_t DwordLength;
1089 __gen_address_type BindingTablePoolBaseAddress;
1090 uint32_t BindingTablePoolEnable;
1091 struct GEN75_MEMORY_OBJECT_CONTROL_STATE SurfaceObjectControlState;
1092 __gen_address_type BindingTablePoolUpperBound;
1093 };
1094
1095 static inline void
1096 GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_pack(__gen_user_data *data, void * restrict dst,
1097 const struct GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC * restrict values)
1098 {
1099 uint32_t *dw = (uint32_t * restrict) dst;
1100
1101 dw[0] =
1102 __gen_field(values->CommandType, 29, 31) |
1103 __gen_field(values->CommandSubType, 27, 28) |
1104 __gen_field(values->_3DCommandOpcode, 24, 26) |
1105 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1106 __gen_field(values->DwordLength, 0, 7) |
1107 0;
1108
1109 uint32_t dw_SurfaceObjectControlState;
1110 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_SurfaceObjectControlState, &values->SurfaceObjectControlState);
1111 uint32_t dw1 =
1112 __gen_field(values->BindingTablePoolEnable, 11, 11) |
1113 __gen_field(dw_SurfaceObjectControlState, 7, 10) |
1114 0;
1115
1116 dw[1] =
1117 __gen_combine_address(data, &dw[1], values->BindingTablePoolBaseAddress, dw1);
1118
1119 uint32_t dw2 =
1120 0;
1121
1122 dw[2] =
1123 __gen_combine_address(data, &dw[2], values->BindingTablePoolUpperBound, dw2);
1124
1125 }
1126
1127 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_length 0x00000002
1128 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_length_bias 0x00000002
1129 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_header\
1130 .CommandType = 3, \
1131 .CommandSubType = 3, \
1132 ._3DCommandOpcode = 0, \
1133 ._3DCommandSubOpcode = 36, \
1134 .DwordLength = 0
1135
1136 struct GEN75_3DSTATE_BLEND_STATE_POINTERS {
1137 uint32_t CommandType;
1138 uint32_t CommandSubType;
1139 uint32_t _3DCommandOpcode;
1140 uint32_t _3DCommandSubOpcode;
1141 uint32_t DwordLength;
1142 uint32_t BlendStatePointer;
1143 };
1144
1145 static inline void
1146 GEN75_3DSTATE_BLEND_STATE_POINTERS_pack(__gen_user_data *data, void * restrict dst,
1147 const struct GEN75_3DSTATE_BLEND_STATE_POINTERS * restrict values)
1148 {
1149 uint32_t *dw = (uint32_t * restrict) dst;
1150
1151 dw[0] =
1152 __gen_field(values->CommandType, 29, 31) |
1153 __gen_field(values->CommandSubType, 27, 28) |
1154 __gen_field(values->_3DCommandOpcode, 24, 26) |
1155 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1156 __gen_field(values->DwordLength, 0, 7) |
1157 0;
1158
1159 dw[1] =
1160 __gen_offset(values->BlendStatePointer, 6, 31) |
1161 0;
1162
1163 }
1164
1165 #define GEN75_3DSTATE_CC_STATE_POINTERS_length 0x00000002
1166 #define GEN75_3DSTATE_CC_STATE_POINTERS_length_bias 0x00000002
1167 #define GEN75_3DSTATE_CC_STATE_POINTERS_header \
1168 .CommandType = 3, \
1169 .CommandSubType = 3, \
1170 ._3DCommandOpcode = 0, \
1171 ._3DCommandSubOpcode = 14, \
1172 .DwordLength = 0
1173
1174 struct GEN75_3DSTATE_CC_STATE_POINTERS {
1175 uint32_t CommandType;
1176 uint32_t CommandSubType;
1177 uint32_t _3DCommandOpcode;
1178 uint32_t _3DCommandSubOpcode;
1179 uint32_t DwordLength;
1180 uint32_t ColorCalcStatePointer;
1181 };
1182
1183 static inline void
1184 GEN75_3DSTATE_CC_STATE_POINTERS_pack(__gen_user_data *data, void * restrict dst,
1185 const struct GEN75_3DSTATE_CC_STATE_POINTERS * restrict values)
1186 {
1187 uint32_t *dw = (uint32_t * restrict) dst;
1188
1189 dw[0] =
1190 __gen_field(values->CommandType, 29, 31) |
1191 __gen_field(values->CommandSubType, 27, 28) |
1192 __gen_field(values->_3DCommandOpcode, 24, 26) |
1193 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1194 __gen_field(values->DwordLength, 0, 7) |
1195 0;
1196
1197 dw[1] =
1198 __gen_offset(values->ColorCalcStatePointer, 6, 31) |
1199 0;
1200
1201 }
1202
1203 #define GEN75_3DSTATE_CHROMA_KEY_length 0x00000004
1204 #define GEN75_3DSTATE_CHROMA_KEY_length_bias 0x00000002
1205 #define GEN75_3DSTATE_CHROMA_KEY_header \
1206 .CommandType = 3, \
1207 .CommandSubType = 3, \
1208 ._3DCommandOpcode = 1, \
1209 ._3DCommandSubOpcode = 4, \
1210 .DwordLength = 2
1211
1212 struct GEN75_3DSTATE_CHROMA_KEY {
1213 uint32_t CommandType;
1214 uint32_t CommandSubType;
1215 uint32_t _3DCommandOpcode;
1216 uint32_t _3DCommandSubOpcode;
1217 uint32_t DwordLength;
1218 uint32_t ChromaKeyTableIndex;
1219 uint32_t ChromaKeyLowValue;
1220 uint32_t ChromaKeyHighValue;
1221 };
1222
1223 static inline void
1224 GEN75_3DSTATE_CHROMA_KEY_pack(__gen_user_data *data, void * restrict dst,
1225 const struct GEN75_3DSTATE_CHROMA_KEY * restrict values)
1226 {
1227 uint32_t *dw = (uint32_t * restrict) dst;
1228
1229 dw[0] =
1230 __gen_field(values->CommandType, 29, 31) |
1231 __gen_field(values->CommandSubType, 27, 28) |
1232 __gen_field(values->_3DCommandOpcode, 24, 26) |
1233 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1234 __gen_field(values->DwordLength, 0, 7) |
1235 0;
1236
1237 dw[1] =
1238 __gen_field(values->ChromaKeyTableIndex, 30, 31) |
1239 0;
1240
1241 dw[2] =
1242 __gen_field(values->ChromaKeyLowValue, 0, 31) |
1243 0;
1244
1245 dw[3] =
1246 __gen_field(values->ChromaKeyHighValue, 0, 31) |
1247 0;
1248
1249 }
1250
1251 #define GEN75_3DSTATE_CLEAR_PARAMS_length 0x00000003
1252 #define GEN75_3DSTATE_CLEAR_PARAMS_length_bias 0x00000002
1253 #define GEN75_3DSTATE_CLEAR_PARAMS_header \
1254 .CommandType = 3, \
1255 .CommandSubType = 3, \
1256 ._3DCommandOpcode = 0, \
1257 ._3DCommandSubOpcode = 4, \
1258 .DwordLength = 1
1259
1260 struct GEN75_3DSTATE_CLEAR_PARAMS {
1261 uint32_t CommandType;
1262 uint32_t CommandSubType;
1263 uint32_t _3DCommandOpcode;
1264 uint32_t _3DCommandSubOpcode;
1265 uint32_t DwordLength;
1266 uint32_t DepthClearValue;
1267 uint32_t DepthClearValueValid;
1268 };
1269
1270 static inline void
1271 GEN75_3DSTATE_CLEAR_PARAMS_pack(__gen_user_data *data, void * restrict dst,
1272 const struct GEN75_3DSTATE_CLEAR_PARAMS * restrict values)
1273 {
1274 uint32_t *dw = (uint32_t * restrict) dst;
1275
1276 dw[0] =
1277 __gen_field(values->CommandType, 29, 31) |
1278 __gen_field(values->CommandSubType, 27, 28) |
1279 __gen_field(values->_3DCommandOpcode, 24, 26) |
1280 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1281 __gen_field(values->DwordLength, 0, 7) |
1282 0;
1283
1284 dw[1] =
1285 __gen_field(values->DepthClearValue, 0, 31) |
1286 0;
1287
1288 dw[2] =
1289 __gen_field(values->DepthClearValueValid, 0, 0) |
1290 0;
1291
1292 }
1293
1294 #define GEN75_3DSTATE_CLIP_length 0x00000004
1295 #define GEN75_3DSTATE_CLIP_length_bias 0x00000002
1296 #define GEN75_3DSTATE_CLIP_header \
1297 .CommandType = 3, \
1298 .CommandSubType = 3, \
1299 ._3DCommandOpcode = 0, \
1300 ._3DCommandSubOpcode = 18, \
1301 .DwordLength = 2
1302
1303 struct GEN75_3DSTATE_CLIP {
1304 uint32_t CommandType;
1305 uint32_t CommandSubType;
1306 uint32_t _3DCommandOpcode;
1307 uint32_t _3DCommandSubOpcode;
1308 uint32_t DwordLength;
1309 uint32_t FrontWinding;
1310 uint32_t VertexSubPixelPrecisionSelect;
1311 uint32_t EarlyCullEnable;
1312 #define CULLMODE_BOTH 0
1313 #define CULLMODE_NONE 1
1314 #define CULLMODE_FRONT 2
1315 #define CULLMODE_BACK 3
1316 uint32_t CullMode;
1317 uint32_t ClipperStatisticsEnable;
1318 uint32_t UserClipDistanceCullTestEnableBitmask;
1319 uint32_t ClipEnable;
1320 #define APIMODE_OGL 0
1321 uint32_t APIMode;
1322 uint32_t ViewportXYClipTestEnable;
1323 uint32_t ViewportZClipTestEnable;
1324 uint32_t GuardbandClipTestEnable;
1325 uint32_t UserClipDistanceClipTestEnableBitmask;
1326 #define CLIPMODE_NORMAL 0
1327 #define CLIPMODE_REJECT_ALL 3
1328 #define CLIPMODE_ACCEPT_ALL 4
1329 uint32_t ClipMode;
1330 uint32_t PerspectiveDivideDisable;
1331 uint32_t NonPerspectiveBarycentricEnable;
1332 #define Vertex0 0
1333 #define Vertex1 1
1334 #define Vertex2 2
1335 uint32_t TriangleStripListProvokingVertexSelect;
1336 #define Vertex0 0
1337 #define Vertex1 1
1338 uint32_t LineStripListProvokingVertexSelect;
1339 #define Vertex0 0
1340 #define Vertex1 1
1341 #define Vertex2 2
1342 uint32_t TriangleFanProvokingVertexSelect;
1343 float MinimumPointWidth;
1344 float MaximumPointWidth;
1345 uint32_t ForceZeroRTAIndexEnable;
1346 uint32_t MaximumVPIndex;
1347 };
1348
1349 static inline void
1350 GEN75_3DSTATE_CLIP_pack(__gen_user_data *data, void * restrict dst,
1351 const struct GEN75_3DSTATE_CLIP * restrict values)
1352 {
1353 uint32_t *dw = (uint32_t * restrict) dst;
1354
1355 dw[0] =
1356 __gen_field(values->CommandType, 29, 31) |
1357 __gen_field(values->CommandSubType, 27, 28) |
1358 __gen_field(values->_3DCommandOpcode, 24, 26) |
1359 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1360 __gen_field(values->DwordLength, 0, 7) |
1361 0;
1362
1363 dw[1] =
1364 __gen_field(values->FrontWinding, 20, 20) |
1365 __gen_field(values->VertexSubPixelPrecisionSelect, 19, 19) |
1366 __gen_field(values->EarlyCullEnable, 18, 18) |
1367 __gen_field(values->CullMode, 16, 17) |
1368 __gen_field(values->ClipperStatisticsEnable, 10, 10) |
1369 __gen_field(values->UserClipDistanceCullTestEnableBitmask, 0, 7) |
1370 0;
1371
1372 dw[2] =
1373 __gen_field(values->ClipEnable, 31, 31) |
1374 __gen_field(values->APIMode, 30, 30) |
1375 __gen_field(values->ViewportXYClipTestEnable, 28, 28) |
1376 __gen_field(values->ViewportZClipTestEnable, 27, 27) |
1377 __gen_field(values->GuardbandClipTestEnable, 26, 26) |
1378 __gen_field(values->UserClipDistanceClipTestEnableBitmask, 16, 23) |
1379 __gen_field(values->ClipMode, 13, 15) |
1380 __gen_field(values->PerspectiveDivideDisable, 9, 9) |
1381 __gen_field(values->NonPerspectiveBarycentricEnable, 8, 8) |
1382 __gen_field(values->TriangleStripListProvokingVertexSelect, 4, 5) |
1383 __gen_field(values->LineStripListProvokingVertexSelect, 2, 3) |
1384 __gen_field(values->TriangleFanProvokingVertexSelect, 0, 1) |
1385 0;
1386
1387 dw[3] =
1388 __gen_field(values->MinimumPointWidth * (1 << 3), 17, 27) |
1389 __gen_field(values->MaximumPointWidth * (1 << 3), 6, 16) |
1390 __gen_field(values->ForceZeroRTAIndexEnable, 5, 5) |
1391 __gen_field(values->MaximumVPIndex, 0, 3) |
1392 0;
1393
1394 }
1395
1396 #define GEN75_3DSTATE_CONSTANT_DS_length 0x00000007
1397 #define GEN75_3DSTATE_CONSTANT_DS_length_bias 0x00000002
1398 #define GEN75_3DSTATE_CONSTANT_DS_header \
1399 .CommandType = 3, \
1400 .CommandSubType = 3, \
1401 ._3DCommandOpcode = 0, \
1402 ._3DCommandSubOpcode = 26, \
1403 .DwordLength = 5
1404
1405 struct GEN75_3DSTATE_CONSTANT_BODY {
1406 uint32_t ConstantBuffer1ReadLength;
1407 uint32_t ConstantBuffer0ReadLength;
1408 uint32_t ConstantBuffer3ReadLength;
1409 uint32_t ConstantBuffer2ReadLength;
1410 __gen_address_type PointerToConstantBuffer0;
1411 struct GEN75_MEMORY_OBJECT_CONTROL_STATE ConstantBufferObjectControlState;
1412 __gen_address_type PointerToConstantBuffer1;
1413 __gen_address_type PointerToConstantBuffer2;
1414 __gen_address_type PointerToConstantBuffer3;
1415 };
1416
1417 static inline void
1418 GEN75_3DSTATE_CONSTANT_BODY_pack(__gen_user_data *data, void * restrict dst,
1419 const struct GEN75_3DSTATE_CONSTANT_BODY * restrict values)
1420 {
1421 uint32_t *dw = (uint32_t * restrict) dst;
1422
1423 dw[0] =
1424 __gen_field(values->ConstantBuffer1ReadLength, 16, 31) |
1425 __gen_field(values->ConstantBuffer0ReadLength, 0, 15) |
1426 0;
1427
1428 dw[1] =
1429 __gen_field(values->ConstantBuffer3ReadLength, 16, 31) |
1430 __gen_field(values->ConstantBuffer2ReadLength, 0, 15) |
1431 0;
1432
1433 uint32_t dw_ConstantBufferObjectControlState;
1434 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_ConstantBufferObjectControlState, &values->ConstantBufferObjectControlState);
1435 uint32_t dw2 =
1436 __gen_field(dw_ConstantBufferObjectControlState, 0, 4) |
1437 0;
1438
1439 dw[2] =
1440 __gen_combine_address(data, &dw[2], values->PointerToConstantBuffer0, dw2);
1441
1442 uint32_t dw3 =
1443 0;
1444
1445 dw[3] =
1446 __gen_combine_address(data, &dw[3], values->PointerToConstantBuffer1, dw3);
1447
1448 uint32_t dw4 =
1449 0;
1450
1451 dw[4] =
1452 __gen_combine_address(data, &dw[4], values->PointerToConstantBuffer2, dw4);
1453
1454 uint32_t dw5 =
1455 0;
1456
1457 dw[5] =
1458 __gen_combine_address(data, &dw[5], values->PointerToConstantBuffer3, dw5);
1459
1460 }
1461
1462 struct GEN75_3DSTATE_CONSTANT_DS {
1463 uint32_t CommandType;
1464 uint32_t CommandSubType;
1465 uint32_t _3DCommandOpcode;
1466 uint32_t _3DCommandSubOpcode;
1467 uint32_t DwordLength;
1468 struct GEN75_3DSTATE_CONSTANT_BODY ConstantBody;
1469 };
1470
1471 static inline void
1472 GEN75_3DSTATE_CONSTANT_DS_pack(__gen_user_data *data, void * restrict dst,
1473 const struct GEN75_3DSTATE_CONSTANT_DS * restrict values)
1474 {
1475 uint32_t *dw = (uint32_t * restrict) dst;
1476
1477 dw[0] =
1478 __gen_field(values->CommandType, 29, 31) |
1479 __gen_field(values->CommandSubType, 27, 28) |
1480 __gen_field(values->_3DCommandOpcode, 24, 26) |
1481 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1482 __gen_field(values->DwordLength, 0, 7) |
1483 0;
1484
1485 GEN75_3DSTATE_CONSTANT_BODY_pack(data, &dw[1], &values->ConstantBody);
1486 }
1487
1488 #define GEN75_3DSTATE_CONSTANT_GS_length 0x00000007
1489 #define GEN75_3DSTATE_CONSTANT_GS_length_bias 0x00000002
1490 #define GEN75_3DSTATE_CONSTANT_GS_header \
1491 .CommandType = 3, \
1492 .CommandSubType = 3, \
1493 ._3DCommandOpcode = 0, \
1494 ._3DCommandSubOpcode = 22, \
1495 .DwordLength = 5
1496
1497 struct GEN75_3DSTATE_CONSTANT_GS {
1498 uint32_t CommandType;
1499 uint32_t CommandSubType;
1500 uint32_t _3DCommandOpcode;
1501 uint32_t _3DCommandSubOpcode;
1502 uint32_t DwordLength;
1503 struct GEN75_3DSTATE_CONSTANT_BODY ConstantBody;
1504 };
1505
1506 static inline void
1507 GEN75_3DSTATE_CONSTANT_GS_pack(__gen_user_data *data, void * restrict dst,
1508 const struct GEN75_3DSTATE_CONSTANT_GS * restrict values)
1509 {
1510 uint32_t *dw = (uint32_t * restrict) dst;
1511
1512 dw[0] =
1513 __gen_field(values->CommandType, 29, 31) |
1514 __gen_field(values->CommandSubType, 27, 28) |
1515 __gen_field(values->_3DCommandOpcode, 24, 26) |
1516 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1517 __gen_field(values->DwordLength, 0, 7) |
1518 0;
1519
1520 GEN75_3DSTATE_CONSTANT_BODY_pack(data, &dw[1], &values->ConstantBody);
1521 }
1522
1523 #define GEN75_3DSTATE_CONSTANT_HS_length 0x00000007
1524 #define GEN75_3DSTATE_CONSTANT_HS_length_bias 0x00000002
1525 #define GEN75_3DSTATE_CONSTANT_HS_header \
1526 .CommandType = 3, \
1527 .CommandSubType = 3, \
1528 ._3DCommandOpcode = 0, \
1529 ._3DCommandSubOpcode = 25, \
1530 .DwordLength = 5
1531
1532 struct GEN75_3DSTATE_CONSTANT_HS {
1533 uint32_t CommandType;
1534 uint32_t CommandSubType;
1535 uint32_t _3DCommandOpcode;
1536 uint32_t _3DCommandSubOpcode;
1537 uint32_t DwordLength;
1538 struct GEN75_3DSTATE_CONSTANT_BODY ConstantBody;
1539 };
1540
1541 static inline void
1542 GEN75_3DSTATE_CONSTANT_HS_pack(__gen_user_data *data, void * restrict dst,
1543 const struct GEN75_3DSTATE_CONSTANT_HS * restrict values)
1544 {
1545 uint32_t *dw = (uint32_t * restrict) dst;
1546
1547 dw[0] =
1548 __gen_field(values->CommandType, 29, 31) |
1549 __gen_field(values->CommandSubType, 27, 28) |
1550 __gen_field(values->_3DCommandOpcode, 24, 26) |
1551 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1552 __gen_field(values->DwordLength, 0, 7) |
1553 0;
1554
1555 GEN75_3DSTATE_CONSTANT_BODY_pack(data, &dw[1], &values->ConstantBody);
1556 }
1557
1558 #define GEN75_3DSTATE_CONSTANT_PS_length 0x00000007
1559 #define GEN75_3DSTATE_CONSTANT_PS_length_bias 0x00000002
1560 #define GEN75_3DSTATE_CONSTANT_PS_header \
1561 .CommandType = 3, \
1562 .CommandSubType = 3, \
1563 ._3DCommandOpcode = 0, \
1564 ._3DCommandSubOpcode = 23, \
1565 .DwordLength = 5
1566
1567 struct GEN75_3DSTATE_CONSTANT_PS {
1568 uint32_t CommandType;
1569 uint32_t CommandSubType;
1570 uint32_t _3DCommandOpcode;
1571 uint32_t _3DCommandSubOpcode;
1572 uint32_t DwordLength;
1573 struct GEN75_3DSTATE_CONSTANT_BODY ConstantBody;
1574 };
1575
1576 static inline void
1577 GEN75_3DSTATE_CONSTANT_PS_pack(__gen_user_data *data, void * restrict dst,
1578 const struct GEN75_3DSTATE_CONSTANT_PS * restrict values)
1579 {
1580 uint32_t *dw = (uint32_t * restrict) dst;
1581
1582 dw[0] =
1583 __gen_field(values->CommandType, 29, 31) |
1584 __gen_field(values->CommandSubType, 27, 28) |
1585 __gen_field(values->_3DCommandOpcode, 24, 26) |
1586 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1587 __gen_field(values->DwordLength, 0, 7) |
1588 0;
1589
1590 GEN75_3DSTATE_CONSTANT_BODY_pack(data, &dw[1], &values->ConstantBody);
1591 }
1592
1593 #define GEN75_3DSTATE_CONSTANT_VS_length 0x00000007
1594 #define GEN75_3DSTATE_CONSTANT_VS_length_bias 0x00000002
1595 #define GEN75_3DSTATE_CONSTANT_VS_header \
1596 .CommandType = 3, \
1597 .CommandSubType = 3, \
1598 ._3DCommandOpcode = 0, \
1599 ._3DCommandSubOpcode = 21, \
1600 .DwordLength = 5
1601
1602 struct GEN75_3DSTATE_CONSTANT_VS {
1603 uint32_t CommandType;
1604 uint32_t CommandSubType;
1605 uint32_t _3DCommandOpcode;
1606 uint32_t _3DCommandSubOpcode;
1607 uint32_t DwordLength;
1608 struct GEN75_3DSTATE_CONSTANT_BODY ConstantBody;
1609 };
1610
1611 static inline void
1612 GEN75_3DSTATE_CONSTANT_VS_pack(__gen_user_data *data, void * restrict dst,
1613 const struct GEN75_3DSTATE_CONSTANT_VS * restrict values)
1614 {
1615 uint32_t *dw = (uint32_t * restrict) dst;
1616
1617 dw[0] =
1618 __gen_field(values->CommandType, 29, 31) |
1619 __gen_field(values->CommandSubType, 27, 28) |
1620 __gen_field(values->_3DCommandOpcode, 24, 26) |
1621 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1622 __gen_field(values->DwordLength, 0, 7) |
1623 0;
1624
1625 GEN75_3DSTATE_CONSTANT_BODY_pack(data, &dw[1], &values->ConstantBody);
1626 }
1627
1628 #define GEN75_3DSTATE_DEPTH_BUFFER_length 0x00000007
1629 #define GEN75_3DSTATE_DEPTH_BUFFER_length_bias 0x00000002
1630 #define GEN75_3DSTATE_DEPTH_BUFFER_header \
1631 .CommandType = 3, \
1632 .CommandSubType = 3, \
1633 ._3DCommandOpcode = 0, \
1634 ._3DCommandSubOpcode = 5, \
1635 .DwordLength = 5
1636
1637 struct GEN75_3DSTATE_DEPTH_BUFFER {
1638 uint32_t CommandType;
1639 uint32_t CommandSubType;
1640 uint32_t _3DCommandOpcode;
1641 uint32_t _3DCommandSubOpcode;
1642 uint32_t DwordLength;
1643 #define SURFTYPE_1D 0
1644 #define SURFTYPE_2D 1
1645 #define SURFTYPE_3D 2
1646 #define SURFTYPE_CUBE 3
1647 #define SURFTYPE_NULL 7
1648 uint32_t SurfaceType;
1649 uint32_t DepthWriteEnable;
1650 uint32_t StencilWriteEnable;
1651 uint32_t HierarchicalDepthBufferEnable;
1652 #define D32_FLOAT 1
1653 #define D24_UNORM_X8_UINT 3
1654 #define D16_UNORM 5
1655 uint32_t SurfaceFormat;
1656 uint32_t SurfacePitch;
1657 __gen_address_type SurfaceBaseAddress;
1658 uint32_t Height;
1659 uint32_t Width;
1660 uint32_t LOD;
1661 #define SURFTYPE_CUBEmustbezero 0
1662 uint32_t Depth;
1663 uint32_t MinimumArrayElement;
1664 struct GEN75_MEMORY_OBJECT_CONTROL_STATE DepthBufferObjectControlState;
1665 uint32_t DepthCoordinateOffsetY;
1666 uint32_t DepthCoordinateOffsetX;
1667 uint32_t RenderTargetViewExtent;
1668 };
1669
1670 static inline void
1671 GEN75_3DSTATE_DEPTH_BUFFER_pack(__gen_user_data *data, void * restrict dst,
1672 const struct GEN75_3DSTATE_DEPTH_BUFFER * restrict values)
1673 {
1674 uint32_t *dw = (uint32_t * restrict) dst;
1675
1676 dw[0] =
1677 __gen_field(values->CommandType, 29, 31) |
1678 __gen_field(values->CommandSubType, 27, 28) |
1679 __gen_field(values->_3DCommandOpcode, 24, 26) |
1680 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1681 __gen_field(values->DwordLength, 0, 7) |
1682 0;
1683
1684 dw[1] =
1685 __gen_field(values->SurfaceType, 29, 31) |
1686 __gen_field(values->DepthWriteEnable, 28, 28) |
1687 __gen_field(values->StencilWriteEnable, 27, 27) |
1688 __gen_field(values->HierarchicalDepthBufferEnable, 22, 22) |
1689 __gen_field(values->SurfaceFormat, 18, 20) |
1690 __gen_field(values->SurfacePitch, 0, 17) |
1691 0;
1692
1693 uint32_t dw2 =
1694 0;
1695
1696 dw[2] =
1697 __gen_combine_address(data, &dw[2], values->SurfaceBaseAddress, dw2);
1698
1699 dw[3] =
1700 __gen_field(values->Height, 18, 31) |
1701 __gen_field(values->Width, 4, 17) |
1702 __gen_field(values->LOD, 0, 3) |
1703 0;
1704
1705 uint32_t dw_DepthBufferObjectControlState;
1706 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_DepthBufferObjectControlState, &values->DepthBufferObjectControlState);
1707 dw[4] =
1708 __gen_field(values->Depth, 21, 31) |
1709 __gen_field(values->MinimumArrayElement, 10, 20) |
1710 __gen_field(dw_DepthBufferObjectControlState, 0, 3) |
1711 0;
1712
1713 dw[5] =
1714 __gen_field(values->DepthCoordinateOffsetY, 16, 31) |
1715 __gen_field(values->DepthCoordinateOffsetX, 0, 15) |
1716 0;
1717
1718 dw[6] =
1719 __gen_field(values->RenderTargetViewExtent, 21, 31) |
1720 0;
1721
1722 }
1723
1724 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 0x00000002
1725 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length_bias 0x00000002
1726 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_header\
1727 .CommandType = 3, \
1728 .CommandSubType = 3, \
1729 ._3DCommandOpcode = 0, \
1730 ._3DCommandSubOpcode = 37, \
1731 .DwordLength = 0
1732
1733 struct GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS {
1734 uint32_t CommandType;
1735 uint32_t CommandSubType;
1736 uint32_t _3DCommandOpcode;
1737 uint32_t _3DCommandSubOpcode;
1738 uint32_t DwordLength;
1739 uint32_t PointertoDEPTH_STENCIL_STATE;
1740 };
1741
1742 static inline void
1743 GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_pack(__gen_user_data *data, void * restrict dst,
1744 const struct GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS * restrict values)
1745 {
1746 uint32_t *dw = (uint32_t * restrict) dst;
1747
1748 dw[0] =
1749 __gen_field(values->CommandType, 29, 31) |
1750 __gen_field(values->CommandSubType, 27, 28) |
1751 __gen_field(values->_3DCommandOpcode, 24, 26) |
1752 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1753 __gen_field(values->DwordLength, 0, 7) |
1754 0;
1755
1756 dw[1] =
1757 __gen_offset(values->PointertoDEPTH_STENCIL_STATE, 6, 31) |
1758 0;
1759
1760 }
1761
1762 #define GEN75_3DSTATE_DRAWING_RECTANGLE_length 0x00000004
1763 #define GEN75_3DSTATE_DRAWING_RECTANGLE_length_bias 0x00000002
1764 #define GEN75_3DSTATE_DRAWING_RECTANGLE_header \
1765 .CommandType = 3, \
1766 .CommandSubType = 3, \
1767 ._3DCommandOpcode = 1, \
1768 ._3DCommandSubOpcode = 0, \
1769 .DwordLength = 2
1770
1771 struct GEN75_3DSTATE_DRAWING_RECTANGLE {
1772 uint32_t CommandType;
1773 uint32_t CommandSubType;
1774 uint32_t _3DCommandOpcode;
1775 uint32_t _3DCommandSubOpcode;
1776 #define Legacy 0
1777 #define Core0Enabled 1
1778 #define Core1Enabled 2
1779 uint32_t CoreModeSelect;
1780 uint32_t DwordLength;
1781 uint32_t ClippedDrawingRectangleYMin;
1782 uint32_t ClippedDrawingRectangleXMin;
1783 uint32_t ClippedDrawingRectangleYMax;
1784 uint32_t ClippedDrawingRectangleXMax;
1785 uint32_t DrawingRectangleOriginY;
1786 uint32_t DrawingRectangleOriginX;
1787 };
1788
1789 static inline void
1790 GEN75_3DSTATE_DRAWING_RECTANGLE_pack(__gen_user_data *data, void * restrict dst,
1791 const struct GEN75_3DSTATE_DRAWING_RECTANGLE * restrict values)
1792 {
1793 uint32_t *dw = (uint32_t * restrict) dst;
1794
1795 dw[0] =
1796 __gen_field(values->CommandType, 29, 31) |
1797 __gen_field(values->CommandSubType, 27, 28) |
1798 __gen_field(values->_3DCommandOpcode, 24, 26) |
1799 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1800 __gen_field(values->CoreModeSelect, 14, 15) |
1801 __gen_field(values->DwordLength, 0, 7) |
1802 0;
1803
1804 dw[1] =
1805 __gen_field(values->ClippedDrawingRectangleYMin, 16, 31) |
1806 __gen_field(values->ClippedDrawingRectangleXMin, 0, 15) |
1807 0;
1808
1809 dw[2] =
1810 __gen_field(values->ClippedDrawingRectangleYMax, 16, 31) |
1811 __gen_field(values->ClippedDrawingRectangleXMax, 0, 15) |
1812 0;
1813
1814 dw[3] =
1815 __gen_field(values->DrawingRectangleOriginY, 16, 31) |
1816 __gen_field(values->DrawingRectangleOriginX, 0, 15) |
1817 0;
1818
1819 }
1820
1821 #define GEN75_3DSTATE_DS_length 0x00000006
1822 #define GEN75_3DSTATE_DS_length_bias 0x00000002
1823 #define GEN75_3DSTATE_DS_header \
1824 .CommandType = 3, \
1825 .CommandSubType = 3, \
1826 ._3DCommandOpcode = 0, \
1827 ._3DCommandSubOpcode = 29, \
1828 .DwordLength = 4
1829
1830 struct GEN75_3DSTATE_DS {
1831 uint32_t CommandType;
1832 uint32_t CommandSubType;
1833 uint32_t _3DCommandOpcode;
1834 uint32_t _3DCommandSubOpcode;
1835 uint32_t DwordLength;
1836 uint32_t KernelStartPointer;
1837 #define Multiple 0
1838 #define Single 1
1839 uint32_t SingleDomainPointDispatch;
1840 #define Dmask 0
1841 #define Vmask 1
1842 uint32_t VectorMaskEnable;
1843 #define NoSamplers 0
1844 #define _14Samplers 1
1845 #define _58Samplers 2
1846 #define _912Samplers 3
1847 #define _1316Samplers 4
1848 uint32_t SamplerCount;
1849 uint32_t BindingTableEntryCount;
1850 #define Normal 0
1851 #define High 1
1852 uint32_t ThreadDispatchPriority;
1853 #define IEEE754 0
1854 #define Alternate 1
1855 uint32_t FloatingPointMode;
1856 uint32_t AccessesUAV;
1857 uint32_t IllegalOpcodeExceptionEnable;
1858 uint32_t SoftwareExceptionEnable;
1859 uint32_t ScratchSpaceBasePointer;
1860 uint32_t PerThreadScratchSpace;
1861 uint32_t DispatchGRFStartRegisterForURBData;
1862 uint32_t PatchURBEntryReadLength;
1863 uint32_t PatchURBEntryReadOffset;
1864 uint32_t MaximumNumberofThreads;
1865 uint32_t StatisticsEnable;
1866 uint32_t ComputeWCoordinateEnable;
1867 uint32_t DSCacheDisable;
1868 uint32_t DSFunctionEnable;
1869 };
1870
1871 static inline void
1872 GEN75_3DSTATE_DS_pack(__gen_user_data *data, void * restrict dst,
1873 const struct GEN75_3DSTATE_DS * restrict values)
1874 {
1875 uint32_t *dw = (uint32_t * restrict) dst;
1876
1877 dw[0] =
1878 __gen_field(values->CommandType, 29, 31) |
1879 __gen_field(values->CommandSubType, 27, 28) |
1880 __gen_field(values->_3DCommandOpcode, 24, 26) |
1881 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1882 __gen_field(values->DwordLength, 0, 7) |
1883 0;
1884
1885 dw[1] =
1886 __gen_offset(values->KernelStartPointer, 6, 31) |
1887 0;
1888
1889 dw[2] =
1890 __gen_field(values->SingleDomainPointDispatch, 31, 31) |
1891 __gen_field(values->VectorMaskEnable, 30, 30) |
1892 __gen_field(values->SamplerCount, 27, 29) |
1893 __gen_field(values->BindingTableEntryCount, 18, 25) |
1894 __gen_field(values->ThreadDispatchPriority, 17, 17) |
1895 __gen_field(values->FloatingPointMode, 16, 16) |
1896 __gen_field(values->AccessesUAV, 14, 14) |
1897 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
1898 __gen_field(values->SoftwareExceptionEnable, 7, 7) |
1899 0;
1900
1901 dw[3] =
1902 __gen_offset(values->ScratchSpaceBasePointer, 10, 31) |
1903 __gen_field(values->PerThreadScratchSpace, 0, 3) |
1904 0;
1905
1906 dw[4] =
1907 __gen_field(values->DispatchGRFStartRegisterForURBData, 20, 24) |
1908 __gen_field(values->PatchURBEntryReadLength, 11, 17) |
1909 __gen_field(values->PatchURBEntryReadOffset, 4, 9) |
1910 0;
1911
1912 dw[5] =
1913 __gen_field(values->MaximumNumberofThreads, 21, 29) |
1914 __gen_field(values->StatisticsEnable, 10, 10) |
1915 __gen_field(values->ComputeWCoordinateEnable, 2, 2) |
1916 __gen_field(values->DSCacheDisable, 1, 1) |
1917 __gen_field(values->DSFunctionEnable, 0, 0) |
1918 0;
1919
1920 }
1921
1922 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_length_bias 0x00000002
1923 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_header \
1924 .CommandType = 3, \
1925 .CommandSubType = 3, \
1926 ._3DCommandOpcode = 0, \
1927 ._3DCommandSubOpcode = 55
1928
1929 struct GEN75_GATHER_CONSTANT_ENTRY {
1930 uint32_t ConstantBufferOffset;
1931 uint32_t ChannelMask;
1932 uint32_t BindingTableIndexOffset;
1933 };
1934
1935 static inline void
1936 GEN75_GATHER_CONSTANT_ENTRY_pack(__gen_user_data *data, void * restrict dst,
1937 const struct GEN75_GATHER_CONSTANT_ENTRY * restrict values)
1938 {
1939 uint32_t *dw = (uint32_t * restrict) dst;
1940
1941 dw[0] =
1942 __gen_offset(values->ConstantBufferOffset, 8, 15) |
1943 __gen_field(values->ChannelMask, 4, 7) |
1944 __gen_field(values->BindingTableIndexOffset, 0, 3) |
1945 0;
1946
1947 }
1948
1949 struct GEN75_3DSTATE_GATHER_CONSTANT_DS {
1950 uint32_t CommandType;
1951 uint32_t CommandSubType;
1952 uint32_t _3DCommandOpcode;
1953 uint32_t _3DCommandSubOpcode;
1954 uint32_t DwordLength;
1955 uint32_t ConstantBufferValid;
1956 uint32_t ConstantBufferBindingTableBlock;
1957 uint32_t GatherBufferOffset;
1958 /* variable length fields follow */
1959 };
1960
1961 static inline void
1962 GEN75_3DSTATE_GATHER_CONSTANT_DS_pack(__gen_user_data *data, void * restrict dst,
1963 const struct GEN75_3DSTATE_GATHER_CONSTANT_DS * restrict values)
1964 {
1965 uint32_t *dw = (uint32_t * restrict) dst;
1966
1967 dw[0] =
1968 __gen_field(values->CommandType, 29, 31) |
1969 __gen_field(values->CommandSubType, 27, 28) |
1970 __gen_field(values->_3DCommandOpcode, 24, 26) |
1971 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
1972 __gen_field(values->DwordLength, 0, 7) |
1973 0;
1974
1975 dw[1] =
1976 __gen_field(values->ConstantBufferValid, 16, 31) |
1977 __gen_field(values->ConstantBufferBindingTableBlock, 12, 15) |
1978 0;
1979
1980 dw[2] =
1981 __gen_offset(values->GatherBufferOffset, 6, 22) |
1982 0;
1983
1984 /* variable length fields follow */
1985 }
1986
1987 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_length_bias 0x00000002
1988 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_header \
1989 .CommandType = 3, \
1990 .CommandSubType = 3, \
1991 ._3DCommandOpcode = 0, \
1992 ._3DCommandSubOpcode = 53
1993
1994 struct GEN75_3DSTATE_GATHER_CONSTANT_GS {
1995 uint32_t CommandType;
1996 uint32_t CommandSubType;
1997 uint32_t _3DCommandOpcode;
1998 uint32_t _3DCommandSubOpcode;
1999 uint32_t DwordLength;
2000 uint32_t ConstantBufferValid;
2001 uint32_t ConstantBufferBindingTableBlock;
2002 uint32_t GatherBufferOffset;
2003 /* variable length fields follow */
2004 };
2005
2006 static inline void
2007 GEN75_3DSTATE_GATHER_CONSTANT_GS_pack(__gen_user_data *data, void * restrict dst,
2008 const struct GEN75_3DSTATE_GATHER_CONSTANT_GS * restrict values)
2009 {
2010 uint32_t *dw = (uint32_t * restrict) dst;
2011
2012 dw[0] =
2013 __gen_field(values->CommandType, 29, 31) |
2014 __gen_field(values->CommandSubType, 27, 28) |
2015 __gen_field(values->_3DCommandOpcode, 24, 26) |
2016 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2017 __gen_field(values->DwordLength, 0, 7) |
2018 0;
2019
2020 dw[1] =
2021 __gen_field(values->ConstantBufferValid, 16, 31) |
2022 __gen_field(values->ConstantBufferBindingTableBlock, 12, 15) |
2023 0;
2024
2025 dw[2] =
2026 __gen_offset(values->GatherBufferOffset, 6, 22) |
2027 0;
2028
2029 /* variable length fields follow */
2030 }
2031
2032 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_length_bias 0x00000002
2033 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_header \
2034 .CommandType = 3, \
2035 .CommandSubType = 3, \
2036 ._3DCommandOpcode = 0, \
2037 ._3DCommandSubOpcode = 54
2038
2039 struct GEN75_3DSTATE_GATHER_CONSTANT_HS {
2040 uint32_t CommandType;
2041 uint32_t CommandSubType;
2042 uint32_t _3DCommandOpcode;
2043 uint32_t _3DCommandSubOpcode;
2044 uint32_t DwordLength;
2045 uint32_t ConstantBufferValid;
2046 uint32_t ConstantBufferBindingTableBlock;
2047 uint32_t GatherBufferOffset;
2048 /* variable length fields follow */
2049 };
2050
2051 static inline void
2052 GEN75_3DSTATE_GATHER_CONSTANT_HS_pack(__gen_user_data *data, void * restrict dst,
2053 const struct GEN75_3DSTATE_GATHER_CONSTANT_HS * restrict values)
2054 {
2055 uint32_t *dw = (uint32_t * restrict) dst;
2056
2057 dw[0] =
2058 __gen_field(values->CommandType, 29, 31) |
2059 __gen_field(values->CommandSubType, 27, 28) |
2060 __gen_field(values->_3DCommandOpcode, 24, 26) |
2061 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2062 __gen_field(values->DwordLength, 0, 7) |
2063 0;
2064
2065 dw[1] =
2066 __gen_field(values->ConstantBufferValid, 16, 31) |
2067 __gen_field(values->ConstantBufferBindingTableBlock, 12, 15) |
2068 0;
2069
2070 dw[2] =
2071 __gen_offset(values->GatherBufferOffset, 6, 22) |
2072 0;
2073
2074 /* variable length fields follow */
2075 }
2076
2077 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_length_bias 0x00000002
2078 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_header \
2079 .CommandType = 3, \
2080 .CommandSubType = 3, \
2081 ._3DCommandOpcode = 0, \
2082 ._3DCommandSubOpcode = 56
2083
2084 struct GEN75_3DSTATE_GATHER_CONSTANT_PS {
2085 uint32_t CommandType;
2086 uint32_t CommandSubType;
2087 uint32_t _3DCommandOpcode;
2088 uint32_t _3DCommandSubOpcode;
2089 uint32_t DwordLength;
2090 uint32_t ConstantBufferValid;
2091 uint32_t ConstantBufferBindingTableBlock;
2092 uint32_t GatherBufferOffset;
2093 uint32_t ConstantBufferDx9Enable;
2094 /* variable length fields follow */
2095 };
2096
2097 static inline void
2098 GEN75_3DSTATE_GATHER_CONSTANT_PS_pack(__gen_user_data *data, void * restrict dst,
2099 const struct GEN75_3DSTATE_GATHER_CONSTANT_PS * restrict values)
2100 {
2101 uint32_t *dw = (uint32_t * restrict) dst;
2102
2103 dw[0] =
2104 __gen_field(values->CommandType, 29, 31) |
2105 __gen_field(values->CommandSubType, 27, 28) |
2106 __gen_field(values->_3DCommandOpcode, 24, 26) |
2107 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2108 __gen_field(values->DwordLength, 0, 7) |
2109 0;
2110
2111 dw[1] =
2112 __gen_field(values->ConstantBufferValid, 16, 31) |
2113 __gen_field(values->ConstantBufferBindingTableBlock, 12, 15) |
2114 0;
2115
2116 dw[2] =
2117 __gen_offset(values->GatherBufferOffset, 6, 22) |
2118 __gen_field(values->ConstantBufferDx9Enable, 4, 4) |
2119 0;
2120
2121 /* variable length fields follow */
2122 }
2123
2124 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_length_bias 0x00000002
2125 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_header \
2126 .CommandType = 3, \
2127 .CommandSubType = 3, \
2128 ._3DCommandOpcode = 0, \
2129 ._3DCommandSubOpcode = 52
2130
2131 struct GEN75_3DSTATE_GATHER_CONSTANT_VS {
2132 uint32_t CommandType;
2133 uint32_t CommandSubType;
2134 uint32_t _3DCommandOpcode;
2135 uint32_t _3DCommandSubOpcode;
2136 uint32_t DwordLength;
2137 uint32_t ConstantBufferValid;
2138 uint32_t ConstantBufferBindingTableBlock;
2139 uint32_t GatherBufferOffset;
2140 uint32_t ConstantBufferDx9Enable;
2141 /* variable length fields follow */
2142 };
2143
2144 static inline void
2145 GEN75_3DSTATE_GATHER_CONSTANT_VS_pack(__gen_user_data *data, void * restrict dst,
2146 const struct GEN75_3DSTATE_GATHER_CONSTANT_VS * restrict values)
2147 {
2148 uint32_t *dw = (uint32_t * restrict) dst;
2149
2150 dw[0] =
2151 __gen_field(values->CommandType, 29, 31) |
2152 __gen_field(values->CommandSubType, 27, 28) |
2153 __gen_field(values->_3DCommandOpcode, 24, 26) |
2154 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2155 __gen_field(values->DwordLength, 0, 7) |
2156 0;
2157
2158 dw[1] =
2159 __gen_field(values->ConstantBufferValid, 16, 31) |
2160 __gen_field(values->ConstantBufferBindingTableBlock, 12, 15) |
2161 0;
2162
2163 dw[2] =
2164 __gen_offset(values->GatherBufferOffset, 6, 22) |
2165 __gen_field(values->ConstantBufferDx9Enable, 4, 4) |
2166 0;
2167
2168 /* variable length fields follow */
2169 }
2170
2171 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_length 0x00000003
2172 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_length_bias 0x00000002
2173 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_header \
2174 .CommandType = 3, \
2175 .CommandSubType = 3, \
2176 ._3DCommandOpcode = 1, \
2177 ._3DCommandSubOpcode = 26, \
2178 .DwordLength = 1
2179
2180 struct GEN75_3DSTATE_GATHER_POOL_ALLOC {
2181 uint32_t CommandType;
2182 uint32_t CommandSubType;
2183 uint32_t _3DCommandOpcode;
2184 uint32_t _3DCommandSubOpcode;
2185 uint32_t DwordLength;
2186 __gen_address_type GatherPoolBaseAddress;
2187 uint32_t GatherPoolEnable;
2188 struct GEN75_MEMORY_OBJECT_CONTROL_STATE MemoryObjectControlState;
2189 __gen_address_type GatherPoolUpperBound;
2190 };
2191
2192 static inline void
2193 GEN75_3DSTATE_GATHER_POOL_ALLOC_pack(__gen_user_data *data, void * restrict dst,
2194 const struct GEN75_3DSTATE_GATHER_POOL_ALLOC * restrict values)
2195 {
2196 uint32_t *dw = (uint32_t * restrict) dst;
2197
2198 dw[0] =
2199 __gen_field(values->CommandType, 29, 31) |
2200 __gen_field(values->CommandSubType, 27, 28) |
2201 __gen_field(values->_3DCommandOpcode, 24, 26) |
2202 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2203 __gen_field(values->DwordLength, 0, 7) |
2204 0;
2205
2206 uint32_t dw_MemoryObjectControlState;
2207 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_MemoryObjectControlState, &values->MemoryObjectControlState);
2208 uint32_t dw1 =
2209 __gen_field(values->GatherPoolEnable, 11, 11) |
2210 __gen_field(dw_MemoryObjectControlState, 0, 3) |
2211 0;
2212
2213 dw[1] =
2214 __gen_combine_address(data, &dw[1], values->GatherPoolBaseAddress, dw1);
2215
2216 uint32_t dw2 =
2217 0;
2218
2219 dw[2] =
2220 __gen_combine_address(data, &dw[2], values->GatherPoolUpperBound, dw2);
2221
2222 }
2223
2224 #define GEN75_3DSTATE_GS_length 0x00000007
2225 #define GEN75_3DSTATE_GS_length_bias 0x00000002
2226 #define GEN75_3DSTATE_GS_header \
2227 .CommandType = 3, \
2228 .CommandSubType = 3, \
2229 ._3DCommandOpcode = 0, \
2230 ._3DCommandSubOpcode = 17, \
2231 .DwordLength = 5
2232
2233 struct GEN75_3DSTATE_GS {
2234 uint32_t CommandType;
2235 uint32_t CommandSubType;
2236 uint32_t _3DCommandOpcode;
2237 uint32_t _3DCommandSubOpcode;
2238 uint32_t DwordLength;
2239 uint32_t KernelStartPointer;
2240 uint32_t SingleProgramFlowSPF;
2241 #define Dmask 0
2242 #define Vmask 1
2243 uint32_t VectorMaskEnableVME;
2244 #define NoSamplers 0
2245 #define _14Samplers 1
2246 #define _58Samplers 2
2247 #define _912Samplers 3
2248 #define _1316Samplers 4
2249 uint32_t SamplerCount;
2250 uint32_t BindingTableEntryCount;
2251 #define NormalPriority 0
2252 #define HighPriority 1
2253 uint32_t ThreadPriority;
2254 #define IEEE754 0
2255 #define alternate 1
2256 uint32_t FloatingPointMode;
2257 uint32_t IllegalOpcodeExceptionEnable;
2258 uint32_t GSaccessesUAV;
2259 uint32_t MaskStackExceptionEnable;
2260 uint32_t SoftwareExceptionEnable;
2261 uint32_t ScratchSpaceBasePointer;
2262 uint32_t PerThreadScratchSpace;
2263 uint32_t OutputVertexSize;
2264 uint32_t OutputTopology;
2265 uint32_t VertexURBEntryReadLength;
2266 uint32_t IncludeVertexHandles;
2267 uint32_t VertexURBEntryReadOffset;
2268 uint32_t DispatchGRFStartRegisterforURBData;
2269 uint32_t MaximumNumberofThreads;
2270 uint32_t ControlDataHeaderSize;
2271 uint32_t InstanceControl;
2272 uint32_t DefaultStreamID;
2273 #define SINGLE 0
2274 #define DUAL_INSTANCE 1
2275 #define DUAL_OBJECT 2
2276 uint32_t DispatchMode;
2277 uint32_t GSStatisticsEnable;
2278 uint32_t GSInvocationsIncrementValue;
2279 uint32_t IncludePrimitiveID;
2280 uint32_t Hint;
2281 #define REORDER_LEADING 0
2282 #define REORDER_TRAILING 1
2283 uint32_t ReorderMode;
2284 uint32_t DiscardAdjacency;
2285 uint32_t GSEnable;
2286 #define GSCTL_CUT 0
2287 #define GSCTL_SID 1
2288 uint32_t ControlDataFormat;
2289 uint32_t SemaphoreHandle;
2290 };
2291
2292 static inline void
2293 GEN75_3DSTATE_GS_pack(__gen_user_data *data, void * restrict dst,
2294 const struct GEN75_3DSTATE_GS * restrict values)
2295 {
2296 uint32_t *dw = (uint32_t * restrict) dst;
2297
2298 dw[0] =
2299 __gen_field(values->CommandType, 29, 31) |
2300 __gen_field(values->CommandSubType, 27, 28) |
2301 __gen_field(values->_3DCommandOpcode, 24, 26) |
2302 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2303 __gen_field(values->DwordLength, 0, 7) |
2304 0;
2305
2306 dw[1] =
2307 __gen_offset(values->KernelStartPointer, 6, 31) |
2308 0;
2309
2310 dw[2] =
2311 __gen_field(values->SingleProgramFlowSPF, 31, 31) |
2312 __gen_field(values->VectorMaskEnableVME, 30, 30) |
2313 __gen_field(values->SamplerCount, 27, 29) |
2314 __gen_field(values->BindingTableEntryCount, 18, 25) |
2315 __gen_field(values->ThreadPriority, 17, 17) |
2316 __gen_field(values->FloatingPointMode, 16, 16) |
2317 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
2318 __gen_field(values->GSaccessesUAV, 12, 12) |
2319 __gen_field(values->MaskStackExceptionEnable, 11, 11) |
2320 __gen_field(values->SoftwareExceptionEnable, 7, 7) |
2321 0;
2322
2323 dw[3] =
2324 __gen_offset(values->ScratchSpaceBasePointer, 10, 31) |
2325 __gen_field(values->PerThreadScratchSpace, 0, 3) |
2326 0;
2327
2328 dw[4] =
2329 __gen_field(values->OutputVertexSize, 23, 28) |
2330 __gen_field(values->OutputTopology, 17, 22) |
2331 __gen_field(values->VertexURBEntryReadLength, 11, 16) |
2332 __gen_field(values->IncludeVertexHandles, 10, 10) |
2333 __gen_field(values->VertexURBEntryReadOffset, 4, 9) |
2334 __gen_field(values->DispatchGRFStartRegisterforURBData, 0, 3) |
2335 0;
2336
2337 dw[5] =
2338 __gen_field(values->MaximumNumberofThreads, 24, 31) |
2339 __gen_field(values->ControlDataHeaderSize, 20, 23) |
2340 __gen_field(values->InstanceControl, 15, 19) |
2341 __gen_field(values->DefaultStreamID, 13, 14) |
2342 __gen_field(values->DispatchMode, 11, 12) |
2343 __gen_field(values->GSStatisticsEnable, 10, 10) |
2344 __gen_field(values->GSInvocationsIncrementValue, 5, 9) |
2345 __gen_field(values->IncludePrimitiveID, 4, 4) |
2346 __gen_field(values->Hint, 3, 3) |
2347 __gen_field(values->ReorderMode, 2, 2) |
2348 __gen_field(values->DiscardAdjacency, 1, 1) |
2349 __gen_field(values->GSEnable, 0, 0) |
2350 0;
2351
2352 dw[6] =
2353 __gen_field(values->ControlDataFormat, 31, 31) |
2354 __gen_offset(values->SemaphoreHandle, 0, 12) |
2355 0;
2356
2357 }
2358
2359 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_length 0x00000003
2360 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_length_bias 0x00000002
2361 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_header \
2362 .CommandType = 3, \
2363 .CommandSubType = 3, \
2364 ._3DCommandOpcode = 0, \
2365 ._3DCommandSubOpcode = 7, \
2366 .DwordLength = 1
2367
2368 struct GEN75_3DSTATE_HIER_DEPTH_BUFFER {
2369 uint32_t CommandType;
2370 uint32_t CommandSubType;
2371 uint32_t _3DCommandOpcode;
2372 uint32_t _3DCommandSubOpcode;
2373 uint32_t DwordLength;
2374 struct GEN75_MEMORY_OBJECT_CONTROL_STATE HierarchicalDepthBufferObjectControlState;
2375 uint32_t SurfacePitch;
2376 __gen_address_type SurfaceBaseAddress;
2377 };
2378
2379 static inline void
2380 GEN75_3DSTATE_HIER_DEPTH_BUFFER_pack(__gen_user_data *data, void * restrict dst,
2381 const struct GEN75_3DSTATE_HIER_DEPTH_BUFFER * restrict values)
2382 {
2383 uint32_t *dw = (uint32_t * restrict) dst;
2384
2385 dw[0] =
2386 __gen_field(values->CommandType, 29, 31) |
2387 __gen_field(values->CommandSubType, 27, 28) |
2388 __gen_field(values->_3DCommandOpcode, 24, 26) |
2389 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2390 __gen_field(values->DwordLength, 0, 7) |
2391 0;
2392
2393 uint32_t dw_HierarchicalDepthBufferObjectControlState;
2394 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_HierarchicalDepthBufferObjectControlState, &values->HierarchicalDepthBufferObjectControlState);
2395 dw[1] =
2396 __gen_field(dw_HierarchicalDepthBufferObjectControlState, 25, 28) |
2397 __gen_field(values->SurfacePitch, 0, 16) |
2398 0;
2399
2400 uint32_t dw2 =
2401 0;
2402
2403 dw[2] =
2404 __gen_combine_address(data, &dw[2], values->SurfaceBaseAddress, dw2);
2405
2406 }
2407
2408 #define GEN75_3DSTATE_HS_length 0x00000007
2409 #define GEN75_3DSTATE_HS_length_bias 0x00000002
2410 #define GEN75_3DSTATE_HS_header \
2411 .CommandType = 3, \
2412 .CommandSubType = 3, \
2413 ._3DCommandOpcode = 0, \
2414 ._3DCommandSubOpcode = 27, \
2415 .DwordLength = 5
2416
2417 struct GEN75_3DSTATE_HS {
2418 uint32_t CommandType;
2419 uint32_t CommandSubType;
2420 uint32_t _3DCommandOpcode;
2421 uint32_t _3DCommandSubOpcode;
2422 uint32_t DwordLength;
2423 #define NoSamplers 0
2424 #define _14Samplers 1
2425 #define _58Samplers 2
2426 #define _912Samplers 3
2427 #define _1316Samplers 4
2428 uint32_t SamplerCount;
2429 uint32_t BindingTableEntryCount;
2430 #define Normal 0
2431 #define High 1
2432 uint32_t ThreadDispatchPriority;
2433 #define IEEE754 0
2434 #define alternate 1
2435 uint32_t FloatingPointMode;
2436 uint32_t IllegalOpcodeExceptionEnable;
2437 uint32_t SoftwareExceptionEnable;
2438 uint32_t MaximumNumberofThreads;
2439 uint32_t Enable;
2440 uint32_t StatisticsEnable;
2441 uint32_t InstanceCount;
2442 uint32_t KernelStartPointer;
2443 uint32_t ScratchSpaceBasePointer;
2444 uint32_t PerThreadScratchSpace;
2445 uint32_t SingleProgramFlow;
2446 #define Dmask 0
2447 #define Vmask 1
2448 uint32_t VectorMaskEnable;
2449 uint32_t HSaccessesUAV;
2450 uint32_t IncludeVertexHandles;
2451 uint32_t DispatchGRFStartRegisterForURBData;
2452 uint32_t VertexURBEntryReadLength;
2453 uint32_t VertexURBEntryReadOffset;
2454 uint32_t SemaphoreHandle;
2455 };
2456
2457 static inline void
2458 GEN75_3DSTATE_HS_pack(__gen_user_data *data, void * restrict dst,
2459 const struct GEN75_3DSTATE_HS * restrict values)
2460 {
2461 uint32_t *dw = (uint32_t * restrict) dst;
2462
2463 dw[0] =
2464 __gen_field(values->CommandType, 29, 31) |
2465 __gen_field(values->CommandSubType, 27, 28) |
2466 __gen_field(values->_3DCommandOpcode, 24, 26) |
2467 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2468 __gen_field(values->DwordLength, 0, 7) |
2469 0;
2470
2471 dw[1] =
2472 __gen_field(values->SamplerCount, 27, 29) |
2473 __gen_field(values->BindingTableEntryCount, 18, 25) |
2474 __gen_field(values->ThreadDispatchPriority, 17, 17) |
2475 __gen_field(values->FloatingPointMode, 16, 16) |
2476 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
2477 __gen_field(values->SoftwareExceptionEnable, 12, 12) |
2478 __gen_field(values->MaximumNumberofThreads, 0, 7) |
2479 0;
2480
2481 dw[2] =
2482 __gen_field(values->Enable, 31, 31) |
2483 __gen_field(values->StatisticsEnable, 29, 29) |
2484 __gen_field(values->InstanceCount, 0, 3) |
2485 0;
2486
2487 dw[3] =
2488 __gen_offset(values->KernelStartPointer, 6, 31) |
2489 0;
2490
2491 dw[4] =
2492 __gen_offset(values->ScratchSpaceBasePointer, 10, 31) |
2493 __gen_field(values->PerThreadScratchSpace, 0, 3) |
2494 0;
2495
2496 dw[5] =
2497 __gen_field(values->SingleProgramFlow, 27, 27) |
2498 __gen_field(values->VectorMaskEnable, 26, 26) |
2499 __gen_field(values->HSaccessesUAV, 25, 25) |
2500 __gen_field(values->IncludeVertexHandles, 24, 24) |
2501 __gen_field(values->DispatchGRFStartRegisterForURBData, 19, 23) |
2502 __gen_field(values->VertexURBEntryReadLength, 11, 16) |
2503 __gen_field(values->VertexURBEntryReadOffset, 4, 9) |
2504 0;
2505
2506 dw[6] =
2507 __gen_offset(values->SemaphoreHandle, 0, 12) |
2508 0;
2509
2510 }
2511
2512 #define GEN75_3DSTATE_INDEX_BUFFER_length 0x00000003
2513 #define GEN75_3DSTATE_INDEX_BUFFER_length_bias 0x00000002
2514 #define GEN75_3DSTATE_INDEX_BUFFER_header \
2515 .CommandType = 3, \
2516 .CommandSubType = 3, \
2517 ._3DCommandOpcode = 0, \
2518 ._3DCommandSubOpcode = 10, \
2519 .DwordLength = 1
2520
2521 struct GEN75_3DSTATE_INDEX_BUFFER {
2522 uint32_t CommandType;
2523 uint32_t CommandSubType;
2524 uint32_t _3DCommandOpcode;
2525 uint32_t _3DCommandSubOpcode;
2526 struct GEN75_MEMORY_OBJECT_CONTROL_STATE MemoryObjectControlState;
2527 #define INDEX_BYTE 0
2528 #define INDEX_WORD 1
2529 #define INDEX_DWORD 2
2530 uint32_t IndexFormat;
2531 uint32_t DwordLength;
2532 __gen_address_type BufferStartingAddress;
2533 __gen_address_type BufferEndingAddress;
2534 };
2535
2536 static inline void
2537 GEN75_3DSTATE_INDEX_BUFFER_pack(__gen_user_data *data, void * restrict dst,
2538 const struct GEN75_3DSTATE_INDEX_BUFFER * restrict values)
2539 {
2540 uint32_t *dw = (uint32_t * restrict) dst;
2541
2542 uint32_t dw_MemoryObjectControlState;
2543 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_MemoryObjectControlState, &values->MemoryObjectControlState);
2544 dw[0] =
2545 __gen_field(values->CommandType, 29, 31) |
2546 __gen_field(values->CommandSubType, 27, 28) |
2547 __gen_field(values->_3DCommandOpcode, 24, 26) |
2548 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2549 __gen_field(dw_MemoryObjectControlState, 12, 15) |
2550 __gen_field(values->IndexFormat, 8, 9) |
2551 __gen_field(values->DwordLength, 0, 7) |
2552 0;
2553
2554 uint32_t dw1 =
2555 0;
2556
2557 dw[1] =
2558 __gen_combine_address(data, &dw[1], values->BufferStartingAddress, dw1);
2559
2560 uint32_t dw2 =
2561 0;
2562
2563 dw[2] =
2564 __gen_combine_address(data, &dw[2], values->BufferEndingAddress, dw2);
2565
2566 }
2567
2568 #define GEN75_3DSTATE_LINE_STIPPLE_length 0x00000003
2569 #define GEN75_3DSTATE_LINE_STIPPLE_length_bias 0x00000002
2570 #define GEN75_3DSTATE_LINE_STIPPLE_header \
2571 .CommandType = 3, \
2572 .CommandSubType = 3, \
2573 ._3DCommandOpcode = 1, \
2574 ._3DCommandSubOpcode = 8, \
2575 .DwordLength = 1
2576
2577 struct GEN75_3DSTATE_LINE_STIPPLE {
2578 uint32_t CommandType;
2579 uint32_t CommandSubType;
2580 uint32_t _3DCommandOpcode;
2581 uint32_t _3DCommandSubOpcode;
2582 uint32_t DwordLength;
2583 uint32_t ModifyEnableCurrentRepeatCounterCurrentStippleIndex;
2584 uint32_t CurrentRepeatCounter;
2585 uint32_t CurrentStippleIndex;
2586 uint32_t LineStipplePattern;
2587 float LineStippleInverseRepeatCount;
2588 uint32_t LineStippleRepeatCount;
2589 };
2590
2591 static inline void
2592 GEN75_3DSTATE_LINE_STIPPLE_pack(__gen_user_data *data, void * restrict dst,
2593 const struct GEN75_3DSTATE_LINE_STIPPLE * restrict values)
2594 {
2595 uint32_t *dw = (uint32_t * restrict) dst;
2596
2597 dw[0] =
2598 __gen_field(values->CommandType, 29, 31) |
2599 __gen_field(values->CommandSubType, 27, 28) |
2600 __gen_field(values->_3DCommandOpcode, 24, 26) |
2601 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2602 __gen_field(values->DwordLength, 0, 7) |
2603 0;
2604
2605 dw[1] =
2606 __gen_field(values->ModifyEnableCurrentRepeatCounterCurrentStippleIndex, 31, 31) |
2607 __gen_field(values->CurrentRepeatCounter, 21, 29) |
2608 __gen_field(values->CurrentStippleIndex, 16, 19) |
2609 __gen_field(values->LineStipplePattern, 0, 15) |
2610 0;
2611
2612 dw[2] =
2613 __gen_field(values->LineStippleInverseRepeatCount * (1 << 16), 15, 31) |
2614 __gen_field(values->LineStippleRepeatCount, 0, 8) |
2615 0;
2616
2617 }
2618
2619 #define GEN75_3DSTATE_MONOFILTER_SIZE_length 0x00000002
2620 #define GEN75_3DSTATE_MONOFILTER_SIZE_length_bias 0x00000002
2621 #define GEN75_3DSTATE_MONOFILTER_SIZE_header \
2622 .CommandType = 3, \
2623 .CommandSubType = 3, \
2624 ._3DCommandOpcode = 1, \
2625 ._3DCommandSubOpcode = 17, \
2626 .DwordLength = 0
2627
2628 struct GEN75_3DSTATE_MONOFILTER_SIZE {
2629 uint32_t CommandType;
2630 uint32_t CommandSubType;
2631 uint32_t _3DCommandOpcode;
2632 uint32_t _3DCommandSubOpcode;
2633 uint32_t DwordLength;
2634 uint32_t MonochromeFilterWidth;
2635 uint32_t MonochromeFilterHeight;
2636 };
2637
2638 static inline void
2639 GEN75_3DSTATE_MONOFILTER_SIZE_pack(__gen_user_data *data, void * restrict dst,
2640 const struct GEN75_3DSTATE_MONOFILTER_SIZE * restrict values)
2641 {
2642 uint32_t *dw = (uint32_t * restrict) dst;
2643
2644 dw[0] =
2645 __gen_field(values->CommandType, 29, 31) |
2646 __gen_field(values->CommandSubType, 27, 28) |
2647 __gen_field(values->_3DCommandOpcode, 24, 26) |
2648 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2649 __gen_field(values->DwordLength, 0, 7) |
2650 0;
2651
2652 dw[1] =
2653 __gen_field(values->MonochromeFilterWidth, 3, 5) |
2654 __gen_field(values->MonochromeFilterHeight, 0, 2) |
2655 0;
2656
2657 }
2658
2659 #define GEN75_3DSTATE_MULTISAMPLE_length 0x00000004
2660 #define GEN75_3DSTATE_MULTISAMPLE_length_bias 0x00000002
2661 #define GEN75_3DSTATE_MULTISAMPLE_header \
2662 .CommandType = 3, \
2663 .CommandSubType = 3, \
2664 ._3DCommandOpcode = 1, \
2665 ._3DCommandSubOpcode = 13, \
2666 .DwordLength = 2
2667
2668 struct GEN75_3DSTATE_MULTISAMPLE {
2669 uint32_t CommandType;
2670 uint32_t CommandSubType;
2671 uint32_t _3DCommandOpcode;
2672 uint32_t _3DCommandSubOpcode;
2673 uint32_t DwordLength;
2674 uint32_t MultiSampleEnable;
2675 #define PIXLOC_CENTER 0
2676 #define PIXLOC_UL_CORNER 1
2677 uint32_t PixelLocation;
2678 #define NUMSAMPLES_1 0
2679 #define NUMSAMPLES_4 2
2680 #define NUMSAMPLES_8 3
2681 uint32_t NumberofMultisamples;
2682 float Sample3XOffset;
2683 float Sample3YOffset;
2684 float Sample2XOffset;
2685 float Sample2YOffset;
2686 float Sample1XOffset;
2687 float Sample1YOffset;
2688 float Sample0XOffset;
2689 float Sample0YOffset;
2690 float Sample7XOffset;
2691 float Sample7YOffset;
2692 float Sample6XOffset;
2693 float Sample6YOffset;
2694 float Sample5XOffset;
2695 float Sample5YOffset;
2696 float Sample4XOffset;
2697 float Sample4YOffset;
2698 };
2699
2700 static inline void
2701 GEN75_3DSTATE_MULTISAMPLE_pack(__gen_user_data *data, void * restrict dst,
2702 const struct GEN75_3DSTATE_MULTISAMPLE * restrict values)
2703 {
2704 uint32_t *dw = (uint32_t * restrict) dst;
2705
2706 dw[0] =
2707 __gen_field(values->CommandType, 29, 31) |
2708 __gen_field(values->CommandSubType, 27, 28) |
2709 __gen_field(values->_3DCommandOpcode, 24, 26) |
2710 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2711 __gen_field(values->DwordLength, 0, 7) |
2712 0;
2713
2714 dw[1] =
2715 __gen_field(values->MultiSampleEnable, 5, 5) |
2716 __gen_field(values->PixelLocation, 4, 4) |
2717 __gen_field(values->NumberofMultisamples, 1, 3) |
2718 0;
2719
2720 dw[2] =
2721 __gen_field(values->Sample3XOffset * (1 << 4), 28, 31) |
2722 __gen_field(values->Sample3YOffset * (1 << 4), 24, 27) |
2723 __gen_field(values->Sample2XOffset * (1 << 4), 20, 23) |
2724 __gen_field(values->Sample2YOffset * (1 << 4), 16, 19) |
2725 __gen_field(values->Sample1XOffset * (1 << 4), 12, 15) |
2726 __gen_field(values->Sample1YOffset * (1 << 4), 8, 11) |
2727 __gen_field(values->Sample0XOffset * (1 << 4), 4, 7) |
2728 __gen_field(values->Sample0YOffset * (1 << 4), 0, 3) |
2729 0;
2730
2731 dw[3] =
2732 __gen_field(values->Sample7XOffset * (1 << 4), 28, 31) |
2733 __gen_field(values->Sample7YOffset * (1 << 4), 24, 27) |
2734 __gen_field(values->Sample6XOffset * (1 << 4), 20, 23) |
2735 __gen_field(values->Sample6YOffset * (1 << 4), 16, 19) |
2736 __gen_field(values->Sample5XOffset * (1 << 4), 12, 15) |
2737 __gen_field(values->Sample5YOffset * (1 << 4), 8, 11) |
2738 __gen_field(values->Sample4XOffset * (1 << 4), 4, 7) |
2739 __gen_field(values->Sample4YOffset * (1 << 4), 0, 3) |
2740 0;
2741
2742 }
2743
2744 #define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_length 0x00000002
2745 #define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_length_bias 0x00000002
2746 #define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_header\
2747 .CommandType = 3, \
2748 .CommandSubType = 3, \
2749 ._3DCommandOpcode = 1, \
2750 ._3DCommandSubOpcode = 6, \
2751 .DwordLength = 0
2752
2753 struct GEN75_3DSTATE_POLY_STIPPLE_OFFSET {
2754 uint32_t CommandType;
2755 uint32_t CommandSubType;
2756 uint32_t _3DCommandOpcode;
2757 uint32_t _3DCommandSubOpcode;
2758 uint32_t DwordLength;
2759 uint32_t PolygonStippleXOffset;
2760 uint32_t PolygonStippleYOffset;
2761 };
2762
2763 static inline void
2764 GEN75_3DSTATE_POLY_STIPPLE_OFFSET_pack(__gen_user_data *data, void * restrict dst,
2765 const struct GEN75_3DSTATE_POLY_STIPPLE_OFFSET * restrict values)
2766 {
2767 uint32_t *dw = (uint32_t * restrict) dst;
2768
2769 dw[0] =
2770 __gen_field(values->CommandType, 29, 31) |
2771 __gen_field(values->CommandSubType, 27, 28) |
2772 __gen_field(values->_3DCommandOpcode, 24, 26) |
2773 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2774 __gen_field(values->DwordLength, 0, 7) |
2775 0;
2776
2777 dw[1] =
2778 __gen_field(values->PolygonStippleXOffset, 8, 12) |
2779 __gen_field(values->PolygonStippleYOffset, 0, 4) |
2780 0;
2781
2782 }
2783
2784 #define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_length 0x00000021
2785 #define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_length_bias 0x00000002
2786 #define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_header\
2787 .CommandType = 3, \
2788 .CommandSubType = 3, \
2789 ._3DCommandOpcode = 1, \
2790 ._3DCommandSubOpcode = 7, \
2791 .DwordLength = 31
2792
2793 struct GEN75_3DSTATE_POLY_STIPPLE_PATTERN {
2794 uint32_t CommandType;
2795 uint32_t CommandSubType;
2796 uint32_t _3DCommandOpcode;
2797 uint32_t _3DCommandSubOpcode;
2798 uint32_t DwordLength;
2799 uint32_t PatternRow;
2800 };
2801
2802 static inline void
2803 GEN75_3DSTATE_POLY_STIPPLE_PATTERN_pack(__gen_user_data *data, void * restrict dst,
2804 const struct GEN75_3DSTATE_POLY_STIPPLE_PATTERN * restrict values)
2805 {
2806 uint32_t *dw = (uint32_t * restrict) dst;
2807
2808 dw[0] =
2809 __gen_field(values->CommandType, 29, 31) |
2810 __gen_field(values->CommandSubType, 27, 28) |
2811 __gen_field(values->_3DCommandOpcode, 24, 26) |
2812 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2813 __gen_field(values->DwordLength, 0, 7) |
2814 0;
2815
2816 dw[1] =
2817 __gen_field(values->PatternRow, 0, 31) |
2818 0;
2819
2820 }
2821
2822 #define GEN75_3DSTATE_PS_length 0x00000008
2823 #define GEN75_3DSTATE_PS_length_bias 0x00000002
2824 #define GEN75_3DSTATE_PS_header \
2825 .CommandType = 3, \
2826 .CommandSubType = 3, \
2827 ._3DCommandOpcode = 0, \
2828 ._3DCommandSubOpcode = 32, \
2829 .DwordLength = 6
2830
2831 struct GEN75_3DSTATE_PS {
2832 uint32_t CommandType;
2833 uint32_t CommandSubType;
2834 uint32_t _3DCommandOpcode;
2835 uint32_t _3DCommandSubOpcode;
2836 uint32_t DwordLength;
2837 uint32_t KernelStartPointer0;
2838 #define Multiple 0
2839 #define Single 1
2840 uint32_t SingleProgramFlowSPF;
2841 #define Dmask 0
2842 #define Vmask 1
2843 uint32_t VectorMaskEnableVME;
2844 uint32_t SamplerCount;
2845 #define FTZ 0
2846 #define RET 1
2847 uint32_t DenormalMode;
2848 uint32_t BindingTableEntryCount;
2849 #define Normal 0
2850 #define High 1
2851 uint32_t ThreadPriority;
2852 #define IEEE745 0
2853 #define Alt 1
2854 uint32_t FloatingPointMode;
2855 #define RTNE 0
2856 #define RU 1
2857 #define RD 2
2858 #define RTZ 3
2859 uint32_t RoundingMode;
2860 uint32_t IllegalOpcodeExceptionEnable;
2861 uint32_t MaskStackExceptionEnable;
2862 uint32_t SoftwareExceptionEnable;
2863 uint32_t ScratchSpaceBasePointer;
2864 uint32_t PerThreadScratchSpace;
2865 uint32_t MaximumNumberofThreads;
2866 uint32_t SampleMask;
2867 uint32_t PushConstantEnable;
2868 uint32_t AttributeEnable;
2869 uint32_t oMaskPresenttoRenderTarget;
2870 uint32_t RenderTargetFastClearEnable;
2871 uint32_t DualSourceBlendEnable;
2872 uint32_t RenderTargetResolveEnable;
2873 uint32_t PSAccessesUAV;
2874 #define POSOFFSET_NONE 0
2875 #define POSOFFSET_CENTROID 2
2876 #define POSOFFSET_SAMPLE 3
2877 uint32_t PositionXYOffsetSelect;
2878 uint32_t _32PixelDispatchEnable;
2879 uint32_t _16PixelDispatchEnable;
2880 uint32_t _8PixelDispatchEnable;
2881 uint32_t DispatchGRFStartRegisterforConstantSetupData0;
2882 uint32_t DispatchGRFStartRegisterforConstantSetupData1;
2883 uint32_t DispatchGRFStartRegisterforConstantSetupData2;
2884 uint32_t KernelStartPointer1;
2885 uint32_t KernelStartPointer2;
2886 };
2887
2888 static inline void
2889 GEN75_3DSTATE_PS_pack(__gen_user_data *data, void * restrict dst,
2890 const struct GEN75_3DSTATE_PS * restrict values)
2891 {
2892 uint32_t *dw = (uint32_t * restrict) dst;
2893
2894 dw[0] =
2895 __gen_field(values->CommandType, 29, 31) |
2896 __gen_field(values->CommandSubType, 27, 28) |
2897 __gen_field(values->_3DCommandOpcode, 24, 26) |
2898 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2899 __gen_field(values->DwordLength, 0, 7) |
2900 0;
2901
2902 dw[1] =
2903 __gen_offset(values->KernelStartPointer0, 6, 31) |
2904 0;
2905
2906 dw[2] =
2907 __gen_field(values->SingleProgramFlowSPF, 31, 31) |
2908 __gen_field(values->VectorMaskEnableVME, 30, 30) |
2909 __gen_field(values->SamplerCount, 27, 29) |
2910 __gen_field(values->DenormalMode, 26, 26) |
2911 __gen_field(values->BindingTableEntryCount, 18, 25) |
2912 __gen_field(values->ThreadPriority, 17, 17) |
2913 __gen_field(values->FloatingPointMode, 16, 16) |
2914 __gen_field(values->RoundingMode, 14, 15) |
2915 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
2916 __gen_field(values->MaskStackExceptionEnable, 11, 11) |
2917 __gen_field(values->SoftwareExceptionEnable, 7, 7) |
2918 0;
2919
2920 dw[3] =
2921 __gen_offset(values->ScratchSpaceBasePointer, 10, 31) |
2922 __gen_field(values->PerThreadScratchSpace, 0, 3) |
2923 0;
2924
2925 dw[4] =
2926 __gen_field(values->MaximumNumberofThreads, 23, 31) |
2927 __gen_field(values->SampleMask, 12, 19) |
2928 __gen_field(values->PushConstantEnable, 11, 11) |
2929 __gen_field(values->AttributeEnable, 10, 10) |
2930 __gen_field(values->oMaskPresenttoRenderTarget, 9, 9) |
2931 __gen_field(values->RenderTargetFastClearEnable, 8, 8) |
2932 __gen_field(values->DualSourceBlendEnable, 7, 7) |
2933 __gen_field(values->RenderTargetResolveEnable, 6, 6) |
2934 __gen_field(values->PSAccessesUAV, 5, 5) |
2935 __gen_field(values->PositionXYOffsetSelect, 3, 4) |
2936 __gen_field(values->_32PixelDispatchEnable, 2, 2) |
2937 __gen_field(values->_16PixelDispatchEnable, 1, 1) |
2938 __gen_field(values->_8PixelDispatchEnable, 0, 0) |
2939 0;
2940
2941 dw[5] =
2942 __gen_field(values->DispatchGRFStartRegisterforConstantSetupData0, 16, 22) |
2943 __gen_field(values->DispatchGRFStartRegisterforConstantSetupData1, 8, 14) |
2944 __gen_field(values->DispatchGRFStartRegisterforConstantSetupData2, 0, 6) |
2945 0;
2946
2947 dw[6] =
2948 __gen_offset(values->KernelStartPointer1, 6, 31) |
2949 0;
2950
2951 dw[7] =
2952 __gen_offset(values->KernelStartPointer2, 6, 31) |
2953 0;
2954
2955 }
2956
2957 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 0x00000002
2958 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length_bias 0x00000002
2959 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_header\
2960 .CommandType = 3, \
2961 .CommandSubType = 3, \
2962 ._3DCommandOpcode = 1, \
2963 ._3DCommandSubOpcode = 20, \
2964 .DwordLength = 0
2965
2966 struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS {
2967 uint32_t CommandType;
2968 uint32_t CommandSubType;
2969 uint32_t _3DCommandOpcode;
2970 uint32_t _3DCommandSubOpcode;
2971 uint32_t DwordLength;
2972 uint32_t ConstantBufferOffset;
2973 uint32_t ConstantBufferSize;
2974 };
2975
2976 static inline void
2977 GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_pack(__gen_user_data *data, void * restrict dst,
2978 const struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS * restrict values)
2979 {
2980 uint32_t *dw = (uint32_t * restrict) dst;
2981
2982 dw[0] =
2983 __gen_field(values->CommandType, 29, 31) |
2984 __gen_field(values->CommandSubType, 27, 28) |
2985 __gen_field(values->_3DCommandOpcode, 24, 26) |
2986 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
2987 __gen_field(values->DwordLength, 0, 7) |
2988 0;
2989
2990 dw[1] =
2991 __gen_field(values->ConstantBufferOffset, 16, 20) |
2992 __gen_field(values->ConstantBufferSize, 0, 5) |
2993 0;
2994
2995 }
2996
2997 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 0x00000002
2998 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length_bias 0x00000002
2999 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_header\
3000 .CommandType = 3, \
3001 .CommandSubType = 3, \
3002 ._3DCommandOpcode = 1, \
3003 ._3DCommandSubOpcode = 21, \
3004 .DwordLength = 0
3005
3006 struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS {
3007 uint32_t CommandType;
3008 uint32_t CommandSubType;
3009 uint32_t _3DCommandOpcode;
3010 uint32_t _3DCommandSubOpcode;
3011 uint32_t DwordLength;
3012 uint32_t ConstantBufferOffset;
3013 uint32_t ConstantBufferSize;
3014 };
3015
3016 static inline void
3017 GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_pack(__gen_user_data *data, void * restrict dst,
3018 const struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS * restrict values)
3019 {
3020 uint32_t *dw = (uint32_t * restrict) dst;
3021
3022 dw[0] =
3023 __gen_field(values->CommandType, 29, 31) |
3024 __gen_field(values->CommandSubType, 27, 28) |
3025 __gen_field(values->_3DCommandOpcode, 24, 26) |
3026 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3027 __gen_field(values->DwordLength, 0, 7) |
3028 0;
3029
3030 dw[1] =
3031 __gen_field(values->ConstantBufferOffset, 16, 20) |
3032 __gen_field(values->ConstantBufferSize, 0, 5) |
3033 0;
3034
3035 }
3036
3037 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 0x00000002
3038 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length_bias 0x00000002
3039 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_header\
3040 .CommandType = 3, \
3041 .CommandSubType = 3, \
3042 ._3DCommandOpcode = 1, \
3043 ._3DCommandSubOpcode = 19, \
3044 .DwordLength = 0
3045
3046 struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS {
3047 uint32_t CommandType;
3048 uint32_t CommandSubType;
3049 uint32_t _3DCommandOpcode;
3050 uint32_t _3DCommandSubOpcode;
3051 uint32_t DwordLength;
3052 uint32_t ConstantBufferOffset;
3053 uint32_t ConstantBufferSize;
3054 };
3055
3056 static inline void
3057 GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_pack(__gen_user_data *data, void * restrict dst,
3058 const struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS * restrict values)
3059 {
3060 uint32_t *dw = (uint32_t * restrict) dst;
3061
3062 dw[0] =
3063 __gen_field(values->CommandType, 29, 31) |
3064 __gen_field(values->CommandSubType, 27, 28) |
3065 __gen_field(values->_3DCommandOpcode, 24, 26) |
3066 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3067 __gen_field(values->DwordLength, 0, 7) |
3068 0;
3069
3070 dw[1] =
3071 __gen_field(values->ConstantBufferOffset, 16, 20) |
3072 __gen_field(values->ConstantBufferSize, 0, 5) |
3073 0;
3074
3075 }
3076
3077 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 0x00000002
3078 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length_bias 0x00000002
3079 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_header\
3080 .CommandType = 3, \
3081 .CommandSubType = 3, \
3082 ._3DCommandOpcode = 1, \
3083 ._3DCommandSubOpcode = 22, \
3084 .DwordLength = 0
3085
3086 struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS {
3087 uint32_t CommandType;
3088 uint32_t CommandSubType;
3089 uint32_t _3DCommandOpcode;
3090 uint32_t _3DCommandSubOpcode;
3091 uint32_t DwordLength;
3092 uint32_t ConstantBufferOffset;
3093 uint32_t ConstantBufferSize;
3094 };
3095
3096 static inline void
3097 GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_pack(__gen_user_data *data, void * restrict dst,
3098 const struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS * restrict values)
3099 {
3100 uint32_t *dw = (uint32_t * restrict) dst;
3101
3102 dw[0] =
3103 __gen_field(values->CommandType, 29, 31) |
3104 __gen_field(values->CommandSubType, 27, 28) |
3105 __gen_field(values->_3DCommandOpcode, 24, 26) |
3106 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3107 __gen_field(values->DwordLength, 0, 7) |
3108 0;
3109
3110 dw[1] =
3111 __gen_field(values->ConstantBufferOffset, 16, 20) |
3112 __gen_field(values->ConstantBufferSize, 0, 5) |
3113 0;
3114
3115 }
3116
3117 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 0x00000002
3118 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length_bias 0x00000002
3119 #define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_header\
3120 .CommandType = 3, \
3121 .CommandSubType = 3, \
3122 ._3DCommandOpcode = 1, \
3123 ._3DCommandSubOpcode = 18, \
3124 .DwordLength = 0
3125
3126 struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS {
3127 uint32_t CommandType;
3128 uint32_t CommandSubType;
3129 uint32_t _3DCommandOpcode;
3130 uint32_t _3DCommandSubOpcode;
3131 uint32_t DwordLength;
3132 uint32_t ConstantBufferOffset;
3133 uint32_t ConstantBufferSize;
3134 };
3135
3136 static inline void
3137 GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_pack(__gen_user_data *data, void * restrict dst,
3138 const struct GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS * restrict values)
3139 {
3140 uint32_t *dw = (uint32_t * restrict) dst;
3141
3142 dw[0] =
3143 __gen_field(values->CommandType, 29, 31) |
3144 __gen_field(values->CommandSubType, 27, 28) |
3145 __gen_field(values->_3DCommandOpcode, 24, 26) |
3146 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3147 __gen_field(values->DwordLength, 0, 7) |
3148 0;
3149
3150 dw[1] =
3151 __gen_field(values->ConstantBufferOffset, 16, 20) |
3152 __gen_field(values->ConstantBufferSize, 0, 5) |
3153 0;
3154
3155 }
3156
3157 #define GEN75_3DSTATE_RAST_MULTISAMPLE_length 0x00000006
3158 #define GEN75_3DSTATE_RAST_MULTISAMPLE_length_bias 0x00000002
3159 #define GEN75_3DSTATE_RAST_MULTISAMPLE_header \
3160 .CommandType = 3, \
3161 .CommandSubType = 3, \
3162 ._3DCommandOpcode = 1, \
3163 ._3DCommandSubOpcode = 14, \
3164 .DwordLength = 4
3165
3166 struct GEN75_3DSTATE_RAST_MULTISAMPLE {
3167 uint32_t CommandType;
3168 uint32_t CommandSubType;
3169 uint32_t _3DCommandOpcode;
3170 uint32_t _3DCommandSubOpcode;
3171 uint32_t DwordLength;
3172 #define NRM_NUMRASTSAMPLES_1 0
3173 #define NRM_NUMRASTSAMPLES_2 1
3174 #define NRM_NUMRASTSAMPLES_4 2
3175 #define NRM_NUMRASTSAMPLES_8 3
3176 #define NRM_NUMRASTSAMPLES_16 4
3177 uint32_t NumberofRasterizationMultisamples;
3178 float Sample3XOffset;
3179 float Sample3YOffset;
3180 float Sample2XOffset;
3181 float Sample2YOffset;
3182 float Sample1XOffset;
3183 float Sample1YOffset;
3184 float Sample0XOffset;
3185 float Sample0YOffset;
3186 float Sample7XOffset;
3187 float Sample7YOffset;
3188 float Sample6XOffset;
3189 float Sample6YOffset;
3190 float Sample5XOffset;
3191 float Sample5YOffset;
3192 float Sample4XOffset;
3193 float Sample4YOffset;
3194 float Sample11XOffset;
3195 float Sample11YOffset;
3196 float Sample10XOffset;
3197 float Sample10YOffset;
3198 float Sample9XOffset;
3199 float Sample9YOffset;
3200 float Sample8XOffset;
3201 float Sample8YOffset;
3202 float Sample15XOffset;
3203 float Sample15YOffset;
3204 float Sample14XOffset;
3205 float Sample14YOffset;
3206 float Sample13XOffset;
3207 float Sample13YOffset;
3208 float Sample12XOffset;
3209 float Sample12YOffset;
3210 };
3211
3212 static inline void
3213 GEN75_3DSTATE_RAST_MULTISAMPLE_pack(__gen_user_data *data, void * restrict dst,
3214 const struct GEN75_3DSTATE_RAST_MULTISAMPLE * restrict values)
3215 {
3216 uint32_t *dw = (uint32_t * restrict) dst;
3217
3218 dw[0] =
3219 __gen_field(values->CommandType, 29, 31) |
3220 __gen_field(values->CommandSubType, 27, 28) |
3221 __gen_field(values->_3DCommandOpcode, 24, 26) |
3222 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3223 __gen_field(values->DwordLength, 0, 7) |
3224 0;
3225
3226 dw[1] =
3227 __gen_field(values->NumberofRasterizationMultisamples, 1, 3) |
3228 0;
3229
3230 dw[2] =
3231 __gen_field(values->Sample3XOffset * (1 << 4), 28, 31) |
3232 __gen_field(values->Sample3YOffset * (1 << 4), 24, 27) |
3233 __gen_field(values->Sample2XOffset * (1 << 4), 20, 23) |
3234 __gen_field(values->Sample2YOffset * (1 << 4), 16, 19) |
3235 __gen_field(values->Sample1XOffset * (1 << 4), 12, 15) |
3236 __gen_field(values->Sample1YOffset * (1 << 4), 8, 11) |
3237 __gen_field(values->Sample0XOffset * (1 << 4), 4, 7) |
3238 __gen_field(values->Sample0YOffset * (1 << 4), 0, 3) |
3239 0;
3240
3241 dw[3] =
3242 __gen_field(values->Sample7XOffset * (1 << 4), 28, 31) |
3243 __gen_field(values->Sample7YOffset * (1 << 4), 24, 27) |
3244 __gen_field(values->Sample6XOffset * (1 << 4), 20, 23) |
3245 __gen_field(values->Sample6YOffset * (1 << 4), 16, 19) |
3246 __gen_field(values->Sample5XOffset * (1 << 4), 12, 15) |
3247 __gen_field(values->Sample5YOffset * (1 << 4), 8, 11) |
3248 __gen_field(values->Sample4XOffset * (1 << 4), 4, 7) |
3249 __gen_field(values->Sample4YOffset * (1 << 4), 0, 3) |
3250 0;
3251
3252 dw[4] =
3253 __gen_field(values->Sample11XOffset * (1 << 4), 28, 31) |
3254 __gen_field(values->Sample11YOffset * (1 << 4), 24, 27) |
3255 __gen_field(values->Sample10XOffset * (1 << 4), 20, 23) |
3256 __gen_field(values->Sample10YOffset * (1 << 4), 16, 19) |
3257 __gen_field(values->Sample9XOffset * (1 << 4), 12, 15) |
3258 __gen_field(values->Sample9YOffset * (1 << 4), 8, 11) |
3259 __gen_field(values->Sample8XOffset * (1 << 4), 4, 7) |
3260 __gen_field(values->Sample8YOffset * (1 << 4), 0, 3) |
3261 0;
3262
3263 dw[5] =
3264 __gen_field(values->Sample15XOffset * (1 << 4), 28, 31) |
3265 __gen_field(values->Sample15YOffset * (1 << 4), 24, 27) |
3266 __gen_field(values->Sample14XOffset * (1 << 4), 20, 23) |
3267 __gen_field(values->Sample14YOffset * (1 << 4), 16, 19) |
3268 __gen_field(values->Sample13XOffset * (1 << 4), 12, 15) |
3269 __gen_field(values->Sample13YOffset * (1 << 4), 8, 11) |
3270 __gen_field(values->Sample12XOffset * (1 << 4), 4, 7) |
3271 __gen_field(values->Sample12YOffset * (1 << 4), 0, 3) |
3272 0;
3273
3274 }
3275
3276 #define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_length_bias 0x00000002
3277 #define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_header\
3278 .CommandType = 3, \
3279 .CommandSubType = 3, \
3280 ._3DCommandOpcode = 1, \
3281 ._3DCommandSubOpcode = 2
3282
3283 struct GEN75_PALETTE_ENTRY {
3284 uint32_t Alpha;
3285 uint32_t Red;
3286 uint32_t Green;
3287 uint32_t Blue;
3288 };
3289
3290 static inline void
3291 GEN75_PALETTE_ENTRY_pack(__gen_user_data *data, void * restrict dst,
3292 const struct GEN75_PALETTE_ENTRY * restrict values)
3293 {
3294 uint32_t *dw = (uint32_t * restrict) dst;
3295
3296 dw[0] =
3297 __gen_field(values->Alpha, 24, 31) |
3298 __gen_field(values->Red, 16, 23) |
3299 __gen_field(values->Green, 8, 15) |
3300 __gen_field(values->Blue, 0, 7) |
3301 0;
3302
3303 }
3304
3305 struct GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0 {
3306 uint32_t CommandType;
3307 uint32_t CommandSubType;
3308 uint32_t _3DCommandOpcode;
3309 uint32_t _3DCommandSubOpcode;
3310 uint32_t DwordLength;
3311 /* variable length fields follow */
3312 };
3313
3314 static inline void
3315 GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_pack(__gen_user_data *data, void * restrict dst,
3316 const struct GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0 * restrict values)
3317 {
3318 uint32_t *dw = (uint32_t * restrict) dst;
3319
3320 dw[0] =
3321 __gen_field(values->CommandType, 29, 31) |
3322 __gen_field(values->CommandSubType, 27, 28) |
3323 __gen_field(values->_3DCommandOpcode, 24, 26) |
3324 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3325 __gen_field(values->DwordLength, 0, 7) |
3326 0;
3327
3328 /* variable length fields follow */
3329 }
3330
3331 #define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_length_bias 0x00000002
3332 #define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_header\
3333 .CommandType = 3, \
3334 .CommandSubType = 3, \
3335 ._3DCommandOpcode = 1, \
3336 ._3DCommandSubOpcode = 12
3337
3338 struct GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1 {
3339 uint32_t CommandType;
3340 uint32_t CommandSubType;
3341 uint32_t _3DCommandOpcode;
3342 uint32_t _3DCommandSubOpcode;
3343 uint32_t DwordLength;
3344 /* variable length fields follow */
3345 };
3346
3347 static inline void
3348 GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_pack(__gen_user_data *data, void * restrict dst,
3349 const struct GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1 * restrict values)
3350 {
3351 uint32_t *dw = (uint32_t * restrict) dst;
3352
3353 dw[0] =
3354 __gen_field(values->CommandType, 29, 31) |
3355 __gen_field(values->CommandSubType, 27, 28) |
3356 __gen_field(values->_3DCommandOpcode, 24, 26) |
3357 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3358 __gen_field(values->DwordLength, 0, 7) |
3359 0;
3360
3361 /* variable length fields follow */
3362 }
3363
3364 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 0x00000002
3365 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_length_bias 0x00000002
3366 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_header\
3367 .CommandType = 3, \
3368 .CommandSubType = 3, \
3369 ._3DCommandOpcode = 0, \
3370 ._3DCommandSubOpcode = 45, \
3371 .DwordLength = 0
3372
3373 struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS {
3374 uint32_t CommandType;
3375 uint32_t CommandSubType;
3376 uint32_t _3DCommandOpcode;
3377 uint32_t _3DCommandSubOpcode;
3378 uint32_t DwordLength;
3379 uint32_t PointertoDSSamplerState;
3380 };
3381
3382 static inline void
3383 GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_pack(__gen_user_data *data, void * restrict dst,
3384 const struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS * restrict values)
3385 {
3386 uint32_t *dw = (uint32_t * restrict) dst;
3387
3388 dw[0] =
3389 __gen_field(values->CommandType, 29, 31) |
3390 __gen_field(values->CommandSubType, 27, 28) |
3391 __gen_field(values->_3DCommandOpcode, 24, 26) |
3392 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3393 __gen_field(values->DwordLength, 0, 7) |
3394 0;
3395
3396 dw[1] =
3397 __gen_offset(values->PointertoDSSamplerState, 5, 31) |
3398 0;
3399
3400 }
3401
3402 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 0x00000002
3403 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_length_bias 0x00000002
3404 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_header\
3405 .CommandType = 3, \
3406 .CommandSubType = 3, \
3407 ._3DCommandOpcode = 0, \
3408 ._3DCommandSubOpcode = 46, \
3409 .DwordLength = 0
3410
3411 struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS {
3412 uint32_t CommandType;
3413 uint32_t CommandSubType;
3414 uint32_t _3DCommandOpcode;
3415 uint32_t _3DCommandSubOpcode;
3416 uint32_t DwordLength;
3417 uint32_t PointertoGSSamplerState;
3418 };
3419
3420 static inline void
3421 GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_pack(__gen_user_data *data, void * restrict dst,
3422 const struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS * restrict values)
3423 {
3424 uint32_t *dw = (uint32_t * restrict) dst;
3425
3426 dw[0] =
3427 __gen_field(values->CommandType, 29, 31) |
3428 __gen_field(values->CommandSubType, 27, 28) |
3429 __gen_field(values->_3DCommandOpcode, 24, 26) |
3430 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3431 __gen_field(values->DwordLength, 0, 7) |
3432 0;
3433
3434 dw[1] =
3435 __gen_offset(values->PointertoGSSamplerState, 5, 31) |
3436 0;
3437
3438 }
3439
3440 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 0x00000002
3441 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_length_bias 0x00000002
3442 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_header\
3443 .CommandType = 3, \
3444 .CommandSubType = 3, \
3445 ._3DCommandOpcode = 0, \
3446 ._3DCommandSubOpcode = 44, \
3447 .DwordLength = 0
3448
3449 struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS {
3450 uint32_t CommandType;
3451 uint32_t CommandSubType;
3452 uint32_t _3DCommandOpcode;
3453 uint32_t _3DCommandSubOpcode;
3454 uint32_t DwordLength;
3455 uint32_t PointertoHSSamplerState;
3456 };
3457
3458 static inline void
3459 GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_pack(__gen_user_data *data, void * restrict dst,
3460 const struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS * restrict values)
3461 {
3462 uint32_t *dw = (uint32_t * restrict) dst;
3463
3464 dw[0] =
3465 __gen_field(values->CommandType, 29, 31) |
3466 __gen_field(values->CommandSubType, 27, 28) |
3467 __gen_field(values->_3DCommandOpcode, 24, 26) |
3468 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3469 __gen_field(values->DwordLength, 0, 7) |
3470 0;
3471
3472 dw[1] =
3473 __gen_offset(values->PointertoHSSamplerState, 5, 31) |
3474 0;
3475
3476 }
3477
3478 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 0x00000002
3479 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_length_bias 0x00000002
3480 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_header\
3481 .CommandType = 3, \
3482 .CommandSubType = 3, \
3483 ._3DCommandOpcode = 0, \
3484 ._3DCommandSubOpcode = 47, \
3485 .DwordLength = 0
3486
3487 struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS {
3488 uint32_t CommandType;
3489 uint32_t CommandSubType;
3490 uint32_t _3DCommandOpcode;
3491 uint32_t _3DCommandSubOpcode;
3492 uint32_t DwordLength;
3493 uint32_t PointertoPSSamplerState;
3494 };
3495
3496 static inline void
3497 GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_pack(__gen_user_data *data, void * restrict dst,
3498 const struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS * restrict values)
3499 {
3500 uint32_t *dw = (uint32_t * restrict) dst;
3501
3502 dw[0] =
3503 __gen_field(values->CommandType, 29, 31) |
3504 __gen_field(values->CommandSubType, 27, 28) |
3505 __gen_field(values->_3DCommandOpcode, 24, 26) |
3506 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3507 __gen_field(values->DwordLength, 0, 7) |
3508 0;
3509
3510 dw[1] =
3511 __gen_offset(values->PointertoPSSamplerState, 5, 31) |
3512 0;
3513
3514 }
3515
3516 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 0x00000002
3517 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_length_bias 0x00000002
3518 #define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_header\
3519 .CommandType = 3, \
3520 .CommandSubType = 3, \
3521 ._3DCommandOpcode = 0, \
3522 ._3DCommandSubOpcode = 43, \
3523 .DwordLength = 0
3524
3525 struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS {
3526 uint32_t CommandType;
3527 uint32_t CommandSubType;
3528 uint32_t _3DCommandOpcode;
3529 uint32_t _3DCommandSubOpcode;
3530 uint32_t DwordLength;
3531 uint32_t PointertoVSSamplerState;
3532 };
3533
3534 static inline void
3535 GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_pack(__gen_user_data *data, void * restrict dst,
3536 const struct GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS * restrict values)
3537 {
3538 uint32_t *dw = (uint32_t * restrict) dst;
3539
3540 dw[0] =
3541 __gen_field(values->CommandType, 29, 31) |
3542 __gen_field(values->CommandSubType, 27, 28) |
3543 __gen_field(values->_3DCommandOpcode, 24, 26) |
3544 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3545 __gen_field(values->DwordLength, 0, 7) |
3546 0;
3547
3548 dw[1] =
3549 __gen_offset(values->PointertoVSSamplerState, 5, 31) |
3550 0;
3551
3552 }
3553
3554 #define GEN75_3DSTATE_SAMPLE_MASK_length 0x00000002
3555 #define GEN75_3DSTATE_SAMPLE_MASK_length_bias 0x00000002
3556 #define GEN75_3DSTATE_SAMPLE_MASK_header \
3557 .CommandType = 3, \
3558 .CommandSubType = 3, \
3559 ._3DCommandOpcode = 0, \
3560 ._3DCommandSubOpcode = 24, \
3561 .DwordLength = 0
3562
3563 struct GEN75_3DSTATE_SAMPLE_MASK {
3564 uint32_t CommandType;
3565 uint32_t CommandSubType;
3566 uint32_t _3DCommandOpcode;
3567 uint32_t _3DCommandSubOpcode;
3568 uint32_t DwordLength;
3569 uint32_t SampleMask;
3570 };
3571
3572 static inline void
3573 GEN75_3DSTATE_SAMPLE_MASK_pack(__gen_user_data *data, void * restrict dst,
3574 const struct GEN75_3DSTATE_SAMPLE_MASK * restrict values)
3575 {
3576 uint32_t *dw = (uint32_t * restrict) dst;
3577
3578 dw[0] =
3579 __gen_field(values->CommandType, 29, 31) |
3580 __gen_field(values->CommandSubType, 27, 28) |
3581 __gen_field(values->_3DCommandOpcode, 24, 26) |
3582 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3583 __gen_field(values->DwordLength, 0, 7) |
3584 0;
3585
3586 dw[1] =
3587 __gen_field(values->SampleMask, 0, 7) |
3588 0;
3589
3590 }
3591
3592 #define GEN75_3DSTATE_SBE_length 0x0000000e
3593 #define GEN75_3DSTATE_SBE_length_bias 0x00000002
3594 #define GEN75_3DSTATE_SBE_header \
3595 .CommandType = 3, \
3596 .CommandSubType = 3, \
3597 ._3DCommandOpcode = 0, \
3598 ._3DCommandSubOpcode = 31, \
3599 .DwordLength = 12
3600
3601 struct GEN75_3DSTATE_SBE {
3602 uint32_t CommandType;
3603 uint32_t CommandSubType;
3604 uint32_t _3DCommandOpcode;
3605 uint32_t _3DCommandSubOpcode;
3606 uint32_t DwordLength;
3607 uint32_t AttributeSwizzleControlMode;
3608 uint32_t NumberofSFOutputAttributes;
3609 uint32_t AttributeSwizzleEnable;
3610 #define UPPERLEFT 0
3611 #define LOWERLEFT 1
3612 uint32_t PointSpriteTextureCoordinateOrigin;
3613 uint32_t VertexURBEntryReadLength;
3614 uint32_t VertexURBEntryReadOffset;
3615 uint32_t Attribute2n1ComponentOverrideW;
3616 uint32_t Attribute2n1ComponentOverrideZ;
3617 uint32_t Attribute2n1ComponentOverrideY;
3618 uint32_t Attribute2n1ComponentOverrideX;
3619 #define CONST_0000 0
3620 #define CONST_0001_FLOAT 1
3621 #define CONST_1111_FLOAT 2
3622 #define PRIM_ID 3
3623 uint32_t Attribute2n1ConstantSource;
3624 #define INPUTATTR 0
3625 #define INPUTATTR_FACING 1
3626 #define INPUTATTR_W 2
3627 #define INPUTATTR_FACING_W 3
3628 uint32_t Attribute2n1SwizzleSelect;
3629 uint32_t Attribute2n1SourceAttribute;
3630 uint32_t Attribute2nComponentOverrideW;
3631 uint32_t Attribute2nComponentOverrideZ;
3632 uint32_t Attribute2nComponentOverrideY;
3633 uint32_t Attribute2nComponentOverrideX;
3634 #define CONST_0000 0
3635 #define CONST_0001_FLOAT 1
3636 #define CONST_1111_FLOAT 2
3637 #define PRIM_ID 3
3638 uint32_t Attribute2nConstantSource;
3639 #define INPUTATTR 0
3640 #define INPUTATTR_FACING 1
3641 #define INPUTATTR_W 2
3642 #define INPUTATTR_FACING_W 3
3643 uint32_t Attribute2nSwizzleSelect;
3644 uint32_t Attribute2nSourceAttribute;
3645 uint32_t PointSpriteTextureCoordinateEnable;
3646 uint32_t ConstantInterpolationEnable310;
3647 uint32_t Attribute7WrapShortestEnables;
3648 uint32_t Attribute6WrapShortestEnables;
3649 uint32_t Attribute5WrapShortestEnables;
3650 uint32_t Attribute4WrapShortestEnables;
3651 uint32_t Attribute3WrapShortestEnables;
3652 uint32_t Attribute2WrapShortestEnables;
3653 uint32_t Attribute1WrapShortestEnables;
3654 uint32_t Attribute0WrapShortestEnables;
3655 uint32_t Attribute15WrapShortestEnables;
3656 uint32_t Attribute14WrapShortestEnables;
3657 uint32_t Attribute13WrapShortestEnables;
3658 uint32_t Attribute12WrapShortestEnables;
3659 uint32_t Attribute11WrapShortestEnables;
3660 uint32_t Attribute10WrapShortestEnables;
3661 uint32_t Attribute9WrapShortestEnables;
3662 uint32_t Attribute8WrapShortestEnables;
3663 };
3664
3665 static inline void
3666 GEN75_3DSTATE_SBE_pack(__gen_user_data *data, void * restrict dst,
3667 const struct GEN75_3DSTATE_SBE * restrict values)
3668 {
3669 uint32_t *dw = (uint32_t * restrict) dst;
3670
3671 dw[0] =
3672 __gen_field(values->CommandType, 29, 31) |
3673 __gen_field(values->CommandSubType, 27, 28) |
3674 __gen_field(values->_3DCommandOpcode, 24, 26) |
3675 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3676 __gen_field(values->DwordLength, 0, 7) |
3677 0;
3678
3679 dw[1] =
3680 __gen_field(values->AttributeSwizzleControlMode, 28, 28) |
3681 __gen_field(values->NumberofSFOutputAttributes, 22, 27) |
3682 __gen_field(values->AttributeSwizzleEnable, 21, 21) |
3683 __gen_field(values->PointSpriteTextureCoordinateOrigin, 20, 20) |
3684 __gen_field(values->VertexURBEntryReadLength, 11, 15) |
3685 __gen_field(values->VertexURBEntryReadOffset, 4, 9) |
3686 0;
3687
3688 dw[2] =
3689 __gen_field(values->Attribute2n1ComponentOverrideW, 31, 31) |
3690 __gen_field(values->Attribute2n1ComponentOverrideZ, 30, 30) |
3691 __gen_field(values->Attribute2n1ComponentOverrideY, 29, 29) |
3692 __gen_field(values->Attribute2n1ComponentOverrideX, 28, 28) |
3693 __gen_field(values->Attribute2n1ConstantSource, 25, 26) |
3694 __gen_field(values->Attribute2n1SwizzleSelect, 22, 23) |
3695 __gen_field(values->Attribute2n1SourceAttribute, 16, 20) |
3696 __gen_field(values->Attribute2nComponentOverrideW, 15, 15) |
3697 __gen_field(values->Attribute2nComponentOverrideZ, 14, 14) |
3698 __gen_field(values->Attribute2nComponentOverrideY, 13, 13) |
3699 __gen_field(values->Attribute2nComponentOverrideX, 12, 12) |
3700 __gen_field(values->Attribute2nConstantSource, 9, 10) |
3701 __gen_field(values->Attribute2nSwizzleSelect, 6, 7) |
3702 __gen_field(values->Attribute2nSourceAttribute, 0, 4) |
3703 0;
3704
3705 dw[10] =
3706 __gen_field(values->PointSpriteTextureCoordinateEnable, 0, 31) |
3707 0;
3708
3709 dw[11] =
3710 __gen_field(values->ConstantInterpolationEnable310, 0, 31) |
3711 0;
3712
3713 dw[12] =
3714 __gen_field(values->Attribute7WrapShortestEnables, 28, 31) |
3715 __gen_field(values->Attribute6WrapShortestEnables, 24, 27) |
3716 __gen_field(values->Attribute5WrapShortestEnables, 20, 23) |
3717 __gen_field(values->Attribute4WrapShortestEnables, 16, 19) |
3718 __gen_field(values->Attribute3WrapShortestEnables, 12, 15) |
3719 __gen_field(values->Attribute2WrapShortestEnables, 8, 11) |
3720 __gen_field(values->Attribute1WrapShortestEnables, 4, 7) |
3721 __gen_field(values->Attribute0WrapShortestEnables, 0, 3) |
3722 0;
3723
3724 dw[13] =
3725 __gen_field(values->Attribute15WrapShortestEnables, 28, 31) |
3726 __gen_field(values->Attribute14WrapShortestEnables, 24, 27) |
3727 __gen_field(values->Attribute13WrapShortestEnables, 20, 23) |
3728 __gen_field(values->Attribute12WrapShortestEnables, 16, 19) |
3729 __gen_field(values->Attribute11WrapShortestEnables, 12, 15) |
3730 __gen_field(values->Attribute10WrapShortestEnables, 8, 11) |
3731 __gen_field(values->Attribute9WrapShortestEnables, 4, 7) |
3732 __gen_field(values->Attribute8WrapShortestEnables, 0, 3) |
3733 0;
3734
3735 }
3736
3737 #define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_length 0x00000002
3738 #define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_length_bias 0x00000002
3739 #define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_header\
3740 .CommandType = 3, \
3741 .CommandSubType = 3, \
3742 ._3DCommandOpcode = 0, \
3743 ._3DCommandSubOpcode = 15, \
3744 .DwordLength = 0
3745
3746 struct GEN75_3DSTATE_SCISSOR_STATE_POINTERS {
3747 uint32_t CommandType;
3748 uint32_t CommandSubType;
3749 uint32_t _3DCommandOpcode;
3750 uint32_t _3DCommandSubOpcode;
3751 uint32_t DwordLength;
3752 uint32_t ScissorRectPointer;
3753 };
3754
3755 static inline void
3756 GEN75_3DSTATE_SCISSOR_STATE_POINTERS_pack(__gen_user_data *data, void * restrict dst,
3757 const struct GEN75_3DSTATE_SCISSOR_STATE_POINTERS * restrict values)
3758 {
3759 uint32_t *dw = (uint32_t * restrict) dst;
3760
3761 dw[0] =
3762 __gen_field(values->CommandType, 29, 31) |
3763 __gen_field(values->CommandSubType, 27, 28) |
3764 __gen_field(values->_3DCommandOpcode, 24, 26) |
3765 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3766 __gen_field(values->DwordLength, 0, 7) |
3767 0;
3768
3769 dw[1] =
3770 __gen_offset(values->ScissorRectPointer, 5, 31) |
3771 0;
3772
3773 }
3774
3775 #define GEN75_3DSTATE_SF_length 0x00000007
3776 #define GEN75_3DSTATE_SF_length_bias 0x00000002
3777 #define GEN75_3DSTATE_SF_header \
3778 .CommandType = 3, \
3779 .CommandSubType = 3, \
3780 ._3DCommandOpcode = 0, \
3781 ._3DCommandSubOpcode = 19, \
3782 .DwordLength = 5
3783
3784 struct GEN75_3DSTATE_SF {
3785 uint32_t CommandType;
3786 uint32_t CommandSubType;
3787 uint32_t _3DCommandOpcode;
3788 uint32_t _3DCommandSubOpcode;
3789 uint32_t DwordLength;
3790 #define D32_FLOAT_S8X24_UINT 0
3791 #define D32_FLOAT 1
3792 #define D24_UNORM_S8_UINT 2
3793 #define D24_UNORM_X8_UINT 3
3794 #define D16_UNORM 5
3795 uint32_t DepthBufferSurfaceFormat;
3796 uint32_t LegacyGlobalDepthBiasEnable;
3797 uint32_t StatisticsEnable;
3798 uint32_t GlobalDepthOffsetEnableSolid;
3799 uint32_t GlobalDepthOffsetEnableWireframe;
3800 uint32_t GlobalDepthOffsetEnablePoint;
3801 #define RASTER_SOLID 0
3802 #define RASTER_WIREFRAME 1
3803 #define RASTER_POINT 2
3804 uint32_t FrontFaceFillMode;
3805 #define RASTER_SOLID 0
3806 #define RASTER_WIREFRAME 1
3807 #define RASTER_POINT 2
3808 uint32_t BackFaceFillMode;
3809 uint32_t ViewTransformEnable;
3810 uint32_t FrontWinding;
3811 uint32_t AntiAliasingEnable;
3812 #define CULLMODE_BOTH 0
3813 #define CULLMODE_NONE 1
3814 #define CULLMODE_FRONT 2
3815 #define CULLMODE_BACK 3
3816 uint32_t CullMode;
3817 float LineWidth;
3818 uint32_t LineEndCapAntialiasingRegionWidth;
3819 uint32_t LineStippleEnable;
3820 uint32_t ScissorRectangleEnable;
3821 uint32_t RTIndependentRasterizationEnable;
3822 uint32_t MultisampleRasterizationMode;
3823 uint32_t LastPixelEnable;
3824 #define Vertex0 0
3825 #define Vertex1 1
3826 #define Vertex2 2
3827 uint32_t TriangleStripListProvokingVertexSelect;
3828 uint32_t LineStripListProvokingVertexSelect;
3829 #define Vertex0 0
3830 #define Vertex1 1
3831 #define Vertex2 2
3832 uint32_t TriangleFanProvokingVertexSelect;
3833 #define AALINEDISTANCE_TRUE 1
3834 uint32_t AALineDistanceMode;
3835 uint32_t VertexSubPixelPrecisionSelect;
3836 uint32_t UsePointWidthState;
3837 float PointWidth;
3838 uint32_t GlobalDepthOffsetConstant;
3839 uint32_t GlobalDepthOffsetScale;
3840 uint32_t GlobalDepthOffsetClamp;
3841 };
3842
3843 static inline void
3844 GEN75_3DSTATE_SF_pack(__gen_user_data *data, void * restrict dst,
3845 const struct GEN75_3DSTATE_SF * restrict values)
3846 {
3847 uint32_t *dw = (uint32_t * restrict) dst;
3848
3849 dw[0] =
3850 __gen_field(values->CommandType, 29, 31) |
3851 __gen_field(values->CommandSubType, 27, 28) |
3852 __gen_field(values->_3DCommandOpcode, 24, 26) |
3853 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3854 __gen_field(values->DwordLength, 0, 7) |
3855 0;
3856
3857 dw[1] =
3858 __gen_field(values->DepthBufferSurfaceFormat, 12, 14) |
3859 __gen_field(values->LegacyGlobalDepthBiasEnable, 11, 11) |
3860 __gen_field(values->StatisticsEnable, 10, 10) |
3861 __gen_field(values->GlobalDepthOffsetEnableSolid, 9, 9) |
3862 __gen_field(values->GlobalDepthOffsetEnableWireframe, 8, 8) |
3863 __gen_field(values->GlobalDepthOffsetEnablePoint, 7, 7) |
3864 __gen_field(values->FrontFaceFillMode, 5, 6) |
3865 __gen_field(values->BackFaceFillMode, 3, 4) |
3866 __gen_field(values->ViewTransformEnable, 1, 1) |
3867 __gen_field(values->FrontWinding, 0, 0) |
3868 0;
3869
3870 dw[2] =
3871 __gen_field(values->AntiAliasingEnable, 31, 31) |
3872 __gen_field(values->CullMode, 29, 30) |
3873 __gen_field(values->LineWidth * (1 << 7), 18, 27) |
3874 __gen_field(values->LineEndCapAntialiasingRegionWidth, 16, 17) |
3875 __gen_field(values->LineStippleEnable, 14, 14) |
3876 __gen_field(values->ScissorRectangleEnable, 11, 11) |
3877 __gen_field(values->RTIndependentRasterizationEnable, 10, 10) |
3878 __gen_field(values->MultisampleRasterizationMode, 8, 9) |
3879 0;
3880
3881 dw[3] =
3882 __gen_field(values->LastPixelEnable, 31, 31) |
3883 __gen_field(values->TriangleStripListProvokingVertexSelect, 29, 30) |
3884 __gen_field(values->LineStripListProvokingVertexSelect, 27, 28) |
3885 __gen_field(values->TriangleFanProvokingVertexSelect, 25, 26) |
3886 __gen_field(values->AALineDistanceMode, 14, 14) |
3887 __gen_field(values->VertexSubPixelPrecisionSelect, 12, 12) |
3888 __gen_field(values->UsePointWidthState, 11, 11) |
3889 __gen_field(values->PointWidth * (1 << 3), 0, 10) |
3890 0;
3891
3892 dw[4] =
3893 __gen_field(values->GlobalDepthOffsetConstant, 0, 31) |
3894 0;
3895
3896 dw[5] =
3897 __gen_field(values->GlobalDepthOffsetScale, 0, 31) |
3898 0;
3899
3900 dw[6] =
3901 __gen_field(values->GlobalDepthOffsetClamp, 0, 31) |
3902 0;
3903
3904 }
3905
3906 #define GEN75_3DSTATE_SO_BUFFER_length 0x00000004
3907 #define GEN75_3DSTATE_SO_BUFFER_length_bias 0x00000002
3908 #define GEN75_3DSTATE_SO_BUFFER_header \
3909 .CommandType = 3, \
3910 .CommandSubType = 3, \
3911 ._3DCommandOpcode = 1, \
3912 ._3DCommandSubOpcode = 24, \
3913 .DwordLength = 2
3914
3915 struct GEN75_3DSTATE_SO_BUFFER {
3916 uint32_t CommandType;
3917 uint32_t CommandSubType;
3918 uint32_t _3DCommandOpcode;
3919 uint32_t _3DCommandSubOpcode;
3920 uint32_t DwordLength;
3921 uint32_t SOBufferIndex;
3922 struct GEN75_MEMORY_OBJECT_CONTROL_STATE SOBufferObjectControlState;
3923 uint32_t SurfacePitch;
3924 __gen_address_type SurfaceBaseAddress;
3925 __gen_address_type SurfaceEndAddress;
3926 };
3927
3928 static inline void
3929 GEN75_3DSTATE_SO_BUFFER_pack(__gen_user_data *data, void * restrict dst,
3930 const struct GEN75_3DSTATE_SO_BUFFER * restrict values)
3931 {
3932 uint32_t *dw = (uint32_t * restrict) dst;
3933
3934 dw[0] =
3935 __gen_field(values->CommandType, 29, 31) |
3936 __gen_field(values->CommandSubType, 27, 28) |
3937 __gen_field(values->_3DCommandOpcode, 24, 26) |
3938 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
3939 __gen_field(values->DwordLength, 0, 7) |
3940 0;
3941
3942 uint32_t dw_SOBufferObjectControlState;
3943 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_SOBufferObjectControlState, &values->SOBufferObjectControlState);
3944 dw[1] =
3945 __gen_field(values->SOBufferIndex, 29, 30) |
3946 __gen_field(dw_SOBufferObjectControlState, 25, 28) |
3947 __gen_field(values->SurfacePitch, 0, 11) |
3948 0;
3949
3950 uint32_t dw2 =
3951 0;
3952
3953 dw[2] =
3954 __gen_combine_address(data, &dw[2], values->SurfaceBaseAddress, dw2);
3955
3956 uint32_t dw3 =
3957 0;
3958
3959 dw[3] =
3960 __gen_combine_address(data, &dw[3], values->SurfaceEndAddress, dw3);
3961
3962 }
3963
3964 #define GEN75_3DSTATE_SO_DECL_LIST_length_bias 0x00000002
3965 #define GEN75_3DSTATE_SO_DECL_LIST_header \
3966 .CommandType = 3, \
3967 .CommandSubType = 3, \
3968 ._3DCommandOpcode = 1, \
3969 ._3DCommandSubOpcode = 23
3970
3971 struct GEN75_SO_DECL {
3972 uint32_t OutputBufferSlot;
3973 uint32_t HoleFlag;
3974 uint32_t RegisterIndex;
3975 uint32_t ComponentMask;
3976 };
3977
3978 static inline void
3979 GEN75_SO_DECL_pack(__gen_user_data *data, void * restrict dst,
3980 const struct GEN75_SO_DECL * restrict values)
3981 {
3982 uint32_t *dw = (uint32_t * restrict) dst;
3983
3984 dw[0] =
3985 __gen_field(values->OutputBufferSlot, 12, 13) |
3986 __gen_field(values->HoleFlag, 11, 11) |
3987 __gen_field(values->RegisterIndex, 4, 9) |
3988 __gen_field(values->ComponentMask, 0, 3) |
3989 0;
3990
3991 }
3992
3993 struct GEN75_SO_DECL_ENTRY {
3994 struct GEN75_SO_DECL Stream3Decl;
3995 struct GEN75_SO_DECL Stream2Decl;
3996 struct GEN75_SO_DECL Stream1Decl;
3997 struct GEN75_SO_DECL Stream0Decl;
3998 };
3999
4000 static inline void
4001 GEN75_SO_DECL_ENTRY_pack(__gen_user_data *data, void * restrict dst,
4002 const struct GEN75_SO_DECL_ENTRY * restrict values)
4003 {
4004 uint32_t *dw = (uint32_t * restrict) dst;
4005
4006 uint32_t dw_Stream3Decl;
4007 GEN75_SO_DECL_pack(data, &dw_Stream3Decl, &values->Stream3Decl);
4008 uint32_t dw_Stream2Decl;
4009 GEN75_SO_DECL_pack(data, &dw_Stream2Decl, &values->Stream2Decl);
4010 uint32_t dw_Stream1Decl;
4011 GEN75_SO_DECL_pack(data, &dw_Stream1Decl, &values->Stream1Decl);
4012 uint32_t dw_Stream0Decl;
4013 GEN75_SO_DECL_pack(data, &dw_Stream0Decl, &values->Stream0Decl);
4014 uint64_t qw0 =
4015 __gen_field(dw_Stream3Decl, 48, 63) |
4016 __gen_field(dw_Stream2Decl, 32, 47) |
4017 __gen_field(dw_Stream1Decl, 16, 31) |
4018 __gen_field(dw_Stream0Decl, 0, 15) |
4019 0;
4020
4021 dw[0] = qw0;
4022 dw[1] = qw0 >> 32;
4023
4024 }
4025
4026 struct GEN75_3DSTATE_SO_DECL_LIST {
4027 uint32_t CommandType;
4028 uint32_t CommandSubType;
4029 uint32_t _3DCommandOpcode;
4030 uint32_t _3DCommandSubOpcode;
4031 uint32_t DwordLength;
4032 uint32_t StreamtoBufferSelects3;
4033 uint32_t StreamtoBufferSelects2;
4034 uint32_t StreamtoBufferSelects1;
4035 uint32_t StreamtoBufferSelects0;
4036 uint32_t NumEntries3;
4037 uint32_t NumEntries2;
4038 uint32_t NumEntries1;
4039 uint32_t NumEntries0;
4040 /* variable length fields follow */
4041 };
4042
4043 static inline void
4044 GEN75_3DSTATE_SO_DECL_LIST_pack(__gen_user_data *data, void * restrict dst,
4045 const struct GEN75_3DSTATE_SO_DECL_LIST * restrict values)
4046 {
4047 uint32_t *dw = (uint32_t * restrict) dst;
4048
4049 dw[0] =
4050 __gen_field(values->CommandType, 29, 31) |
4051 __gen_field(values->CommandSubType, 27, 28) |
4052 __gen_field(values->_3DCommandOpcode, 24, 26) |
4053 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4054 __gen_field(values->DwordLength, 0, 8) |
4055 0;
4056
4057 dw[1] =
4058 __gen_field(values->StreamtoBufferSelects3, 12, 15) |
4059 __gen_field(values->StreamtoBufferSelects2, 8, 11) |
4060 __gen_field(values->StreamtoBufferSelects1, 4, 7) |
4061 __gen_field(values->StreamtoBufferSelects0, 0, 3) |
4062 0;
4063
4064 dw[2] =
4065 __gen_field(values->NumEntries3, 24, 31) |
4066 __gen_field(values->NumEntries2, 16, 23) |
4067 __gen_field(values->NumEntries1, 8, 15) |
4068 __gen_field(values->NumEntries0, 0, 7) |
4069 0;
4070
4071 /* variable length fields follow */
4072 }
4073
4074 #define GEN75_3DSTATE_STENCIL_BUFFER_length 0x00000003
4075 #define GEN75_3DSTATE_STENCIL_BUFFER_length_bias 0x00000002
4076 #define GEN75_3DSTATE_STENCIL_BUFFER_header \
4077 .CommandType = 3, \
4078 .CommandSubType = 3, \
4079 ._3DCommandOpcode = 0, \
4080 ._3DCommandSubOpcode = 6, \
4081 .DwordLength = 1
4082
4083 struct GEN75_3DSTATE_STENCIL_BUFFER {
4084 uint32_t CommandType;
4085 uint32_t CommandSubType;
4086 uint32_t _3DCommandOpcode;
4087 uint32_t _3DCommandSubOpcode;
4088 uint32_t DwordLength;
4089 uint32_t StencilBufferEnable;
4090 struct GEN75_MEMORY_OBJECT_CONTROL_STATE StencilBufferObjectControlState;
4091 uint32_t SurfacePitch;
4092 __gen_address_type SurfaceBaseAddress;
4093 };
4094
4095 static inline void
4096 GEN75_3DSTATE_STENCIL_BUFFER_pack(__gen_user_data *data, void * restrict dst,
4097 const struct GEN75_3DSTATE_STENCIL_BUFFER * restrict values)
4098 {
4099 uint32_t *dw = (uint32_t * restrict) dst;
4100
4101 dw[0] =
4102 __gen_field(values->CommandType, 29, 31) |
4103 __gen_field(values->CommandSubType, 27, 28) |
4104 __gen_field(values->_3DCommandOpcode, 24, 26) |
4105 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4106 __gen_field(values->DwordLength, 0, 7) |
4107 0;
4108
4109 uint32_t dw_StencilBufferObjectControlState;
4110 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_StencilBufferObjectControlState, &values->StencilBufferObjectControlState);
4111 dw[1] =
4112 __gen_field(values->StencilBufferEnable, 31, 31) |
4113 __gen_field(dw_StencilBufferObjectControlState, 25, 28) |
4114 __gen_field(values->SurfacePitch, 0, 16) |
4115 0;
4116
4117 uint32_t dw2 =
4118 0;
4119
4120 dw[2] =
4121 __gen_combine_address(data, &dw[2], values->SurfaceBaseAddress, dw2);
4122
4123 }
4124
4125 #define GEN75_3DSTATE_STREAMOUT_length 0x00000003
4126 #define GEN75_3DSTATE_STREAMOUT_length_bias 0x00000002
4127 #define GEN75_3DSTATE_STREAMOUT_header \
4128 .CommandType = 3, \
4129 .CommandSubType = 3, \
4130 ._3DCommandOpcode = 0, \
4131 ._3DCommandSubOpcode = 30, \
4132 .DwordLength = 1
4133
4134 struct GEN75_3DSTATE_STREAMOUT {
4135 uint32_t CommandType;
4136 uint32_t CommandSubType;
4137 uint32_t _3DCommandOpcode;
4138 uint32_t _3DCommandSubOpcode;
4139 uint32_t DwordLength;
4140 uint32_t SOFunctionEnable;
4141 uint32_t RenderingDisable;
4142 uint32_t RenderStreamSelect;
4143 #define LEADING 0
4144 #define TRAILING 1
4145 uint32_t ReorderMode;
4146 uint32_t SOStatisticsEnable;
4147 uint32_t SOBufferEnable3;
4148 uint32_t SOBufferEnable2;
4149 uint32_t SOBufferEnable1;
4150 uint32_t SOBufferEnable0;
4151 uint32_t Stream3VertexReadOffset;
4152 uint32_t Stream3VertexReadLength;
4153 uint32_t Stream2VertexReadOffset;
4154 uint32_t Stream2VertexReadLength;
4155 uint32_t Stream1VertexReadOffset;
4156 uint32_t Stream1VertexReadLength;
4157 uint32_t Stream0VertexReadOffset;
4158 uint32_t Stream0VertexReadLength;
4159 };
4160
4161 static inline void
4162 GEN75_3DSTATE_STREAMOUT_pack(__gen_user_data *data, void * restrict dst,
4163 const struct GEN75_3DSTATE_STREAMOUT * restrict values)
4164 {
4165 uint32_t *dw = (uint32_t * restrict) dst;
4166
4167 dw[0] =
4168 __gen_field(values->CommandType, 29, 31) |
4169 __gen_field(values->CommandSubType, 27, 28) |
4170 __gen_field(values->_3DCommandOpcode, 24, 26) |
4171 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4172 __gen_field(values->DwordLength, 0, 7) |
4173 0;
4174
4175 dw[1] =
4176 __gen_field(values->SOFunctionEnable, 31, 31) |
4177 __gen_field(values->RenderingDisable, 30, 30) |
4178 __gen_field(values->RenderStreamSelect, 27, 28) |
4179 __gen_field(values->ReorderMode, 26, 26) |
4180 __gen_field(values->SOStatisticsEnable, 25, 25) |
4181 __gen_field(values->SOBufferEnable3, 11, 11) |
4182 __gen_field(values->SOBufferEnable2, 10, 10) |
4183 __gen_field(values->SOBufferEnable1, 9, 9) |
4184 __gen_field(values->SOBufferEnable0, 8, 8) |
4185 0;
4186
4187 dw[2] =
4188 __gen_field(values->Stream3VertexReadOffset, 29, 29) |
4189 __gen_field(values->Stream3VertexReadLength, 24, 28) |
4190 __gen_field(values->Stream2VertexReadOffset, 21, 21) |
4191 __gen_field(values->Stream2VertexReadLength, 16, 20) |
4192 __gen_field(values->Stream1VertexReadOffset, 13, 13) |
4193 __gen_field(values->Stream1VertexReadLength, 8, 12) |
4194 __gen_field(values->Stream0VertexReadOffset, 5, 5) |
4195 __gen_field(values->Stream0VertexReadLength, 0, 4) |
4196 0;
4197
4198 }
4199
4200 #define GEN75_3DSTATE_TE_length 0x00000004
4201 #define GEN75_3DSTATE_TE_length_bias 0x00000002
4202 #define GEN75_3DSTATE_TE_header \
4203 .CommandType = 3, \
4204 .CommandSubType = 3, \
4205 ._3DCommandOpcode = 0, \
4206 ._3DCommandSubOpcode = 28, \
4207 .DwordLength = 2
4208
4209 struct GEN75_3DSTATE_TE {
4210 uint32_t CommandType;
4211 uint32_t CommandSubType;
4212 uint32_t _3DCommandOpcode;
4213 uint32_t _3DCommandSubOpcode;
4214 uint32_t DwordLength;
4215 #define INTEGER 0
4216 #define ODD_FRACTIONAL 1
4217 #define EVEN_FRACTIONAL 2
4218 uint32_t Partitioning;
4219 #define POINT 0
4220 #define LINE 1
4221 #define TRI_CW 2
4222 #define TRI_CCW 3
4223 uint32_t OutputTopology;
4224 #define QUAD 0
4225 #define TRI 1
4226 #define ISOLINE 2
4227 uint32_t TEDomain;
4228 #define HW_TESS 0
4229 #define SW_TESS 1
4230 uint32_t TEMode;
4231 uint32_t TEEnable;
4232 float MaximumTessellationFactorOdd;
4233 float MaximumTessellationFactorNotOdd;
4234 };
4235
4236 static inline void
4237 GEN75_3DSTATE_TE_pack(__gen_user_data *data, void * restrict dst,
4238 const struct GEN75_3DSTATE_TE * restrict values)
4239 {
4240 uint32_t *dw = (uint32_t * restrict) dst;
4241
4242 dw[0] =
4243 __gen_field(values->CommandType, 29, 31) |
4244 __gen_field(values->CommandSubType, 27, 28) |
4245 __gen_field(values->_3DCommandOpcode, 24, 26) |
4246 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4247 __gen_field(values->DwordLength, 0, 7) |
4248 0;
4249
4250 dw[1] =
4251 __gen_field(values->Partitioning, 12, 13) |
4252 __gen_field(values->OutputTopology, 8, 9) |
4253 __gen_field(values->TEDomain, 4, 5) |
4254 __gen_field(values->TEMode, 1, 2) |
4255 __gen_field(values->TEEnable, 0, 0) |
4256 0;
4257
4258 dw[2] =
4259 __gen_float(values->MaximumTessellationFactorOdd) |
4260 0;
4261
4262 dw[3] =
4263 __gen_float(values->MaximumTessellationFactorNotOdd) |
4264 0;
4265
4266 }
4267
4268 #define GEN75_3DSTATE_URB_DS_length 0x00000002
4269 #define GEN75_3DSTATE_URB_DS_length_bias 0x00000002
4270 #define GEN75_3DSTATE_URB_DS_header \
4271 .CommandType = 3, \
4272 .CommandSubType = 3, \
4273 ._3DCommandOpcode = 0, \
4274 ._3DCommandSubOpcode = 50, \
4275 .DwordLength = 0
4276
4277 struct GEN75_3DSTATE_URB_DS {
4278 uint32_t CommandType;
4279 uint32_t CommandSubType;
4280 uint32_t _3DCommandOpcode;
4281 uint32_t _3DCommandSubOpcode;
4282 uint32_t DwordLength;
4283 uint32_t DSURBStartingAddress;
4284 uint32_t DSURBEntryAllocationSize;
4285 uint32_t DSNumberofURBEntries;
4286 };
4287
4288 static inline void
4289 GEN75_3DSTATE_URB_DS_pack(__gen_user_data *data, void * restrict dst,
4290 const struct GEN75_3DSTATE_URB_DS * restrict values)
4291 {
4292 uint32_t *dw = (uint32_t * restrict) dst;
4293
4294 dw[0] =
4295 __gen_field(values->CommandType, 29, 31) |
4296 __gen_field(values->CommandSubType, 27, 28) |
4297 __gen_field(values->_3DCommandOpcode, 24, 26) |
4298 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4299 __gen_field(values->DwordLength, 0, 7) |
4300 0;
4301
4302 dw[1] =
4303 __gen_field(values->DSURBStartingAddress, 25, 30) |
4304 __gen_field(values->DSURBEntryAllocationSize, 16, 24) |
4305 __gen_field(values->DSNumberofURBEntries, 0, 15) |
4306 0;
4307
4308 }
4309
4310 #define GEN75_3DSTATE_URB_GS_length 0x00000002
4311 #define GEN75_3DSTATE_URB_GS_length_bias 0x00000002
4312 #define GEN75_3DSTATE_URB_GS_header \
4313 .CommandType = 3, \
4314 .CommandSubType = 3, \
4315 ._3DCommandOpcode = 0, \
4316 ._3DCommandSubOpcode = 51, \
4317 .DwordLength = 0
4318
4319 struct GEN75_3DSTATE_URB_GS {
4320 uint32_t CommandType;
4321 uint32_t CommandSubType;
4322 uint32_t _3DCommandOpcode;
4323 uint32_t _3DCommandSubOpcode;
4324 uint32_t DwordLength;
4325 uint32_t GSURBStartingAddress;
4326 uint32_t GSURBEntryAllocationSize;
4327 uint32_t GSNumberofURBEntries;
4328 };
4329
4330 static inline void
4331 GEN75_3DSTATE_URB_GS_pack(__gen_user_data *data, void * restrict dst,
4332 const struct GEN75_3DSTATE_URB_GS * restrict values)
4333 {
4334 uint32_t *dw = (uint32_t * restrict) dst;
4335
4336 dw[0] =
4337 __gen_field(values->CommandType, 29, 31) |
4338 __gen_field(values->CommandSubType, 27, 28) |
4339 __gen_field(values->_3DCommandOpcode, 24, 26) |
4340 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4341 __gen_field(values->DwordLength, 0, 7) |
4342 0;
4343
4344 dw[1] =
4345 __gen_field(values->GSURBStartingAddress, 25, 30) |
4346 __gen_field(values->GSURBEntryAllocationSize, 16, 24) |
4347 __gen_field(values->GSNumberofURBEntries, 0, 15) |
4348 0;
4349
4350 }
4351
4352 #define GEN75_3DSTATE_URB_HS_length 0x00000002
4353 #define GEN75_3DSTATE_URB_HS_length_bias 0x00000002
4354 #define GEN75_3DSTATE_URB_HS_header \
4355 .CommandType = 3, \
4356 .CommandSubType = 3, \
4357 ._3DCommandOpcode = 0, \
4358 ._3DCommandSubOpcode = 49, \
4359 .DwordLength = 0
4360
4361 struct GEN75_3DSTATE_URB_HS {
4362 uint32_t CommandType;
4363 uint32_t CommandSubType;
4364 uint32_t _3DCommandOpcode;
4365 uint32_t _3DCommandSubOpcode;
4366 uint32_t DwordLength;
4367 uint32_t HSURBStartingAddress;
4368 uint32_t HSURBEntryAllocationSize;
4369 uint32_t HSNumberofURBEntries;
4370 };
4371
4372 static inline void
4373 GEN75_3DSTATE_URB_HS_pack(__gen_user_data *data, void * restrict dst,
4374 const struct GEN75_3DSTATE_URB_HS * restrict values)
4375 {
4376 uint32_t *dw = (uint32_t * restrict) dst;
4377
4378 dw[0] =
4379 __gen_field(values->CommandType, 29, 31) |
4380 __gen_field(values->CommandSubType, 27, 28) |
4381 __gen_field(values->_3DCommandOpcode, 24, 26) |
4382 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4383 __gen_field(values->DwordLength, 0, 7) |
4384 0;
4385
4386 dw[1] =
4387 __gen_field(values->HSURBStartingAddress, 25, 30) |
4388 __gen_field(values->HSURBEntryAllocationSize, 16, 24) |
4389 __gen_field(values->HSNumberofURBEntries, 0, 15) |
4390 0;
4391
4392 }
4393
4394 #define GEN75_3DSTATE_VERTEX_BUFFERS_length_bias 0x00000002
4395 #define GEN75_3DSTATE_VERTEX_BUFFERS_header \
4396 .CommandType = 3, \
4397 .CommandSubType = 3, \
4398 ._3DCommandOpcode = 0, \
4399 ._3DCommandSubOpcode = 8
4400
4401 struct GEN75_VERTEX_BUFFER_STATE {
4402 uint32_t VertexBufferIndex;
4403 #define VERTEXDATA 0
4404 #define INSTANCEDATA 1
4405 uint32_t BufferAccessType;
4406 struct GEN75_MEMORY_OBJECT_CONTROL_STATE VertexBufferMemoryObjectControlState;
4407 uint32_t AddressModifyEnable;
4408 uint32_t NullVertexBuffer;
4409 uint32_t VertexFetchInvalidate;
4410 uint32_t BufferPitch;
4411 __gen_address_type BufferStartingAddress;
4412 __gen_address_type EndAddress;
4413 uint32_t InstanceDataStepRate;
4414 };
4415
4416 static inline void
4417 GEN75_VERTEX_BUFFER_STATE_pack(__gen_user_data *data, void * restrict dst,
4418 const struct GEN75_VERTEX_BUFFER_STATE * restrict values)
4419 {
4420 uint32_t *dw = (uint32_t * restrict) dst;
4421
4422 uint32_t dw_VertexBufferMemoryObjectControlState;
4423 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_VertexBufferMemoryObjectControlState, &values->VertexBufferMemoryObjectControlState);
4424 dw[0] =
4425 __gen_field(values->VertexBufferIndex, 26, 31) |
4426 __gen_field(values->BufferAccessType, 20, 20) |
4427 __gen_field(dw_VertexBufferMemoryObjectControlState, 16, 19) |
4428 __gen_field(values->AddressModifyEnable, 14, 14) |
4429 __gen_field(values->NullVertexBuffer, 13, 13) |
4430 __gen_field(values->VertexFetchInvalidate, 12, 12) |
4431 __gen_field(values->BufferPitch, 0, 11) |
4432 0;
4433
4434 uint32_t dw1 =
4435 0;
4436
4437 dw[1] =
4438 __gen_combine_address(data, &dw[1], values->BufferStartingAddress, dw1);
4439
4440 uint32_t dw2 =
4441 0;
4442
4443 dw[2] =
4444 __gen_combine_address(data, &dw[2], values->EndAddress, dw2);
4445
4446 dw[3] =
4447 __gen_field(values->InstanceDataStepRate, 0, 31) |
4448 0;
4449
4450 }
4451
4452 struct GEN75_3DSTATE_VERTEX_BUFFERS {
4453 uint32_t CommandType;
4454 uint32_t CommandSubType;
4455 uint32_t _3DCommandOpcode;
4456 uint32_t _3DCommandSubOpcode;
4457 uint32_t DwordLength;
4458 /* variable length fields follow */
4459 };
4460
4461 static inline void
4462 GEN75_3DSTATE_VERTEX_BUFFERS_pack(__gen_user_data *data, void * restrict dst,
4463 const struct GEN75_3DSTATE_VERTEX_BUFFERS * restrict values)
4464 {
4465 uint32_t *dw = (uint32_t * restrict) dst;
4466
4467 dw[0] =
4468 __gen_field(values->CommandType, 29, 31) |
4469 __gen_field(values->CommandSubType, 27, 28) |
4470 __gen_field(values->_3DCommandOpcode, 24, 26) |
4471 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4472 __gen_field(values->DwordLength, 0, 7) |
4473 0;
4474
4475 /* variable length fields follow */
4476 }
4477
4478 #define GEN75_3DSTATE_VERTEX_ELEMENTS_length_bias 0x00000002
4479 #define GEN75_3DSTATE_VERTEX_ELEMENTS_header \
4480 .CommandType = 3, \
4481 .CommandSubType = 3, \
4482 ._3DCommandOpcode = 0, \
4483 ._3DCommandSubOpcode = 9
4484
4485 struct GEN75_VERTEX_ELEMENT_STATE {
4486 uint32_t VertexBufferIndex;
4487 uint32_t Valid;
4488 uint32_t SourceElementFormat;
4489 uint32_t EdgeFlagEnable;
4490 uint32_t SourceElementOffset;
4491 uint32_t Component0Control;
4492 uint32_t Component1Control;
4493 uint32_t Component2Control;
4494 uint32_t Component3Control;
4495 };
4496
4497 static inline void
4498 GEN75_VERTEX_ELEMENT_STATE_pack(__gen_user_data *data, void * restrict dst,
4499 const struct GEN75_VERTEX_ELEMENT_STATE * restrict values)
4500 {
4501 uint32_t *dw = (uint32_t * restrict) dst;
4502
4503 dw[0] =
4504 __gen_field(values->VertexBufferIndex, 26, 31) |
4505 __gen_field(values->Valid, 25, 25) |
4506 __gen_field(values->SourceElementFormat, 16, 24) |
4507 __gen_field(values->EdgeFlagEnable, 15, 15) |
4508 __gen_field(values->SourceElementOffset, 0, 11) |
4509 0;
4510
4511 dw[1] =
4512 __gen_field(values->Component0Control, 28, 30) |
4513 __gen_field(values->Component1Control, 24, 26) |
4514 __gen_field(values->Component2Control, 20, 22) |
4515 __gen_field(values->Component3Control, 16, 18) |
4516 0;
4517
4518 }
4519
4520 struct GEN75_3DSTATE_VERTEX_ELEMENTS {
4521 uint32_t CommandType;
4522 uint32_t CommandSubType;
4523 uint32_t _3DCommandOpcode;
4524 uint32_t _3DCommandSubOpcode;
4525 uint32_t DwordLength;
4526 /* variable length fields follow */
4527 };
4528
4529 static inline void
4530 GEN75_3DSTATE_VERTEX_ELEMENTS_pack(__gen_user_data *data, void * restrict dst,
4531 const struct GEN75_3DSTATE_VERTEX_ELEMENTS * restrict values)
4532 {
4533 uint32_t *dw = (uint32_t * restrict) dst;
4534
4535 dw[0] =
4536 __gen_field(values->CommandType, 29, 31) |
4537 __gen_field(values->CommandSubType, 27, 28) |
4538 __gen_field(values->_3DCommandOpcode, 24, 26) |
4539 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4540 __gen_field(values->DwordLength, 0, 7) |
4541 0;
4542
4543 /* variable length fields follow */
4544 }
4545
4546 #define GEN75_3DSTATE_VF_length 0x00000002
4547 #define GEN75_3DSTATE_VF_length_bias 0x00000002
4548 #define GEN75_3DSTATE_VF_header \
4549 .CommandType = 3, \
4550 .CommandSubType = 3, \
4551 ._3DCommandOpcode = 0, \
4552 ._3DCommandSubOpcode = 12, \
4553 .DwordLength = 0
4554
4555 struct GEN75_3DSTATE_VF {
4556 uint32_t CommandType;
4557 uint32_t CommandSubType;
4558 uint32_t _3DCommandOpcode;
4559 uint32_t _3DCommandSubOpcode;
4560 uint32_t IndexedDrawCutIndexEnable;
4561 uint32_t DwordLength;
4562 uint32_t CutIndex;
4563 };
4564
4565 static inline void
4566 GEN75_3DSTATE_VF_pack(__gen_user_data *data, void * restrict dst,
4567 const struct GEN75_3DSTATE_VF * restrict values)
4568 {
4569 uint32_t *dw = (uint32_t * restrict) dst;
4570
4571 dw[0] =
4572 __gen_field(values->CommandType, 29, 31) |
4573 __gen_field(values->CommandSubType, 27, 28) |
4574 __gen_field(values->_3DCommandOpcode, 24, 26) |
4575 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4576 __gen_field(values->IndexedDrawCutIndexEnable, 8, 8) |
4577 __gen_field(values->DwordLength, 0, 7) |
4578 0;
4579
4580 dw[1] =
4581 __gen_field(values->CutIndex, 0, 31) |
4582 0;
4583
4584 }
4585
4586 #define GEN75_3DSTATE_VF_STATISTICS_length 0x00000001
4587 #define GEN75_3DSTATE_VF_STATISTICS_length_bias 0x00000001
4588 #define GEN75_3DSTATE_VF_STATISTICS_header \
4589 .CommandType = 3, \
4590 .CommandSubType = 1, \
4591 ._3DCommandOpcode = 0, \
4592 ._3DCommandSubOpcode = 11
4593
4594 struct GEN75_3DSTATE_VF_STATISTICS {
4595 uint32_t CommandType;
4596 uint32_t CommandSubType;
4597 uint32_t _3DCommandOpcode;
4598 uint32_t _3DCommandSubOpcode;
4599 uint32_t StatisticsEnable;
4600 };
4601
4602 static inline void
4603 GEN75_3DSTATE_VF_STATISTICS_pack(__gen_user_data *data, void * restrict dst,
4604 const struct GEN75_3DSTATE_VF_STATISTICS * restrict values)
4605 {
4606 uint32_t *dw = (uint32_t * restrict) dst;
4607
4608 dw[0] =
4609 __gen_field(values->CommandType, 29, 31) |
4610 __gen_field(values->CommandSubType, 27, 28) |
4611 __gen_field(values->_3DCommandOpcode, 24, 26) |
4612 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4613 __gen_field(values->StatisticsEnable, 0, 0) |
4614 0;
4615
4616 }
4617
4618 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 0x00000002
4619 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length_bias 0x00000002
4620 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_header\
4621 .CommandType = 3, \
4622 .CommandSubType = 3, \
4623 ._3DCommandOpcode = 0, \
4624 ._3DCommandSubOpcode = 35, \
4625 .DwordLength = 0
4626
4627 struct GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC {
4628 uint32_t CommandType;
4629 uint32_t CommandSubType;
4630 uint32_t _3DCommandOpcode;
4631 uint32_t _3DCommandSubOpcode;
4632 uint32_t DwordLength;
4633 uint32_t CCViewportPointer;
4634 };
4635
4636 static inline void
4637 GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_pack(__gen_user_data *data, void * restrict dst,
4638 const struct GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC * restrict values)
4639 {
4640 uint32_t *dw = (uint32_t * restrict) dst;
4641
4642 dw[0] =
4643 __gen_field(values->CommandType, 29, 31) |
4644 __gen_field(values->CommandSubType, 27, 28) |
4645 __gen_field(values->_3DCommandOpcode, 24, 26) |
4646 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4647 __gen_field(values->DwordLength, 0, 7) |
4648 0;
4649
4650 dw[1] =
4651 __gen_offset(values->CCViewportPointer, 5, 31) |
4652 0;
4653
4654 }
4655
4656 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 0x00000002
4657 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length_bias 0x00000002
4658 #define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_header\
4659 .CommandType = 3, \
4660 .CommandSubType = 3, \
4661 ._3DCommandOpcode = 0, \
4662 ._3DCommandSubOpcode = 33, \
4663 .DwordLength = 0
4664
4665 struct GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP {
4666 uint32_t CommandType;
4667 uint32_t CommandSubType;
4668 uint32_t _3DCommandOpcode;
4669 uint32_t _3DCommandSubOpcode;
4670 uint32_t DwordLength;
4671 uint32_t SFClipViewportPointer;
4672 };
4673
4674 static inline void
4675 GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_pack(__gen_user_data *data, void * restrict dst,
4676 const struct GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP * restrict values)
4677 {
4678 uint32_t *dw = (uint32_t * restrict) dst;
4679
4680 dw[0] =
4681 __gen_field(values->CommandType, 29, 31) |
4682 __gen_field(values->CommandSubType, 27, 28) |
4683 __gen_field(values->_3DCommandOpcode, 24, 26) |
4684 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4685 __gen_field(values->DwordLength, 0, 7) |
4686 0;
4687
4688 dw[1] =
4689 __gen_offset(values->SFClipViewportPointer, 6, 31) |
4690 0;
4691
4692 }
4693
4694 #define GEN75_3DSTATE_VS_length 0x00000006
4695 #define GEN75_3DSTATE_VS_length_bias 0x00000002
4696 #define GEN75_3DSTATE_VS_header \
4697 .CommandType = 3, \
4698 .CommandSubType = 3, \
4699 ._3DCommandOpcode = 0, \
4700 ._3DCommandSubOpcode = 16, \
4701 .DwordLength = 4
4702
4703 struct GEN75_3DSTATE_VS {
4704 uint32_t CommandType;
4705 uint32_t CommandSubType;
4706 uint32_t _3DCommandOpcode;
4707 uint32_t _3DCommandSubOpcode;
4708 uint32_t DwordLength;
4709 uint32_t KernelStartPointer;
4710 #define Multiple 0
4711 #define Single 1
4712 uint32_t SingleVertexDispatch;
4713 #define Dmask 0
4714 #define Vmask 1
4715 uint32_t VectorMaskEnableVME;
4716 #define NoSamplers 0
4717 #define _14Samplers 1
4718 #define _58Samplers 2
4719 #define _912Samplers 3
4720 #define _1316Samplers 4
4721 uint32_t SamplerCount;
4722 uint32_t BindingTableEntryCount;
4723 #define NormalPriority 0
4724 #define HighPriority 1
4725 uint32_t ThreadPriority;
4726 #define IEEE754 0
4727 #define Alternate 1
4728 uint32_t FloatingPointMode;
4729 uint32_t IllegalOpcodeExceptionEnable;
4730 uint32_t VSaccessesUAV;
4731 uint32_t SoftwareExceptionEnable;
4732 uint32_t ScratchSpaceBaseOffset;
4733 uint32_t PerThreadScratchSpace;
4734 uint32_t DispatchGRFStartRegisterforURBData;
4735 uint32_t VertexURBEntryReadLength;
4736 uint32_t VertexURBEntryReadOffset;
4737 uint32_t MaximumNumberofThreads;
4738 uint32_t StatisticsEnable;
4739 uint32_t VertexCacheDisable;
4740 uint32_t VSFunctionEnable;
4741 };
4742
4743 static inline void
4744 GEN75_3DSTATE_VS_pack(__gen_user_data *data, void * restrict dst,
4745 const struct GEN75_3DSTATE_VS * restrict values)
4746 {
4747 uint32_t *dw = (uint32_t * restrict) dst;
4748
4749 dw[0] =
4750 __gen_field(values->CommandType, 29, 31) |
4751 __gen_field(values->CommandSubType, 27, 28) |
4752 __gen_field(values->_3DCommandOpcode, 24, 26) |
4753 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4754 __gen_field(values->DwordLength, 0, 7) |
4755 0;
4756
4757 dw[1] =
4758 __gen_offset(values->KernelStartPointer, 6, 31) |
4759 0;
4760
4761 dw[2] =
4762 __gen_field(values->SingleVertexDispatch, 31, 31) |
4763 __gen_field(values->VectorMaskEnableVME, 30, 30) |
4764 __gen_field(values->SamplerCount, 27, 29) |
4765 __gen_field(values->BindingTableEntryCount, 18, 25) |
4766 __gen_field(values->ThreadPriority, 17, 17) |
4767 __gen_field(values->FloatingPointMode, 16, 16) |
4768 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
4769 __gen_field(values->VSaccessesUAV, 12, 12) |
4770 __gen_field(values->SoftwareExceptionEnable, 7, 7) |
4771 0;
4772
4773 dw[3] =
4774 __gen_offset(values->ScratchSpaceBaseOffset, 10, 31) |
4775 __gen_field(values->PerThreadScratchSpace, 0, 3) |
4776 0;
4777
4778 dw[4] =
4779 __gen_field(values->DispatchGRFStartRegisterforURBData, 20, 24) |
4780 __gen_field(values->VertexURBEntryReadLength, 11, 16) |
4781 __gen_field(values->VertexURBEntryReadOffset, 4, 9) |
4782 0;
4783
4784 dw[5] =
4785 __gen_field(values->MaximumNumberofThreads, 23, 31) |
4786 __gen_field(values->StatisticsEnable, 10, 10) |
4787 __gen_field(values->VertexCacheDisable, 1, 1) |
4788 __gen_field(values->VSFunctionEnable, 0, 0) |
4789 0;
4790
4791 }
4792
4793 #define GEN75_3DSTATE_WM_length 0x00000003
4794 #define GEN75_3DSTATE_WM_length_bias 0x00000002
4795 #define GEN75_3DSTATE_WM_header \
4796 .CommandType = 3, \
4797 .CommandSubType = 3, \
4798 ._3DCommandOpcode = 0, \
4799 ._3DCommandSubOpcode = 20, \
4800 .DwordLength = 1
4801
4802 struct GEN75_3DSTATE_WM {
4803 uint32_t CommandType;
4804 uint32_t CommandSubType;
4805 uint32_t _3DCommandOpcode;
4806 uint32_t _3DCommandSubOpcode;
4807 uint32_t DwordLength;
4808 uint32_t StatisticsEnable;
4809 uint32_t DepthBufferClear;
4810 uint32_t ThreadDispatchEnable;
4811 uint32_t DepthBufferResolveEnable;
4812 uint32_t HierarchicalDepthBufferResolveEnable;
4813 uint32_t LegacyDiamondLineRasterization;
4814 uint32_t PixelShaderKillPixel;
4815 #define PSCDEPTH_OFF 0
4816 #define PSCDEPTH_ON 1
4817 #define PSCDEPTH_ON_GE 2
4818 #define PSCDEPTH_ON_LE 3
4819 uint32_t PixelShaderComputedDepthMode;
4820 #define EDSC_NORMAL 0
4821 #define EDSC_PSEXEC 1
4822 #define EDSC_PREPS 2
4823 uint32_t EarlyDepthStencilControl;
4824 uint32_t PixelShaderUsesSourceDepth;
4825 uint32_t PixelShaderUsesSourceW;
4826 #define INTERP_PIXEL 0
4827 #define INTERP_CENTROID 2
4828 #define INTERP_SAMPLE 3
4829 uint32_t PositionZWInterpolationMode;
4830 uint32_t BarycentricInterpolationMode;
4831 uint32_t PixelShaderUsesInputCoverageMask;
4832 uint32_t LineEndCapAntialiasingRegionWidth;
4833 uint32_t LineAntialiasingRegionWidth;
4834 uint32_t RTIndependentRasterizationEnable;
4835 uint32_t PolygonStippleEnable;
4836 uint32_t LineStippleEnable;
4837 #define RASTRULE_UPPER_LEFT 0
4838 #define RASTRULE_UPPER_RIGHT 1
4839 uint32_t PointRasterizationRule;
4840 #define MSRASTMODE_OFF_PIXEL 0
4841 #define MSRASTMODE_OFF_PATTERN 1
4842 #define MSRASTMODE_ON_PIXEL 2
4843 #define MSRASTMODE_ON_PATTERN 3
4844 uint32_t MultisampleRasterizationMode;
4845 #define MSDISPMODE_PERSAMPLE 0
4846 #define MSDISPMODE_PERPIXEL 1
4847 uint32_t MultisampleDispatchMode;
4848 #define OFF 0
4849 #define ON 1
4850 uint32_t PSUAVonly;
4851 };
4852
4853 static inline void
4854 GEN75_3DSTATE_WM_pack(__gen_user_data *data, void * restrict dst,
4855 const struct GEN75_3DSTATE_WM * restrict values)
4856 {
4857 uint32_t *dw = (uint32_t * restrict) dst;
4858
4859 dw[0] =
4860 __gen_field(values->CommandType, 29, 31) |
4861 __gen_field(values->CommandSubType, 27, 28) |
4862 __gen_field(values->_3DCommandOpcode, 24, 26) |
4863 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
4864 __gen_field(values->DwordLength, 0, 7) |
4865 0;
4866
4867 dw[1] =
4868 __gen_field(values->StatisticsEnable, 31, 31) |
4869 __gen_field(values->DepthBufferClear, 30, 30) |
4870 __gen_field(values->ThreadDispatchEnable, 29, 29) |
4871 __gen_field(values->DepthBufferResolveEnable, 28, 28) |
4872 __gen_field(values->HierarchicalDepthBufferResolveEnable, 27, 27) |
4873 __gen_field(values->LegacyDiamondLineRasterization, 26, 26) |
4874 __gen_field(values->PixelShaderKillPixel, 25, 25) |
4875 __gen_field(values->PixelShaderComputedDepthMode, 23, 24) |
4876 __gen_field(values->EarlyDepthStencilControl, 21, 22) |
4877 __gen_field(values->PixelShaderUsesSourceDepth, 20, 20) |
4878 __gen_field(values->PixelShaderUsesSourceW, 19, 19) |
4879 __gen_field(values->PositionZWInterpolationMode, 17, 18) |
4880 __gen_field(values->BarycentricInterpolationMode, 11, 16) |
4881 __gen_field(values->PixelShaderUsesInputCoverageMask, 10, 10) |
4882 __gen_field(values->LineEndCapAntialiasingRegionWidth, 8, 9) |
4883 __gen_field(values->LineAntialiasingRegionWidth, 6, 7) |
4884 __gen_field(values->RTIndependentRasterizationEnable, 5, 5) |
4885 __gen_field(values->PolygonStippleEnable, 4, 4) |
4886 __gen_field(values->LineStippleEnable, 3, 3) |
4887 __gen_field(values->PointRasterizationRule, 2, 2) |
4888 __gen_field(values->MultisampleRasterizationMode, 0, 1) |
4889 0;
4890
4891 dw[2] =
4892 __gen_field(values->MultisampleDispatchMode, 31, 31) |
4893 __gen_field(values->PSUAVonly, 30, 30) |
4894 0;
4895
4896 }
4897
4898 #define GEN75_GPGPU_OBJECT_length 0x00000008
4899 #define GEN75_GPGPU_OBJECT_length_bias 0x00000002
4900 #define GEN75_GPGPU_OBJECT_header \
4901 .CommandType = 3, \
4902 .Pipeline = 2, \
4903 .MediaCommandOpcode = 1, \
4904 .SubOpcode = 4, \
4905 .DwordLength = 6
4906
4907 struct GEN75_GPGPU_OBJECT {
4908 uint32_t CommandType;
4909 uint32_t Pipeline;
4910 uint32_t MediaCommandOpcode;
4911 uint32_t SubOpcode;
4912 uint32_t PredicateEnable;
4913 uint32_t DwordLength;
4914 uint32_t SharedLocalMemoryFixedOffset;
4915 uint32_t InterfaceDescriptorOffset;
4916 uint32_t SharedLocalMemoryOffset;
4917 uint32_t EndofThreadGroup;
4918 #define Slice0 0
4919 #define Slice1 1
4920 uint32_t SliceDestinationSelect;
4921 #define HalfSlice1 2
4922 #define HalfSlice0 1
4923 #define EitherHalfSlice 0
4924 uint32_t HalfSliceDestinationSelect;
4925 uint32_t IndirectDataLength;
4926 uint32_t IndirectDataStartAddress;
4927 uint32_t ThreadGroupIDX;
4928 uint32_t ThreadGroupIDY;
4929 uint32_t ThreadGroupIDZ;
4930 uint32_t ExecutionMask;
4931 };
4932
4933 static inline void
4934 GEN75_GPGPU_OBJECT_pack(__gen_user_data *data, void * restrict dst,
4935 const struct GEN75_GPGPU_OBJECT * restrict values)
4936 {
4937 uint32_t *dw = (uint32_t * restrict) dst;
4938
4939 dw[0] =
4940 __gen_field(values->CommandType, 29, 31) |
4941 __gen_field(values->Pipeline, 27, 28) |
4942 __gen_field(values->MediaCommandOpcode, 24, 26) |
4943 __gen_field(values->SubOpcode, 16, 23) |
4944 __gen_field(values->PredicateEnable, 8, 8) |
4945 __gen_field(values->DwordLength, 0, 7) |
4946 0;
4947
4948 dw[1] =
4949 __gen_field(values->SharedLocalMemoryFixedOffset, 7, 7) |
4950 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
4951 0;
4952
4953 dw[2] =
4954 __gen_field(values->SharedLocalMemoryOffset, 28, 31) |
4955 __gen_field(values->EndofThreadGroup, 24, 24) |
4956 __gen_field(values->SliceDestinationSelect, 19, 19) |
4957 __gen_field(values->HalfSliceDestinationSelect, 17, 18) |
4958 __gen_field(values->IndirectDataLength, 0, 16) |
4959 0;
4960
4961 dw[3] =
4962 __gen_offset(values->IndirectDataStartAddress, 0, 31) |
4963 0;
4964
4965 dw[4] =
4966 __gen_field(values->ThreadGroupIDX, 0, 31) |
4967 0;
4968
4969 dw[5] =
4970 __gen_field(values->ThreadGroupIDY, 0, 31) |
4971 0;
4972
4973 dw[6] =
4974 __gen_field(values->ThreadGroupIDZ, 0, 31) |
4975 0;
4976
4977 dw[7] =
4978 __gen_field(values->ExecutionMask, 0, 31) |
4979 0;
4980
4981 }
4982
4983 #define GEN75_GPGPU_WALKER_length 0x0000000b
4984 #define GEN75_GPGPU_WALKER_length_bias 0x00000002
4985 #define GEN75_GPGPU_WALKER_header \
4986 .CommandType = 3, \
4987 .Pipeline = 2, \
4988 .MediaCommandOpcode = 1, \
4989 .SubOpcodeA = 5, \
4990 .DwordLength = 9
4991
4992 struct GEN75_GPGPU_WALKER {
4993 uint32_t CommandType;
4994 uint32_t Pipeline;
4995 uint32_t MediaCommandOpcode;
4996 uint32_t SubOpcodeA;
4997 uint32_t IndirectParameterEnable;
4998 uint32_t PredicateEnable;
4999 uint32_t DwordLength;
5000 uint32_t InterfaceDescriptorOffset;
5001 #define SIMD8 0
5002 #define SIMD16 1
5003 #define SIMD32 2
5004 uint32_t SIMDSize;
5005 uint32_t ThreadDepthCounterMaximum;
5006 uint32_t ThreadHeightCounterMaximum;
5007 uint32_t ThreadWidthCounterMaximum;
5008 uint32_t ThreadGroupIDStartingX;
5009 uint32_t ThreadGroupIDXDimension;
5010 uint32_t ThreadGroupIDStartingY;
5011 uint32_t ThreadGroupIDYDimension;
5012 uint32_t ThreadGroupIDStartingZ;
5013 uint32_t ThreadGroupIDZDimension;
5014 uint32_t RightExecutionMask;
5015 uint32_t BottomExecutionMask;
5016 };
5017
5018 static inline void
5019 GEN75_GPGPU_WALKER_pack(__gen_user_data *data, void * restrict dst,
5020 const struct GEN75_GPGPU_WALKER * restrict values)
5021 {
5022 uint32_t *dw = (uint32_t * restrict) dst;
5023
5024 dw[0] =
5025 __gen_field(values->CommandType, 29, 31) |
5026 __gen_field(values->Pipeline, 27, 28) |
5027 __gen_field(values->MediaCommandOpcode, 24, 26) |
5028 __gen_field(values->SubOpcodeA, 16, 23) |
5029 __gen_field(values->IndirectParameterEnable, 10, 10) |
5030 __gen_field(values->PredicateEnable, 8, 8) |
5031 __gen_field(values->DwordLength, 0, 7) |
5032 0;
5033
5034 dw[1] =
5035 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
5036 0;
5037
5038 dw[2] =
5039 __gen_field(values->SIMDSize, 30, 31) |
5040 __gen_field(values->ThreadDepthCounterMaximum, 16, 21) |
5041 __gen_field(values->ThreadHeightCounterMaximum, 8, 13) |
5042 __gen_field(values->ThreadWidthCounterMaximum, 0, 5) |
5043 0;
5044
5045 dw[3] =
5046 __gen_field(values->ThreadGroupIDStartingX, 0, 31) |
5047 0;
5048
5049 dw[4] =
5050 __gen_field(values->ThreadGroupIDXDimension, 0, 31) |
5051 0;
5052
5053 dw[5] =
5054 __gen_field(values->ThreadGroupIDStartingY, 0, 31) |
5055 0;
5056
5057 dw[6] =
5058 __gen_field(values->ThreadGroupIDYDimension, 0, 31) |
5059 0;
5060
5061 dw[7] =
5062 __gen_field(values->ThreadGroupIDStartingZ, 0, 31) |
5063 0;
5064
5065 dw[8] =
5066 __gen_field(values->ThreadGroupIDZDimension, 0, 31) |
5067 0;
5068
5069 dw[9] =
5070 __gen_field(values->RightExecutionMask, 0, 31) |
5071 0;
5072
5073 dw[10] =
5074 __gen_field(values->BottomExecutionMask, 0, 31) |
5075 0;
5076
5077 }
5078
5079 #define GEN75_MEDIA_CURBE_LOAD_length 0x00000004
5080 #define GEN75_MEDIA_CURBE_LOAD_length_bias 0x00000002
5081 #define GEN75_MEDIA_CURBE_LOAD_header \
5082 .CommandType = 3, \
5083 .Pipeline = 2, \
5084 .MediaCommandOpcode = 0, \
5085 .SubOpcode = 1, \
5086 .DwordLength = 2
5087
5088 struct GEN75_MEDIA_CURBE_LOAD {
5089 uint32_t CommandType;
5090 uint32_t Pipeline;
5091 uint32_t MediaCommandOpcode;
5092 uint32_t SubOpcode;
5093 uint32_t DwordLength;
5094 uint32_t CURBETotalDataLength;
5095 uint32_t CURBEDataStartAddress;
5096 };
5097
5098 static inline void
5099 GEN75_MEDIA_CURBE_LOAD_pack(__gen_user_data *data, void * restrict dst,
5100 const struct GEN75_MEDIA_CURBE_LOAD * restrict values)
5101 {
5102 uint32_t *dw = (uint32_t * restrict) dst;
5103
5104 dw[0] =
5105 __gen_field(values->CommandType, 29, 31) |
5106 __gen_field(values->Pipeline, 27, 28) |
5107 __gen_field(values->MediaCommandOpcode, 24, 26) |
5108 __gen_field(values->SubOpcode, 16, 23) |
5109 __gen_field(values->DwordLength, 0, 15) |
5110 0;
5111
5112 dw[1] =
5113 0;
5114
5115 dw[2] =
5116 __gen_field(values->CURBETotalDataLength, 0, 16) |
5117 0;
5118
5119 dw[3] =
5120 __gen_field(values->CURBEDataStartAddress, 0, 31) |
5121 0;
5122
5123 }
5124
5125 #define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 0x00000004
5126 #define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length_bias 0x00000002
5127 #define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_header\
5128 .CommandType = 3, \
5129 .Pipeline = 2, \
5130 .MediaCommandOpcode = 0, \
5131 .SubOpcode = 2, \
5132 .DwordLength = 2
5133
5134 struct GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD {
5135 uint32_t CommandType;
5136 uint32_t Pipeline;
5137 uint32_t MediaCommandOpcode;
5138 uint32_t SubOpcode;
5139 uint32_t DwordLength;
5140 uint32_t InterfaceDescriptorTotalLength;
5141 uint32_t InterfaceDescriptorDataStartAddress;
5142 };
5143
5144 static inline void
5145 GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_pack(__gen_user_data *data, void * restrict dst,
5146 const struct GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD * restrict values)
5147 {
5148 uint32_t *dw = (uint32_t * restrict) dst;
5149
5150 dw[0] =
5151 __gen_field(values->CommandType, 29, 31) |
5152 __gen_field(values->Pipeline, 27, 28) |
5153 __gen_field(values->MediaCommandOpcode, 24, 26) |
5154 __gen_field(values->SubOpcode, 16, 23) |
5155 __gen_field(values->DwordLength, 0, 15) |
5156 0;
5157
5158 dw[1] =
5159 0;
5160
5161 dw[2] =
5162 __gen_field(values->InterfaceDescriptorTotalLength, 0, 16) |
5163 0;
5164
5165 dw[3] =
5166 __gen_offset(values->InterfaceDescriptorDataStartAddress, 0, 31) |
5167 0;
5168
5169 }
5170
5171 #define GEN75_MEDIA_OBJECT_length_bias 0x00000002
5172 #define GEN75_MEDIA_OBJECT_header \
5173 .CommandType = 3, \
5174 .MediaCommandPipeline = 2, \
5175 .MediaCommandOpcode = 1, \
5176 .MediaCommandSubOpcode = 0
5177
5178 struct GEN75_MEDIA_OBJECT {
5179 uint32_t CommandType;
5180 uint32_t MediaCommandPipeline;
5181 uint32_t MediaCommandOpcode;
5182 uint32_t MediaCommandSubOpcode;
5183 uint32_t DwordLength;
5184 uint32_t InterfaceDescriptorOffset;
5185 uint32_t ChildrenPresent;
5186 #define Nothreadsynchronization 0
5187 #define Threaddispatchissynchronizedbythespawnrootthreadmessage 1
5188 uint32_t ThreadSynchronization;
5189 #define Notusingscoreboard 0
5190 #define Usingscoreboard 1
5191 uint32_t UseScoreboard;
5192 #define Slice0 0
5193 #define Slice1 1
5194 #define EitherSlice 0
5195 uint32_t SliceDestinationSelect;
5196 #define HalfSlice1 2
5197 #define HalfSlice0 1
5198 #define Eitherhalfslice 0
5199 uint32_t HalfSliceDestinationSelect;
5200 uint32_t IndirectDataLength;
5201 __gen_address_type IndirectDataStartAddress;
5202 uint32_t ScoredboardY;
5203 uint32_t ScoreboardX;
5204 uint32_t ScoreboardColor;
5205 uint32_t ScoreboardMask;
5206 /* variable length fields follow */
5207 };
5208
5209 static inline void
5210 GEN75_MEDIA_OBJECT_pack(__gen_user_data *data, void * restrict dst,
5211 const struct GEN75_MEDIA_OBJECT * restrict values)
5212 {
5213 uint32_t *dw = (uint32_t * restrict) dst;
5214
5215 dw[0] =
5216 __gen_field(values->CommandType, 29, 31) |
5217 __gen_field(values->MediaCommandPipeline, 27, 28) |
5218 __gen_field(values->MediaCommandOpcode, 24, 26) |
5219 __gen_field(values->MediaCommandSubOpcode, 16, 23) |
5220 __gen_field(values->DwordLength, 0, 15) |
5221 0;
5222
5223 dw[1] =
5224 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
5225 0;
5226
5227 dw[2] =
5228 __gen_field(values->ChildrenPresent, 31, 31) |
5229 __gen_field(values->ThreadSynchronization, 24, 24) |
5230 __gen_field(values->UseScoreboard, 21, 21) |
5231 __gen_field(values->SliceDestinationSelect, 19, 19) |
5232 __gen_field(values->HalfSliceDestinationSelect, 17, 18) |
5233 __gen_field(values->IndirectDataLength, 0, 16) |
5234 0;
5235
5236 uint32_t dw3 =
5237 0;
5238
5239 dw[3] =
5240 __gen_combine_address(data, &dw[3], values->IndirectDataStartAddress, dw3);
5241
5242 dw[4] =
5243 __gen_field(values->ScoredboardY, 16, 24) |
5244 __gen_field(values->ScoreboardX, 0, 8) |
5245 0;
5246
5247 dw[5] =
5248 __gen_field(values->ScoreboardColor, 16, 19) |
5249 __gen_field(values->ScoreboardMask, 0, 7) |
5250 0;
5251
5252 /* variable length fields follow */
5253 }
5254
5255 #define GEN75_MEDIA_OBJECT_PRT_length 0x00000010
5256 #define GEN75_MEDIA_OBJECT_PRT_length_bias 0x00000002
5257 #define GEN75_MEDIA_OBJECT_PRT_header \
5258 .CommandType = 3, \
5259 .Pipeline = 2, \
5260 .MediaCommandOpcode = 1, \
5261 .SubOpcode = 2, \
5262 .DwordLength = 14
5263
5264 struct GEN75_MEDIA_OBJECT_PRT {
5265 uint32_t CommandType;
5266 uint32_t Pipeline;
5267 uint32_t MediaCommandOpcode;
5268 uint32_t SubOpcode;
5269 uint32_t DwordLength;
5270 uint32_t InterfaceDescriptorOffset;
5271 uint32_t ChildrenPresent;
5272 uint32_t PRT_FenceNeeded;
5273 #define Rootthreadqueue 0
5274 #define VFEstateflush 1
5275 uint32_t PRT_FenceType;
5276 uint32_t InlineData;
5277 };
5278
5279 static inline void
5280 GEN75_MEDIA_OBJECT_PRT_pack(__gen_user_data *data, void * restrict dst,
5281 const struct GEN75_MEDIA_OBJECT_PRT * restrict values)
5282 {
5283 uint32_t *dw = (uint32_t * restrict) dst;
5284
5285 dw[0] =
5286 __gen_field(values->CommandType, 29, 31) |
5287 __gen_field(values->Pipeline, 27, 28) |
5288 __gen_field(values->MediaCommandOpcode, 24, 26) |
5289 __gen_field(values->SubOpcode, 16, 23) |
5290 __gen_field(values->DwordLength, 0, 15) |
5291 0;
5292
5293 dw[1] =
5294 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
5295 0;
5296
5297 dw[2] =
5298 __gen_field(values->ChildrenPresent, 31, 31) |
5299 __gen_field(values->PRT_FenceNeeded, 23, 23) |
5300 __gen_field(values->PRT_FenceType, 22, 22) |
5301 0;
5302
5303 dw[3] =
5304 0;
5305
5306 dw[4] =
5307 __gen_field(values->InlineData, 0, 31) |
5308 0;
5309
5310 }
5311
5312 #define GEN75_MEDIA_OBJECT_WALKER_length_bias 0x00000002
5313 #define GEN75_MEDIA_OBJECT_WALKER_header \
5314 .CommandType = 3, \
5315 .Pipeline = 2, \
5316 .MediaCommandOpcode = 1, \
5317 .SubOpcode = 3
5318
5319 struct GEN75_MEDIA_OBJECT_WALKER {
5320 uint32_t CommandType;
5321 uint32_t Pipeline;
5322 uint32_t MediaCommandOpcode;
5323 uint32_t SubOpcode;
5324 uint32_t DwordLength;
5325 uint32_t InterfaceDescriptorOffset;
5326 uint32_t ChildrenPresent;
5327 #define Nothreadsynchronization 0
5328 #define Threaddispatchissynchronizedbythespawnrootthreadmessage 1
5329 uint32_t ThreadSynchronization;
5330 #define Notusingscoreboard 0
5331 #define Usingscoreboard 1
5332 uint32_t UseScoreboard;
5333 uint32_t IndirectDataLength;
5334 uint32_t IndirectDataStartAddress;
5335 uint32_t ScoreboardMask;
5336 uint32_t DualMode;
5337 uint32_t Repel;
5338 uint32_t QuadMode;
5339 uint32_t ColorCountMinusOne;
5340 uint32_t MiddleLoopExtraSteps;
5341 uint32_t LocalMidLoopUnitY;
5342 uint32_t MidLoopUnitX;
5343 uint32_t GlobalLoopExecCount;
5344 uint32_t LocalLoopExecCount;
5345 uint32_t BlockResolutionY;
5346 uint32_t BlockResolutionX;
5347 uint32_t LocalStartY;
5348 uint32_t LocalStartX;
5349 uint32_t LocalOuterLoopStrideY;
5350 uint32_t LocalOuterLoopStrideX;
5351 uint32_t LocalInnerLoopUnitY;
5352 uint32_t LocalInnerLoopUnitX;
5353 uint32_t GlobalResolutionY;
5354 uint32_t GlobalResolutionX;
5355 uint32_t GlobalStartY;
5356 uint32_t GlobalStartX;
5357 uint32_t GlobalOuterLoopStrideY;
5358 uint32_t GlobalOuterLoopStrideX;
5359 uint32_t GlobalInnerLoopUnitY;
5360 uint32_t GlobalInnerLoopUnitX;
5361 /* variable length fields follow */
5362 };
5363
5364 static inline void
5365 GEN75_MEDIA_OBJECT_WALKER_pack(__gen_user_data *data, void * restrict dst,
5366 const struct GEN75_MEDIA_OBJECT_WALKER * restrict values)
5367 {
5368 uint32_t *dw = (uint32_t * restrict) dst;
5369
5370 dw[0] =
5371 __gen_field(values->CommandType, 29, 31) |
5372 __gen_field(values->Pipeline, 27, 28) |
5373 __gen_field(values->MediaCommandOpcode, 24, 26) |
5374 __gen_field(values->SubOpcode, 16, 23) |
5375 __gen_field(values->DwordLength, 0, 15) |
5376 0;
5377
5378 dw[1] =
5379 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
5380 0;
5381
5382 dw[2] =
5383 __gen_field(values->ChildrenPresent, 31, 31) |
5384 __gen_field(values->ThreadSynchronization, 24, 24) |
5385 __gen_field(values->UseScoreboard, 21, 21) |
5386 __gen_field(values->IndirectDataLength, 0, 16) |
5387 0;
5388
5389 dw[3] =
5390 __gen_offset(values->IndirectDataStartAddress, 0, 31) |
5391 0;
5392
5393 dw[4] =
5394 0;
5395
5396 dw[5] =
5397 __gen_field(values->ScoreboardMask, 0, 7) |
5398 0;
5399
5400 dw[6] =
5401 __gen_field(values->DualMode, 31, 31) |
5402 __gen_field(values->Repel, 30, 30) |
5403 __gen_field(values->QuadMode, 29, 29) |
5404 __gen_field(values->ColorCountMinusOne, 24, 27) |
5405 __gen_field(values->MiddleLoopExtraSteps, 16, 20) |
5406 __gen_field(values->LocalMidLoopUnitY, 12, 13) |
5407 __gen_field(values->MidLoopUnitX, 8, 9) |
5408 0;
5409
5410 dw[7] =
5411 __gen_field(values->GlobalLoopExecCount, 16, 25) |
5412 __gen_field(values->LocalLoopExecCount, 0, 9) |
5413 0;
5414
5415 dw[8] =
5416 __gen_field(values->BlockResolutionY, 16, 24) |
5417 __gen_field(values->BlockResolutionX, 0, 8) |
5418 0;
5419
5420 dw[9] =
5421 __gen_field(values->LocalStartY, 16, 24) |
5422 __gen_field(values->LocalStartX, 0, 8) |
5423 0;
5424
5425 dw[10] =
5426 0;
5427
5428 dw[11] =
5429 __gen_field(values->LocalOuterLoopStrideY, 16, 25) |
5430 __gen_field(values->LocalOuterLoopStrideX, 0, 9) |
5431 0;
5432
5433 dw[12] =
5434 __gen_field(values->LocalInnerLoopUnitY, 16, 25) |
5435 __gen_field(values->LocalInnerLoopUnitX, 0, 9) |
5436 0;
5437
5438 dw[13] =
5439 __gen_field(values->GlobalResolutionY, 16, 24) |
5440 __gen_field(values->GlobalResolutionX, 0, 8) |
5441 0;
5442
5443 dw[14] =
5444 __gen_field(values->GlobalStartY, 16, 25) |
5445 __gen_field(values->GlobalStartX, 0, 9) |
5446 0;
5447
5448 dw[15] =
5449 __gen_field(values->GlobalOuterLoopStrideY, 16, 25) |
5450 __gen_field(values->GlobalOuterLoopStrideX, 0, 9) |
5451 0;
5452
5453 dw[16] =
5454 __gen_field(values->GlobalInnerLoopUnitY, 16, 25) |
5455 __gen_field(values->GlobalInnerLoopUnitX, 0, 9) |
5456 0;
5457
5458 /* variable length fields follow */
5459 }
5460
5461 #define GEN75_MEDIA_STATE_FLUSH_length 0x00000002
5462 #define GEN75_MEDIA_STATE_FLUSH_length_bias 0x00000002
5463 #define GEN75_MEDIA_STATE_FLUSH_header \
5464 .CommandType = 3, \
5465 .Pipeline = 2, \
5466 .MediaCommandOpcode = 0, \
5467 .SubOpcode = 4, \
5468 .DwordLength = 0
5469
5470 struct GEN75_MEDIA_STATE_FLUSH {
5471 uint32_t CommandType;
5472 uint32_t Pipeline;
5473 uint32_t MediaCommandOpcode;
5474 uint32_t SubOpcode;
5475 uint32_t DwordLength;
5476 uint32_t DisablePreemption;
5477 uint32_t FlushtoGO;
5478 uint32_t WatermarkRequired;
5479 uint32_t InterfaceDescriptorOffset;
5480 };
5481
5482 static inline void
5483 GEN75_MEDIA_STATE_FLUSH_pack(__gen_user_data *data, void * restrict dst,
5484 const struct GEN75_MEDIA_STATE_FLUSH * restrict values)
5485 {
5486 uint32_t *dw = (uint32_t * restrict) dst;
5487
5488 dw[0] =
5489 __gen_field(values->CommandType, 29, 31) |
5490 __gen_field(values->Pipeline, 27, 28) |
5491 __gen_field(values->MediaCommandOpcode, 24, 26) |
5492 __gen_field(values->SubOpcode, 16, 23) |
5493 __gen_field(values->DwordLength, 0, 15) |
5494 0;
5495
5496 dw[1] =
5497 __gen_field(values->DisablePreemption, 8, 8) |
5498 __gen_field(values->FlushtoGO, 7, 7) |
5499 __gen_field(values->WatermarkRequired, 6, 6) |
5500 __gen_field(values->InterfaceDescriptorOffset, 0, 5) |
5501 0;
5502
5503 }
5504
5505 #define GEN75_MEDIA_VFE_STATE_length 0x00000008
5506 #define GEN75_MEDIA_VFE_STATE_length_bias 0x00000002
5507 #define GEN75_MEDIA_VFE_STATE_header \
5508 .CommandType = 3, \
5509 .Pipeline = 2, \
5510 .MediaCommandOpcode = 0, \
5511 .SubOpcode = 0, \
5512 .DwordLength = 6
5513
5514 struct GEN75_MEDIA_VFE_STATE {
5515 uint32_t CommandType;
5516 uint32_t Pipeline;
5517 uint32_t MediaCommandOpcode;
5518 uint32_t SubOpcode;
5519 uint32_t DwordLength;
5520 uint32_t ScratchSpaceBasePointer;
5521 uint32_t StackSize;
5522 uint32_t PerThreadScratchSpace;
5523 uint32_t MaximumNumberofThreads;
5524 uint32_t NumberofURBEntries;
5525 #define Maintainingtheexistingtimestampstate 0
5526 #define Resettingrelativetimerandlatchingtheglobaltimestamp 1
5527 uint32_t ResetGatewayTimer;
5528 #define MaintainingOpenGatewayForwardMsgCloseGatewayprotocollegacymode 0
5529 #define BypassingOpenGatewayCloseGatewayprotocol 1
5530 uint32_t BypassGatewayControl;
5531 uint32_t GPGPUMode;
5532 uint32_t HalfSliceDisable;
5533 uint32_t URBEntryAllocationSize;
5534 uint32_t CURBEAllocationSize;
5535 #define Scoreboarddisabled 0
5536 #define Scoreboardenabled 1
5537 uint32_t ScoreboardEnable;
5538 #define StallingScoreboard 0
5539 #define NonStallingScoreboard 1
5540 uint32_t ScoreboardType;
5541 uint32_t ScoreboardMask;
5542 uint32_t Scoreboard3DeltaY;
5543 uint32_t Scoreboard3DeltaX;
5544 uint32_t Scoreboard2DeltaY;
5545 uint32_t Scoreboard2DeltaX;
5546 uint32_t Scoreboard1DeltaY;
5547 uint32_t Scoreboard1DeltaX;
5548 uint32_t Scoreboard0DeltaY;
5549 uint32_t Scoreboard0DeltaX;
5550 uint32_t Scoreboard7DeltaY;
5551 uint32_t Scoreboard7DeltaX;
5552 uint32_t Scoreboard6DeltaY;
5553 uint32_t Scoreboard6DeltaX;
5554 uint32_t Scoreboard5DeltaY;
5555 uint32_t Scoreboard5DeltaX;
5556 uint32_t Scoreboard4DeltaY;
5557 uint32_t Scoreboard4DeltaX;
5558 };
5559
5560 static inline void
5561 GEN75_MEDIA_VFE_STATE_pack(__gen_user_data *data, void * restrict dst,
5562 const struct GEN75_MEDIA_VFE_STATE * restrict values)
5563 {
5564 uint32_t *dw = (uint32_t * restrict) dst;
5565
5566 dw[0] =
5567 __gen_field(values->CommandType, 29, 31) |
5568 __gen_field(values->Pipeline, 27, 28) |
5569 __gen_field(values->MediaCommandOpcode, 24, 26) |
5570 __gen_field(values->SubOpcode, 16, 23) |
5571 __gen_field(values->DwordLength, 0, 15) |
5572 0;
5573
5574 dw[1] =
5575 __gen_offset(values->ScratchSpaceBasePointer, 10, 31) |
5576 __gen_field(values->StackSize, 4, 7) |
5577 __gen_field(values->PerThreadScratchSpace, 0, 3) |
5578 0;
5579
5580 dw[2] =
5581 __gen_field(values->MaximumNumberofThreads, 16, 31) |
5582 __gen_field(values->NumberofURBEntries, 8, 15) |
5583 __gen_field(values->ResetGatewayTimer, 7, 7) |
5584 __gen_field(values->BypassGatewayControl, 6, 6) |
5585 __gen_field(values->GPGPUMode, 2, 2) |
5586 0;
5587
5588 dw[3] =
5589 __gen_field(values->HalfSliceDisable, 0, 1) |
5590 0;
5591
5592 dw[4] =
5593 __gen_field(values->URBEntryAllocationSize, 16, 31) |
5594 __gen_field(values->CURBEAllocationSize, 0, 15) |
5595 0;
5596
5597 dw[5] =
5598 __gen_field(values->ScoreboardEnable, 31, 31) |
5599 __gen_field(values->ScoreboardType, 30, 30) |
5600 __gen_field(values->ScoreboardMask, 0, 7) |
5601 0;
5602
5603 dw[6] =
5604 __gen_field(values->Scoreboard3DeltaY, 28, 31) |
5605 __gen_field(values->Scoreboard3DeltaX, 24, 27) |
5606 __gen_field(values->Scoreboard2DeltaY, 20, 23) |
5607 __gen_field(values->Scoreboard2DeltaX, 16, 19) |
5608 __gen_field(values->Scoreboard1DeltaY, 12, 15) |
5609 __gen_field(values->Scoreboard1DeltaX, 8, 11) |
5610 __gen_field(values->Scoreboard0DeltaY, 4, 7) |
5611 __gen_field(values->Scoreboard0DeltaX, 0, 3) |
5612 0;
5613
5614 dw[7] =
5615 __gen_field(values->Scoreboard7DeltaY, 28, 31) |
5616 __gen_field(values->Scoreboard7DeltaX, 24, 27) |
5617 __gen_field(values->Scoreboard6DeltaY, 20, 23) |
5618 __gen_field(values->Scoreboard6DeltaX, 16, 19) |
5619 __gen_field(values->Scoreboard5DeltaY, 12, 15) |
5620 __gen_field(values->Scoreboard5DeltaX, 8, 11) |
5621 __gen_field(values->Scoreboard4DeltaY, 4, 7) |
5622 __gen_field(values->Scoreboard4DeltaX, 0, 3) |
5623 0;
5624
5625 }
5626
5627 #define GEN75_MI_ARB_CHECK_length 0x00000001
5628 #define GEN75_MI_ARB_CHECK_length_bias 0x00000001
5629 #define GEN75_MI_ARB_CHECK_header \
5630 .CommandType = 0, \
5631 .MICommandOpcode = 5
5632
5633 struct GEN75_MI_ARB_CHECK {
5634 uint32_t CommandType;
5635 uint32_t MICommandOpcode;
5636 };
5637
5638 static inline void
5639 GEN75_MI_ARB_CHECK_pack(__gen_user_data *data, void * restrict dst,
5640 const struct GEN75_MI_ARB_CHECK * restrict values)
5641 {
5642 uint32_t *dw = (uint32_t * restrict) dst;
5643
5644 dw[0] =
5645 __gen_field(values->CommandType, 29, 31) |
5646 __gen_field(values->MICommandOpcode, 23, 28) |
5647 0;
5648
5649 }
5650
5651 #define GEN75_MI_ARB_ON_OFF_length 0x00000001
5652 #define GEN75_MI_ARB_ON_OFF_length_bias 0x00000001
5653 #define GEN75_MI_ARB_ON_OFF_header \
5654 .CommandType = 0, \
5655 .MICommandOpcode = 8
5656
5657 struct GEN75_MI_ARB_ON_OFF {
5658 uint32_t CommandType;
5659 uint32_t MICommandOpcode;
5660 uint32_t ArbitrationEnable;
5661 };
5662
5663 static inline void
5664 GEN75_MI_ARB_ON_OFF_pack(__gen_user_data *data, void * restrict dst,
5665 const struct GEN75_MI_ARB_ON_OFF * restrict values)
5666 {
5667 uint32_t *dw = (uint32_t * restrict) dst;
5668
5669 dw[0] =
5670 __gen_field(values->CommandType, 29, 31) |
5671 __gen_field(values->MICommandOpcode, 23, 28) |
5672 __gen_field(values->ArbitrationEnable, 0, 0) |
5673 0;
5674
5675 }
5676
5677 #define GEN75_MI_BATCH_BUFFER_END_length 0x00000001
5678 #define GEN75_MI_BATCH_BUFFER_END_length_bias 0x00000001
5679 #define GEN75_MI_BATCH_BUFFER_END_header \
5680 .CommandType = 0, \
5681 .MICommandOpcode = 10
5682
5683 struct GEN75_MI_BATCH_BUFFER_END {
5684 uint32_t CommandType;
5685 uint32_t MICommandOpcode;
5686 };
5687
5688 static inline void
5689 GEN75_MI_BATCH_BUFFER_END_pack(__gen_user_data *data, void * restrict dst,
5690 const struct GEN75_MI_BATCH_BUFFER_END * restrict values)
5691 {
5692 uint32_t *dw = (uint32_t * restrict) dst;
5693
5694 dw[0] =
5695 __gen_field(values->CommandType, 29, 31) |
5696 __gen_field(values->MICommandOpcode, 23, 28) |
5697 0;
5698
5699 }
5700
5701 #define GEN75_MI_BATCH_BUFFER_START_length 0x00000002
5702 #define GEN75_MI_BATCH_BUFFER_START_length_bias 0x00000002
5703 #define GEN75_MI_BATCH_BUFFER_START_header \
5704 .CommandType = 0, \
5705 .MICommandOpcode = 49, \
5706 .DwordLength = 0
5707
5708 struct GEN75_MI_BATCH_BUFFER_START {
5709 uint32_t CommandType;
5710 uint32_t MICommandOpcode;
5711 #define _1stlevelbatch 0
5712 #define _2ndlevelbatch 1
5713 uint32_t _2ndLevelBatchBuffer;
5714 uint32_t AddOffsetEnable;
5715 uint32_t PredicationEnable;
5716 uint32_t NonPrivileged;
5717 uint32_t ClearCommandBufferEnable;
5718 uint32_t ResourceStreamerEnable;
5719 #define ASI_GGTT 0
5720 #define ASI_PPGTT 1
5721 uint32_t AddressSpaceIndicator;
5722 uint32_t DwordLength;
5723 __gen_address_type BatchBufferStartAddress;
5724 };
5725
5726 static inline void
5727 GEN75_MI_BATCH_BUFFER_START_pack(__gen_user_data *data, void * restrict dst,
5728 const struct GEN75_MI_BATCH_BUFFER_START * restrict values)
5729 {
5730 uint32_t *dw = (uint32_t * restrict) dst;
5731
5732 dw[0] =
5733 __gen_field(values->CommandType, 29, 31) |
5734 __gen_field(values->MICommandOpcode, 23, 28) |
5735 __gen_field(values->_2ndLevelBatchBuffer, 22, 22) |
5736 __gen_field(values->AddOffsetEnable, 16, 16) |
5737 __gen_field(values->PredicationEnable, 15, 15) |
5738 __gen_field(values->NonPrivileged, 13, 13) |
5739 __gen_field(values->ClearCommandBufferEnable, 11, 11) |
5740 __gen_field(values->ResourceStreamerEnable, 10, 10) |
5741 __gen_field(values->AddressSpaceIndicator, 8, 8) |
5742 __gen_field(values->DwordLength, 0, 7) |
5743 0;
5744
5745 uint32_t dw1 =
5746 0;
5747
5748 dw[1] =
5749 __gen_combine_address(data, &dw[1], values->BatchBufferStartAddress, dw1);
5750
5751 }
5752
5753 #define GEN75_MI_CLFLUSH_length_bias 0x00000002
5754 #define GEN75_MI_CLFLUSH_header \
5755 .CommandType = 0, \
5756 .MICommandOpcode = 39
5757
5758 struct GEN75_MI_CLFLUSH {
5759 uint32_t CommandType;
5760 uint32_t MICommandOpcode;
5761 #define PerProcessGraphicsAddress 0
5762 #define GlobalGraphicsAddress 1
5763 uint32_t UseGlobalGTT;
5764 uint32_t DwordLength;
5765 __gen_address_type PageBaseAddress;
5766 uint32_t StartingCachelineOffset;
5767 __gen_address_type PageBaseAddressHigh;
5768 /* variable length fields follow */
5769 };
5770
5771 static inline void
5772 GEN75_MI_CLFLUSH_pack(__gen_user_data *data, void * restrict dst,
5773 const struct GEN75_MI_CLFLUSH * restrict values)
5774 {
5775 uint32_t *dw = (uint32_t * restrict) dst;
5776
5777 dw[0] =
5778 __gen_field(values->CommandType, 29, 31) |
5779 __gen_field(values->MICommandOpcode, 23, 28) |
5780 __gen_field(values->UseGlobalGTT, 22, 22) |
5781 __gen_field(values->DwordLength, 0, 9) |
5782 0;
5783
5784 uint32_t dw1 =
5785 __gen_field(values->StartingCachelineOffset, 6, 11) |
5786 0;
5787
5788 dw[1] =
5789 __gen_combine_address(data, &dw[1], values->PageBaseAddress, dw1);
5790
5791 uint32_t dw2 =
5792 0;
5793
5794 dw[2] =
5795 __gen_combine_address(data, &dw[2], values->PageBaseAddressHigh, dw2);
5796
5797 /* variable length fields follow */
5798 }
5799
5800 #define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_length 0x00000002
5801 #define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_length_bias 0x00000002
5802 #define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_header\
5803 .CommandType = 0, \
5804 .MICommandOpcode = 54, \
5805 .UseGlobalGTT = 0, \
5806 .CompareSemaphore = 0, \
5807 .DwordLength = 0
5808
5809 struct GEN75_MI_CONDITIONAL_BATCH_BUFFER_END {
5810 uint32_t CommandType;
5811 uint32_t MICommandOpcode;
5812 uint32_t UseGlobalGTT;
5813 uint32_t CompareSemaphore;
5814 uint32_t DwordLength;
5815 uint32_t CompareDataDword;
5816 __gen_address_type CompareAddress;
5817 };
5818
5819 static inline void
5820 GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_pack(__gen_user_data *data, void * restrict dst,
5821 const struct GEN75_MI_CONDITIONAL_BATCH_BUFFER_END * restrict values)
5822 {
5823 uint32_t *dw = (uint32_t * restrict) dst;
5824
5825 dw[0] =
5826 __gen_field(values->CommandType, 29, 31) |
5827 __gen_field(values->MICommandOpcode, 23, 28) |
5828 __gen_field(values->UseGlobalGTT, 22, 22) |
5829 __gen_field(values->CompareSemaphore, 21, 21) |
5830 __gen_field(values->DwordLength, 0, 7) |
5831 0;
5832
5833 dw[1] =
5834 __gen_field(values->CompareDataDword, 0, 31) |
5835 0;
5836
5837 uint32_t dw2 =
5838 0;
5839
5840 dw[2] =
5841 __gen_combine_address(data, &dw[2], values->CompareAddress, dw2);
5842
5843 }
5844
5845 #define GEN75_MI_FLUSH_length 0x00000001
5846 #define GEN75_MI_FLUSH_length_bias 0x00000001
5847 #define GEN75_MI_FLUSH_header \
5848 .CommandType = 0, \
5849 .MICommandOpcode = 4
5850
5851 struct GEN75_MI_FLUSH {
5852 uint32_t CommandType;
5853 uint32_t MICommandOpcode;
5854 uint32_t IndirectStatePointersDisable;
5855 uint32_t GenericMediaStateClear;
5856 #define DontReset 0
5857 #define Reset 1
5858 uint32_t GlobalSnapshotCountReset;
5859 #define Flush 0
5860 #define DontFlush 1
5861 uint32_t RenderCacheFlushInhibit;
5862 #define DontInvalidate 0
5863 #define Invalidate 1
5864 uint32_t StateInstructionCacheInvalidate;
5865 };
5866
5867 static inline void
5868 GEN75_MI_FLUSH_pack(__gen_user_data *data, void * restrict dst,
5869 const struct GEN75_MI_FLUSH * restrict values)
5870 {
5871 uint32_t *dw = (uint32_t * restrict) dst;
5872
5873 dw[0] =
5874 __gen_field(values->CommandType, 29, 31) |
5875 __gen_field(values->MICommandOpcode, 23, 28) |
5876 __gen_field(values->IndirectStatePointersDisable, 5, 5) |
5877 __gen_field(values->GenericMediaStateClear, 4, 4) |
5878 __gen_field(values->GlobalSnapshotCountReset, 3, 3) |
5879 __gen_field(values->RenderCacheFlushInhibit, 2, 2) |
5880 __gen_field(values->StateInstructionCacheInvalidate, 1, 1) |
5881 0;
5882
5883 }
5884
5885 #define GEN75_MI_LOAD_REGISTER_IMM_length 0x00000003
5886 #define GEN75_MI_LOAD_REGISTER_IMM_length_bias 0x00000002
5887 #define GEN75_MI_LOAD_REGISTER_IMM_header \
5888 .CommandType = 0, \
5889 .MICommandOpcode = 34, \
5890 .DwordLength = 1
5891
5892 struct GEN75_MI_LOAD_REGISTER_IMM {
5893 uint32_t CommandType;
5894 uint32_t MICommandOpcode;
5895 uint32_t ByteWriteDisables;
5896 uint32_t DwordLength;
5897 uint32_t RegisterOffset;
5898 uint32_t DataDWord;
5899 };
5900
5901 static inline void
5902 GEN75_MI_LOAD_REGISTER_IMM_pack(__gen_user_data *data, void * restrict dst,
5903 const struct GEN75_MI_LOAD_REGISTER_IMM * restrict values)
5904 {
5905 uint32_t *dw = (uint32_t * restrict) dst;
5906
5907 dw[0] =
5908 __gen_field(values->CommandType, 29, 31) |
5909 __gen_field(values->MICommandOpcode, 23, 28) |
5910 __gen_field(values->ByteWriteDisables, 8, 11) |
5911 __gen_field(values->DwordLength, 0, 7) |
5912 0;
5913
5914 dw[1] =
5915 __gen_offset(values->RegisterOffset, 2, 22) |
5916 0;
5917
5918 dw[2] =
5919 __gen_field(values->DataDWord, 0, 31) |
5920 0;
5921
5922 }
5923
5924 #define GEN75_MI_LOAD_REGISTER_MEM_length 0x00000003
5925 #define GEN75_MI_LOAD_REGISTER_MEM_length_bias 0x00000002
5926 #define GEN75_MI_LOAD_REGISTER_MEM_header \
5927 .CommandType = 0, \
5928 .MICommandOpcode = 41, \
5929 .DwordLength = 1
5930
5931 struct GEN75_MI_LOAD_REGISTER_MEM {
5932 uint32_t CommandType;
5933 uint32_t MICommandOpcode;
5934 uint32_t UseGlobalGTT;
5935 uint32_t AsyncModeEnable;
5936 uint32_t DwordLength;
5937 uint32_t RegisterAddress;
5938 __gen_address_type MemoryAddress;
5939 };
5940
5941 static inline void
5942 GEN75_MI_LOAD_REGISTER_MEM_pack(__gen_user_data *data, void * restrict dst,
5943 const struct GEN75_MI_LOAD_REGISTER_MEM * restrict values)
5944 {
5945 uint32_t *dw = (uint32_t * restrict) dst;
5946
5947 dw[0] =
5948 __gen_field(values->CommandType, 29, 31) |
5949 __gen_field(values->MICommandOpcode, 23, 28) |
5950 __gen_field(values->UseGlobalGTT, 22, 22) |
5951 __gen_field(values->AsyncModeEnable, 21, 21) |
5952 __gen_field(values->DwordLength, 0, 7) |
5953 0;
5954
5955 dw[1] =
5956 __gen_offset(values->RegisterAddress, 2, 22) |
5957 0;
5958
5959 uint32_t dw2 =
5960 0;
5961
5962 dw[2] =
5963 __gen_combine_address(data, &dw[2], values->MemoryAddress, dw2);
5964
5965 }
5966
5967 #define GEN75_MI_LOAD_REGISTER_REG_length 0x00000003
5968 #define GEN75_MI_LOAD_REGISTER_REG_length_bias 0x00000002
5969 #define GEN75_MI_LOAD_REGISTER_REG_header \
5970 .CommandType = 0, \
5971 .MICommandOpcode = 42, \
5972 .DwordLength = 1
5973
5974 struct GEN75_MI_LOAD_REGISTER_REG {
5975 uint32_t CommandType;
5976 uint32_t MICommandOpcode;
5977 uint32_t DwordLength;
5978 uint32_t SourceRegisterAddress;
5979 uint32_t DestinationRegisterAddress;
5980 };
5981
5982 static inline void
5983 GEN75_MI_LOAD_REGISTER_REG_pack(__gen_user_data *data, void * restrict dst,
5984 const struct GEN75_MI_LOAD_REGISTER_REG * restrict values)
5985 {
5986 uint32_t *dw = (uint32_t * restrict) dst;
5987
5988 dw[0] =
5989 __gen_field(values->CommandType, 29, 31) |
5990 __gen_field(values->MICommandOpcode, 23, 28) |
5991 __gen_field(values->DwordLength, 0, 7) |
5992 0;
5993
5994 dw[1] =
5995 __gen_offset(values->SourceRegisterAddress, 2, 22) |
5996 0;
5997
5998 dw[2] =
5999 __gen_offset(values->DestinationRegisterAddress, 2, 22) |
6000 0;
6001
6002 }
6003
6004 #define GEN75_MI_LOAD_SCAN_LINES_EXCL_length 0x00000002
6005 #define GEN75_MI_LOAD_SCAN_LINES_EXCL_length_bias 0x00000002
6006 #define GEN75_MI_LOAD_SCAN_LINES_EXCL_header \
6007 .CommandType = 0, \
6008 .MICommandOpcode = 19, \
6009 .DwordLength = 0
6010
6011 struct GEN75_MI_LOAD_SCAN_LINES_EXCL {
6012 uint32_t CommandType;
6013 uint32_t MICommandOpcode;
6014 #define DisplayPlaneA 0
6015 #define DisplayPlaneB 1
6016 #define DisplayPlaneC 4
6017 uint32_t DisplayPlaneSelect;
6018 uint32_t DwordLength;
6019 uint32_t StartScanLineNumber;
6020 uint32_t EndScanLineNumber;
6021 };
6022
6023 static inline void
6024 GEN75_MI_LOAD_SCAN_LINES_EXCL_pack(__gen_user_data *data, void * restrict dst,
6025 const struct GEN75_MI_LOAD_SCAN_LINES_EXCL * restrict values)
6026 {
6027 uint32_t *dw = (uint32_t * restrict) dst;
6028
6029 dw[0] =
6030 __gen_field(values->CommandType, 29, 31) |
6031 __gen_field(values->MICommandOpcode, 23, 28) |
6032 __gen_field(values->DisplayPlaneSelect, 19, 21) |
6033 __gen_field(values->DwordLength, 0, 5) |
6034 0;
6035
6036 dw[1] =
6037 __gen_field(values->StartScanLineNumber, 16, 28) |
6038 __gen_field(values->EndScanLineNumber, 0, 12) |
6039 0;
6040
6041 }
6042
6043 #define GEN75_MI_LOAD_SCAN_LINES_INCL_length 0x00000002
6044 #define GEN75_MI_LOAD_SCAN_LINES_INCL_length_bias 0x00000002
6045 #define GEN75_MI_LOAD_SCAN_LINES_INCL_header \
6046 .CommandType = 0, \
6047 .MICommandOpcode = 18, \
6048 .DwordLength = 0
6049
6050 struct GEN75_MI_LOAD_SCAN_LINES_INCL {
6051 uint32_t CommandType;
6052 uint32_t MICommandOpcode;
6053 #define DisplayPlaneA 0
6054 #define DisplayPlaneB 1
6055 #define DisplayPlaneC 4
6056 uint32_t DisplayPlaneSelect;
6057 uint32_t DwordLength;
6058 uint32_t StartScanLineNumber;
6059 uint32_t EndScanLineNumber;
6060 };
6061
6062 static inline void
6063 GEN75_MI_LOAD_SCAN_LINES_INCL_pack(__gen_user_data *data, void * restrict dst,
6064 const struct GEN75_MI_LOAD_SCAN_LINES_INCL * restrict values)
6065 {
6066 uint32_t *dw = (uint32_t * restrict) dst;
6067
6068 dw[0] =
6069 __gen_field(values->CommandType, 29, 31) |
6070 __gen_field(values->MICommandOpcode, 23, 28) |
6071 __gen_field(values->DisplayPlaneSelect, 19, 21) |
6072 __gen_field(values->DwordLength, 0, 5) |
6073 0;
6074
6075 dw[1] =
6076 __gen_field(values->StartScanLineNumber, 16, 28) |
6077 __gen_field(values->EndScanLineNumber, 0, 12) |
6078 0;
6079
6080 }
6081
6082 #define GEN75_MI_LOAD_URB_MEM_length 0x00000003
6083 #define GEN75_MI_LOAD_URB_MEM_length_bias 0x00000002
6084 #define GEN75_MI_LOAD_URB_MEM_header \
6085 .CommandType = 0, \
6086 .MICommandOpcode = 44, \
6087 .DwordLength = 1
6088
6089 struct GEN75_MI_LOAD_URB_MEM {
6090 uint32_t CommandType;
6091 uint32_t MICommandOpcode;
6092 uint32_t DwordLength;
6093 uint32_t URBAddress;
6094 __gen_address_type MemoryAddress;
6095 };
6096
6097 static inline void
6098 GEN75_MI_LOAD_URB_MEM_pack(__gen_user_data *data, void * restrict dst,
6099 const struct GEN75_MI_LOAD_URB_MEM * restrict values)
6100 {
6101 uint32_t *dw = (uint32_t * restrict) dst;
6102
6103 dw[0] =
6104 __gen_field(values->CommandType, 29, 31) |
6105 __gen_field(values->MICommandOpcode, 23, 28) |
6106 __gen_field(values->DwordLength, 0, 7) |
6107 0;
6108
6109 dw[1] =
6110 __gen_field(values->URBAddress, 2, 14) |
6111 0;
6112
6113 uint32_t dw2 =
6114 0;
6115
6116 dw[2] =
6117 __gen_combine_address(data, &dw[2], values->MemoryAddress, dw2);
6118
6119 }
6120
6121 #define GEN75_MI_MATH_length_bias 0x00000002
6122 #define GEN75_MI_MATH_header \
6123 .CommandType = 0, \
6124 .MICommandOpcode = 26
6125
6126 struct GEN75_MI_MATH {
6127 uint32_t CommandType;
6128 uint32_t MICommandOpcode;
6129 uint32_t DwordLength;
6130 uint32_t ALUINSTRUCTION1;
6131 uint32_t ALUINSTRUCTION2;
6132 /* variable length fields follow */
6133 };
6134
6135 static inline void
6136 GEN75_MI_MATH_pack(__gen_user_data *data, void * restrict dst,
6137 const struct GEN75_MI_MATH * restrict values)
6138 {
6139 uint32_t *dw = (uint32_t * restrict) dst;
6140
6141 dw[0] =
6142 __gen_field(values->CommandType, 29, 31) |
6143 __gen_field(values->MICommandOpcode, 23, 28) |
6144 __gen_field(values->DwordLength, 0, 5) |
6145 0;
6146
6147 dw[1] =
6148 __gen_field(values->ALUINSTRUCTION1, 0, 31) |
6149 0;
6150
6151 dw[2] =
6152 __gen_field(values->ALUINSTRUCTION2, 0, 31) |
6153 0;
6154
6155 /* variable length fields follow */
6156 }
6157
6158 #define GEN75_MI_NOOP_length 0x00000001
6159 #define GEN75_MI_NOOP_length_bias 0x00000001
6160 #define GEN75_MI_NOOP_header \
6161 .CommandType = 0, \
6162 .MICommandOpcode = 0
6163
6164 struct GEN75_MI_NOOP {
6165 uint32_t CommandType;
6166 uint32_t MICommandOpcode;
6167 uint32_t IdentificationNumberRegisterWriteEnable;
6168 uint32_t IdentificationNumber;
6169 };
6170
6171 static inline void
6172 GEN75_MI_NOOP_pack(__gen_user_data *data, void * restrict dst,
6173 const struct GEN75_MI_NOOP * restrict values)
6174 {
6175 uint32_t *dw = (uint32_t * restrict) dst;
6176
6177 dw[0] =
6178 __gen_field(values->CommandType, 29, 31) |
6179 __gen_field(values->MICommandOpcode, 23, 28) |
6180 __gen_field(values->IdentificationNumberRegisterWriteEnable, 22, 22) |
6181 __gen_field(values->IdentificationNumber, 0, 21) |
6182 0;
6183
6184 }
6185
6186 #define GEN75_MI_PREDICATE_length 0x00000001
6187 #define GEN75_MI_PREDICATE_length_bias 0x00000001
6188 #define GEN75_MI_PREDICATE_header \
6189 .CommandType = 0, \
6190 .MICommandOpcode = 12
6191
6192 struct GEN75_MI_PREDICATE {
6193 uint32_t CommandType;
6194 uint32_t MICommandOpcode;
6195 #define KEEP 0
6196 #define LOAD 2
6197 #define LOADINV 3
6198 uint32_t LoadOperation;
6199 #define COMBINE_SET 0
6200 #define COMBINE_AND 1
6201 #define COMBINE_OR 2
6202 #define COMBINE_XOR 3
6203 uint32_t CombineOperation;
6204 #define COMPARE_SRCS_EQUAL 2
6205 #define COMPARE_DELTAS_EQUAL 3
6206 uint32_t CompareOperation;
6207 };
6208
6209 static inline void
6210 GEN75_MI_PREDICATE_pack(__gen_user_data *data, void * restrict dst,
6211 const struct GEN75_MI_PREDICATE * restrict values)
6212 {
6213 uint32_t *dw = (uint32_t * restrict) dst;
6214
6215 dw[0] =
6216 __gen_field(values->CommandType, 29, 31) |
6217 __gen_field(values->MICommandOpcode, 23, 28) |
6218 __gen_field(values->LoadOperation, 6, 7) |
6219 __gen_field(values->CombineOperation, 3, 4) |
6220 __gen_field(values->CompareOperation, 0, 1) |
6221 0;
6222
6223 }
6224
6225 #define GEN75_MI_REPORT_HEAD_length 0x00000001
6226 #define GEN75_MI_REPORT_HEAD_length_bias 0x00000001
6227 #define GEN75_MI_REPORT_HEAD_header \
6228 .CommandType = 0, \
6229 .MICommandOpcode = 7
6230
6231 struct GEN75_MI_REPORT_HEAD {
6232 uint32_t CommandType;
6233 uint32_t MICommandOpcode;
6234 };
6235
6236 static inline void
6237 GEN75_MI_REPORT_HEAD_pack(__gen_user_data *data, void * restrict dst,
6238 const struct GEN75_MI_REPORT_HEAD * restrict values)
6239 {
6240 uint32_t *dw = (uint32_t * restrict) dst;
6241
6242 dw[0] =
6243 __gen_field(values->CommandType, 29, 31) |
6244 __gen_field(values->MICommandOpcode, 23, 28) |
6245 0;
6246
6247 }
6248
6249 #define GEN75_MI_RS_CONTEXT_length 0x00000001
6250 #define GEN75_MI_RS_CONTEXT_length_bias 0x00000001
6251 #define GEN75_MI_RS_CONTEXT_header \
6252 .CommandType = 0, \
6253 .MICommandOpcode = 15
6254
6255 struct GEN75_MI_RS_CONTEXT {
6256 uint32_t CommandType;
6257 uint32_t MICommandOpcode;
6258 #define Restore 0
6259 #define Save 1
6260 uint32_t ResourceStreamerSave;
6261 };
6262
6263 static inline void
6264 GEN75_MI_RS_CONTEXT_pack(__gen_user_data *data, void * restrict dst,
6265 const struct GEN75_MI_RS_CONTEXT * restrict values)
6266 {
6267 uint32_t *dw = (uint32_t * restrict) dst;
6268
6269 dw[0] =
6270 __gen_field(values->CommandType, 29, 31) |
6271 __gen_field(values->MICommandOpcode, 23, 28) |
6272 __gen_field(values->ResourceStreamerSave, 0, 0) |
6273 0;
6274
6275 }
6276
6277 #define GEN75_MI_RS_CONTROL_length 0x00000001
6278 #define GEN75_MI_RS_CONTROL_length_bias 0x00000001
6279 #define GEN75_MI_RS_CONTROL_header \
6280 .CommandType = 0, \
6281 .MICommandOpcode = 6
6282
6283 struct GEN75_MI_RS_CONTROL {
6284 uint32_t CommandType;
6285 uint32_t MICommandOpcode;
6286 #define Stop 0
6287 #define Start 1
6288 uint32_t ResourceStreamerControl;
6289 };
6290
6291 static inline void
6292 GEN75_MI_RS_CONTROL_pack(__gen_user_data *data, void * restrict dst,
6293 const struct GEN75_MI_RS_CONTROL * restrict values)
6294 {
6295 uint32_t *dw = (uint32_t * restrict) dst;
6296
6297 dw[0] =
6298 __gen_field(values->CommandType, 29, 31) |
6299 __gen_field(values->MICommandOpcode, 23, 28) |
6300 __gen_field(values->ResourceStreamerControl, 0, 0) |
6301 0;
6302
6303 }
6304
6305 #define GEN75_MI_RS_STORE_DATA_IMM_length 0x00000004
6306 #define GEN75_MI_RS_STORE_DATA_IMM_length_bias 0x00000002
6307 #define GEN75_MI_RS_STORE_DATA_IMM_header \
6308 .CommandType = 0, \
6309 .MICommandOpcode = 43, \
6310 .DwordLength = 2
6311
6312 struct GEN75_MI_RS_STORE_DATA_IMM {
6313 uint32_t CommandType;
6314 uint32_t MICommandOpcode;
6315 uint32_t DwordLength;
6316 __gen_address_type DestinationAddress;
6317 uint32_t CoreModeEnable;
6318 uint32_t DataDWord0;
6319 };
6320
6321 static inline void
6322 GEN75_MI_RS_STORE_DATA_IMM_pack(__gen_user_data *data, void * restrict dst,
6323 const struct GEN75_MI_RS_STORE_DATA_IMM * restrict values)
6324 {
6325 uint32_t *dw = (uint32_t * restrict) dst;
6326
6327 dw[0] =
6328 __gen_field(values->CommandType, 29, 31) |
6329 __gen_field(values->MICommandOpcode, 23, 28) |
6330 __gen_field(values->DwordLength, 0, 7) |
6331 0;
6332
6333 dw[1] =
6334 0;
6335
6336 uint32_t dw2 =
6337 __gen_field(values->CoreModeEnable, 0, 0) |
6338 0;
6339
6340 dw[2] =
6341 __gen_combine_address(data, &dw[2], values->DestinationAddress, dw2);
6342
6343 dw[3] =
6344 __gen_field(values->DataDWord0, 0, 31) |
6345 0;
6346
6347 }
6348
6349 #define GEN75_MI_SEMAPHORE_MBOX_length 0x00000003
6350 #define GEN75_MI_SEMAPHORE_MBOX_length_bias 0x00000002
6351 #define GEN75_MI_SEMAPHORE_MBOX_header \
6352 .CommandType = 0, \
6353 .MICommandOpcode = 22, \
6354 .DwordLength = 1
6355
6356 struct GEN75_MI_SEMAPHORE_MBOX {
6357 uint32_t CommandType;
6358 uint32_t MICommandOpcode;
6359 #define RVSYNC 0
6360 #define RVESYNC 1
6361 #define RBSYNC 2
6362 #define UseGeneralRegisterSelect 3
6363 uint32_t RegisterSelect;
6364 uint32_t GeneralRegisterSelect;
6365 uint32_t DwordLength;
6366 uint32_t SemaphoreDataDword;
6367 };
6368
6369 static inline void
6370 GEN75_MI_SEMAPHORE_MBOX_pack(__gen_user_data *data, void * restrict dst,
6371 const struct GEN75_MI_SEMAPHORE_MBOX * restrict values)
6372 {
6373 uint32_t *dw = (uint32_t * restrict) dst;
6374
6375 dw[0] =
6376 __gen_field(values->CommandType, 29, 31) |
6377 __gen_field(values->MICommandOpcode, 23, 28) |
6378 __gen_field(values->RegisterSelect, 16, 17) |
6379 __gen_field(values->GeneralRegisterSelect, 8, 13) |
6380 __gen_field(values->DwordLength, 0, 7) |
6381 0;
6382
6383 dw[1] =
6384 __gen_field(values->SemaphoreDataDword, 0, 31) |
6385 0;
6386
6387 dw[2] =
6388 0;
6389
6390 }
6391
6392 #define GEN75_MI_SET_CONTEXT_length 0x00000002
6393 #define GEN75_MI_SET_CONTEXT_length_bias 0x00000002
6394 #define GEN75_MI_SET_CONTEXT_header \
6395 .CommandType = 0, \
6396 .MICommandOpcode = 24, \
6397 .DwordLength = 0
6398
6399 struct GEN75_MI_SET_CONTEXT {
6400 uint32_t CommandType;
6401 uint32_t MICommandOpcode;
6402 uint32_t DwordLength;
6403 __gen_address_type LogicalContextAddress;
6404 uint32_t ReservedMustbe1;
6405 uint32_t CoreModeEnable;
6406 uint32_t ResourceStreamerStateSaveEnable;
6407 uint32_t ResourceStreamerStateRestoreEnable;
6408 uint32_t ForceRestore;
6409 uint32_t RestoreInhibit;
6410 };
6411
6412 static inline void
6413 GEN75_MI_SET_CONTEXT_pack(__gen_user_data *data, void * restrict dst,
6414 const struct GEN75_MI_SET_CONTEXT * restrict values)
6415 {
6416 uint32_t *dw = (uint32_t * restrict) dst;
6417
6418 dw[0] =
6419 __gen_field(values->CommandType, 29, 31) |
6420 __gen_field(values->MICommandOpcode, 23, 28) |
6421 __gen_field(values->DwordLength, 0, 7) |
6422 0;
6423
6424 uint32_t dw1 =
6425 __gen_field(values->ReservedMustbe1, 8, 8) |
6426 __gen_field(values->CoreModeEnable, 4, 4) |
6427 __gen_field(values->ResourceStreamerStateSaveEnable, 3, 3) |
6428 __gen_field(values->ResourceStreamerStateRestoreEnable, 2, 2) |
6429 __gen_field(values->ForceRestore, 1, 1) |
6430 __gen_field(values->RestoreInhibit, 0, 0) |
6431 0;
6432
6433 dw[1] =
6434 __gen_combine_address(data, &dw[1], values->LogicalContextAddress, dw1);
6435
6436 }
6437
6438 #define GEN75_MI_SET_PREDICATE_length 0x00000001
6439 #define GEN75_MI_SET_PREDICATE_length_bias 0x00000001
6440 #define GEN75_MI_SET_PREDICATE_header \
6441 .CommandType = 0, \
6442 .MICommandOpcode = 1, \
6443 .PREDICATEENABLE = 6
6444
6445 struct GEN75_MI_SET_PREDICATE {
6446 uint32_t CommandType;
6447 uint32_t MICommandOpcode;
6448 #define PredicateAlways 0
6449 #define PredicateonClear 1
6450 #define PredicateonSet 2
6451 #define PredicateDisable 3
6452 uint32_t PREDICATEENABLE;
6453 };
6454
6455 static inline void
6456 GEN75_MI_SET_PREDICATE_pack(__gen_user_data *data, void * restrict dst,
6457 const struct GEN75_MI_SET_PREDICATE * restrict values)
6458 {
6459 uint32_t *dw = (uint32_t * restrict) dst;
6460
6461 dw[0] =
6462 __gen_field(values->CommandType, 29, 31) |
6463 __gen_field(values->MICommandOpcode, 23, 28) |
6464 __gen_field(values->PREDICATEENABLE, 0, 1) |
6465 0;
6466
6467 }
6468
6469 #define GEN75_MI_STORE_DATA_IMM_length 0x00000004
6470 #define GEN75_MI_STORE_DATA_IMM_length_bias 0x00000002
6471 #define GEN75_MI_STORE_DATA_IMM_header \
6472 .CommandType = 0, \
6473 .MICommandOpcode = 32, \
6474 .DwordLength = 2
6475
6476 struct GEN75_MI_STORE_DATA_IMM {
6477 uint32_t CommandType;
6478 uint32_t MICommandOpcode;
6479 uint32_t UseGlobalGTT;
6480 uint32_t DwordLength;
6481 uint32_t Address;
6482 uint32_t CoreModeEnable;
6483 uint32_t DataDWord0;
6484 uint32_t DataDWord1;
6485 };
6486
6487 static inline void
6488 GEN75_MI_STORE_DATA_IMM_pack(__gen_user_data *data, void * restrict dst,
6489 const struct GEN75_MI_STORE_DATA_IMM * restrict values)
6490 {
6491 uint32_t *dw = (uint32_t * restrict) dst;
6492
6493 dw[0] =
6494 __gen_field(values->CommandType, 29, 31) |
6495 __gen_field(values->MICommandOpcode, 23, 28) |
6496 __gen_field(values->UseGlobalGTT, 22, 22) |
6497 __gen_field(values->DwordLength, 0, 5) |
6498 0;
6499
6500 dw[1] =
6501 0;
6502
6503 dw[2] =
6504 __gen_field(values->Address, 2, 31) |
6505 __gen_field(values->CoreModeEnable, 0, 0) |
6506 0;
6507
6508 dw[3] =
6509 __gen_field(values->DataDWord0, 0, 31) |
6510 0;
6511
6512 dw[4] =
6513 __gen_field(values->DataDWord1, 0, 31) |
6514 0;
6515
6516 }
6517
6518 #define GEN75_MI_STORE_DATA_INDEX_length 0x00000003
6519 #define GEN75_MI_STORE_DATA_INDEX_length_bias 0x00000002
6520 #define GEN75_MI_STORE_DATA_INDEX_header \
6521 .CommandType = 0, \
6522 .MICommandOpcode = 33, \
6523 .DwordLength = 1
6524
6525 struct GEN75_MI_STORE_DATA_INDEX {
6526 uint32_t CommandType;
6527 uint32_t MICommandOpcode;
6528 uint32_t DwordLength;
6529 uint32_t Offset;
6530 uint32_t DataDWord0;
6531 uint32_t DataDWord1;
6532 };
6533
6534 static inline void
6535 GEN75_MI_STORE_DATA_INDEX_pack(__gen_user_data *data, void * restrict dst,
6536 const struct GEN75_MI_STORE_DATA_INDEX * restrict values)
6537 {
6538 uint32_t *dw = (uint32_t * restrict) dst;
6539
6540 dw[0] =
6541 __gen_field(values->CommandType, 29, 31) |
6542 __gen_field(values->MICommandOpcode, 23, 28) |
6543 __gen_field(values->DwordLength, 0, 7) |
6544 0;
6545
6546 dw[1] =
6547 __gen_field(values->Offset, 2, 11) |
6548 0;
6549
6550 dw[2] =
6551 __gen_field(values->DataDWord0, 0, 31) |
6552 0;
6553
6554 dw[3] =
6555 __gen_field(values->DataDWord1, 0, 31) |
6556 0;
6557
6558 }
6559
6560 #define GEN75_MI_STORE_URB_MEM_length 0x00000003
6561 #define GEN75_MI_STORE_URB_MEM_length_bias 0x00000002
6562 #define GEN75_MI_STORE_URB_MEM_header \
6563 .CommandType = 0, \
6564 .MICommandOpcode = 45, \
6565 .DwordLength = 1
6566
6567 struct GEN75_MI_STORE_URB_MEM {
6568 uint32_t CommandType;
6569 uint32_t MICommandOpcode;
6570 uint32_t DwordLength;
6571 uint32_t URBAddress;
6572 __gen_address_type MemoryAddress;
6573 };
6574
6575 static inline void
6576 GEN75_MI_STORE_URB_MEM_pack(__gen_user_data *data, void * restrict dst,
6577 const struct GEN75_MI_STORE_URB_MEM * restrict values)
6578 {
6579 uint32_t *dw = (uint32_t * restrict) dst;
6580
6581 dw[0] =
6582 __gen_field(values->CommandType, 29, 31) |
6583 __gen_field(values->MICommandOpcode, 23, 28) |
6584 __gen_field(values->DwordLength, 0, 7) |
6585 0;
6586
6587 dw[1] =
6588 __gen_field(values->URBAddress, 2, 14) |
6589 0;
6590
6591 uint32_t dw2 =
6592 0;
6593
6594 dw[2] =
6595 __gen_combine_address(data, &dw[2], values->MemoryAddress, dw2);
6596
6597 }
6598
6599 #define GEN75_MI_SUSPEND_FLUSH_length 0x00000001
6600 #define GEN75_MI_SUSPEND_FLUSH_length_bias 0x00000001
6601 #define GEN75_MI_SUSPEND_FLUSH_header \
6602 .CommandType = 0, \
6603 .MICommandOpcode = 11
6604
6605 struct GEN75_MI_SUSPEND_FLUSH {
6606 uint32_t CommandType;
6607 uint32_t MICommandOpcode;
6608 uint32_t SuspendFlush;
6609 };
6610
6611 static inline void
6612 GEN75_MI_SUSPEND_FLUSH_pack(__gen_user_data *data, void * restrict dst,
6613 const struct GEN75_MI_SUSPEND_FLUSH * restrict values)
6614 {
6615 uint32_t *dw = (uint32_t * restrict) dst;
6616
6617 dw[0] =
6618 __gen_field(values->CommandType, 29, 31) |
6619 __gen_field(values->MICommandOpcode, 23, 28) |
6620 __gen_field(values->SuspendFlush, 0, 0) |
6621 0;
6622
6623 }
6624
6625 #define GEN75_MI_TOPOLOGY_FILTER_length 0x00000001
6626 #define GEN75_MI_TOPOLOGY_FILTER_length_bias 0x00000001
6627 #define GEN75_MI_TOPOLOGY_FILTER_header \
6628 .CommandType = 0, \
6629 .MICommandOpcode = 13
6630
6631 struct GEN75_MI_TOPOLOGY_FILTER {
6632 uint32_t CommandType;
6633 uint32_t MICommandOpcode;
6634 uint32_t TopologyFilterValue;
6635 };
6636
6637 static inline void
6638 GEN75_MI_TOPOLOGY_FILTER_pack(__gen_user_data *data, void * restrict dst,
6639 const struct GEN75_MI_TOPOLOGY_FILTER * restrict values)
6640 {
6641 uint32_t *dw = (uint32_t * restrict) dst;
6642
6643 dw[0] =
6644 __gen_field(values->CommandType, 29, 31) |
6645 __gen_field(values->MICommandOpcode, 23, 28) |
6646 __gen_field(values->TopologyFilterValue, 0, 5) |
6647 0;
6648
6649 }
6650
6651 #define GEN75_MI_UPDATE_GTT_length_bias 0x00000002
6652 #define GEN75_MI_UPDATE_GTT_header \
6653 .CommandType = 0, \
6654 .MICommandOpcode = 35
6655
6656 struct GEN75_MI_UPDATE_GTT {
6657 uint32_t CommandType;
6658 uint32_t MICommandOpcode;
6659 #define PerProcessGraphicsAddress 0
6660 #define GlobalGraphicsAddress 1
6661 uint32_t UseGlobalGTT;
6662 uint32_t DwordLength;
6663 __gen_address_type EntryAddress;
6664 /* variable length fields follow */
6665 };
6666
6667 static inline void
6668 GEN75_MI_UPDATE_GTT_pack(__gen_user_data *data, void * restrict dst,
6669 const struct GEN75_MI_UPDATE_GTT * restrict values)
6670 {
6671 uint32_t *dw = (uint32_t * restrict) dst;
6672
6673 dw[0] =
6674 __gen_field(values->CommandType, 29, 31) |
6675 __gen_field(values->MICommandOpcode, 23, 28) |
6676 __gen_field(values->UseGlobalGTT, 22, 22) |
6677 __gen_field(values->DwordLength, 0, 7) |
6678 0;
6679
6680 uint32_t dw1 =
6681 0;
6682
6683 dw[1] =
6684 __gen_combine_address(data, &dw[1], values->EntryAddress, dw1);
6685
6686 /* variable length fields follow */
6687 }
6688
6689 #define GEN75_MI_URB_ATOMIC_ALLOC_length 0x00000001
6690 #define GEN75_MI_URB_ATOMIC_ALLOC_length_bias 0x00000001
6691 #define GEN75_MI_URB_ATOMIC_ALLOC_header \
6692 .CommandType = 0, \
6693 .MICommandOpcode = 9
6694
6695 struct GEN75_MI_URB_ATOMIC_ALLOC {
6696 uint32_t CommandType;
6697 uint32_t MICommandOpcode;
6698 uint32_t URBAtomicStorageOffset;
6699 uint32_t URBAtomicStorageSize;
6700 };
6701
6702 static inline void
6703 GEN75_MI_URB_ATOMIC_ALLOC_pack(__gen_user_data *data, void * restrict dst,
6704 const struct GEN75_MI_URB_ATOMIC_ALLOC * restrict values)
6705 {
6706 uint32_t *dw = (uint32_t * restrict) dst;
6707
6708 dw[0] =
6709 __gen_field(values->CommandType, 29, 31) |
6710 __gen_field(values->MICommandOpcode, 23, 28) |
6711 __gen_field(values->URBAtomicStorageOffset, 12, 19) |
6712 __gen_field(values->URBAtomicStorageSize, 0, 8) |
6713 0;
6714
6715 }
6716
6717 #define GEN75_MI_URB_CLEAR_length 0x00000002
6718 #define GEN75_MI_URB_CLEAR_length_bias 0x00000002
6719 #define GEN75_MI_URB_CLEAR_header \
6720 .CommandType = 0, \
6721 .MICommandOpcode = 25, \
6722 .DwordLength = 0
6723
6724 struct GEN75_MI_URB_CLEAR {
6725 uint32_t CommandType;
6726 uint32_t MICommandOpcode;
6727 uint32_t DwordLength;
6728 uint32_t URBClearLength;
6729 uint32_t URBAddress;
6730 };
6731
6732 static inline void
6733 GEN75_MI_URB_CLEAR_pack(__gen_user_data *data, void * restrict dst,
6734 const struct GEN75_MI_URB_CLEAR * restrict values)
6735 {
6736 uint32_t *dw = (uint32_t * restrict) dst;
6737
6738 dw[0] =
6739 __gen_field(values->CommandType, 29, 31) |
6740 __gen_field(values->MICommandOpcode, 23, 28) |
6741 __gen_field(values->DwordLength, 0, 7) |
6742 0;
6743
6744 dw[1] =
6745 __gen_field(values->URBClearLength, 16, 29) |
6746 __gen_offset(values->URBAddress, 0, 14) |
6747 0;
6748
6749 }
6750
6751 #define GEN75_MI_USER_INTERRUPT_length 0x00000001
6752 #define GEN75_MI_USER_INTERRUPT_length_bias 0x00000001
6753 #define GEN75_MI_USER_INTERRUPT_header \
6754 .CommandType = 0, \
6755 .MICommandOpcode = 2
6756
6757 struct GEN75_MI_USER_INTERRUPT {
6758 uint32_t CommandType;
6759 uint32_t MICommandOpcode;
6760 };
6761
6762 static inline void
6763 GEN75_MI_USER_INTERRUPT_pack(__gen_user_data *data, void * restrict dst,
6764 const struct GEN75_MI_USER_INTERRUPT * restrict values)
6765 {
6766 uint32_t *dw = (uint32_t * restrict) dst;
6767
6768 dw[0] =
6769 __gen_field(values->CommandType, 29, 31) |
6770 __gen_field(values->MICommandOpcode, 23, 28) |
6771 0;
6772
6773 }
6774
6775 #define GEN75_MI_WAIT_FOR_EVENT_length 0x00000001
6776 #define GEN75_MI_WAIT_FOR_EVENT_length_bias 0x00000001
6777 #define GEN75_MI_WAIT_FOR_EVENT_header \
6778 .CommandType = 0, \
6779 .MICommandOpcode = 3
6780
6781 struct GEN75_MI_WAIT_FOR_EVENT {
6782 uint32_t CommandType;
6783 uint32_t MICommandOpcode;
6784 uint32_t DisplayPipeCHorizontalBlankWaitEnable;
6785 uint32_t DisplayPipeCVerticalBlankWaitEnable;
6786 uint32_t DisplaySpriteCFlipPendingWaitEnable;
6787 #define Notenabled 0
6788 uint32_t ConditionCodeWaitSelect;
6789 uint32_t DisplayPlaneCFlipPendingWaitEnable;
6790 uint32_t DisplayPipeCScanLineWaitEnable;
6791 uint32_t DisplayPipeBHorizontalBlankWaitEnable;
6792 uint32_t DisplayPipeBVerticalBlankWaitEnable;
6793 uint32_t DisplaySpriteBFlipPendingWaitEnable;
6794 uint32_t DisplayPlaneBFlipPendingWaitEnable;
6795 uint32_t DisplayPipeBScanLineWaitEnable;
6796 uint32_t DisplayPipeAHorizontalBlankWaitEnable;
6797 uint32_t DisplayPipeAVerticalBlankWaitEnable;
6798 uint32_t DisplaySpriteAFlipPendingWaitEnable;
6799 uint32_t DisplayPlaneAFlipPendingWaitEnable;
6800 uint32_t DisplayPipeAScanLineWaitEnable;
6801 };
6802
6803 static inline void
6804 GEN75_MI_WAIT_FOR_EVENT_pack(__gen_user_data *data, void * restrict dst,
6805 const struct GEN75_MI_WAIT_FOR_EVENT * restrict values)
6806 {
6807 uint32_t *dw = (uint32_t * restrict) dst;
6808
6809 dw[0] =
6810 __gen_field(values->CommandType, 29, 31) |
6811 __gen_field(values->MICommandOpcode, 23, 28) |
6812 __gen_field(values->DisplayPipeCHorizontalBlankWaitEnable, 22, 22) |
6813 __gen_field(values->DisplayPipeCVerticalBlankWaitEnable, 21, 21) |
6814 __gen_field(values->DisplaySpriteCFlipPendingWaitEnable, 20, 20) |
6815 __gen_field(values->ConditionCodeWaitSelect, 16, 19) |
6816 __gen_field(values->DisplayPlaneCFlipPendingWaitEnable, 15, 15) |
6817 __gen_field(values->DisplayPipeCScanLineWaitEnable, 14, 14) |
6818 __gen_field(values->DisplayPipeBHorizontalBlankWaitEnable, 13, 13) |
6819 __gen_field(values->DisplayPipeBVerticalBlankWaitEnable, 11, 11) |
6820 __gen_field(values->DisplaySpriteBFlipPendingWaitEnable, 10, 10) |
6821 __gen_field(values->DisplayPlaneBFlipPendingWaitEnable, 9, 9) |
6822 __gen_field(values->DisplayPipeBScanLineWaitEnable, 8, 8) |
6823 __gen_field(values->DisplayPipeAHorizontalBlankWaitEnable, 5, 5) |
6824 __gen_field(values->DisplayPipeAVerticalBlankWaitEnable, 3, 3) |
6825 __gen_field(values->DisplaySpriteAFlipPendingWaitEnable, 2, 2) |
6826 __gen_field(values->DisplayPlaneAFlipPendingWaitEnable, 1, 1) |
6827 __gen_field(values->DisplayPipeAScanLineWaitEnable, 0, 0) |
6828 0;
6829
6830 }
6831
6832 #define GEN75_PIPE_CONTROL_length 0x00000005
6833 #define GEN75_PIPE_CONTROL_length_bias 0x00000002
6834 #define GEN75_PIPE_CONTROL_header \
6835 .CommandType = 3, \
6836 .CommandSubType = 3, \
6837 ._3DCommandOpcode = 2, \
6838 ._3DCommandSubOpcode = 0, \
6839 .DwordLength = 3
6840
6841 struct GEN75_PIPE_CONTROL {
6842 uint32_t CommandType;
6843 uint32_t CommandSubType;
6844 uint32_t _3DCommandOpcode;
6845 uint32_t _3DCommandSubOpcode;
6846 uint32_t DwordLength;
6847 #define DAT_PPGTT 0
6848 #define DAT_GGTT 1
6849 uint32_t DestinationAddressType;
6850 #define NoLRIOperation 0
6851 #define MMIOWriteImmediateData 1
6852 uint32_t LRIPostSyncOperation;
6853 uint32_t StoreDataIndex;
6854 uint32_t CommandStreamerStallEnable;
6855 #define DontReset 0
6856 #define Reset 1
6857 uint32_t GlobalSnapshotCountReset;
6858 uint32_t TLBInvalidate;
6859 uint32_t GenericMediaStateClear;
6860 #define NoWrite 0
6861 #define WriteImmediateData 1
6862 #define WritePSDepthCount 2
6863 #define WriteTimestamp 3
6864 uint32_t PostSyncOperation;
6865 uint32_t DepthStallEnable;
6866 #define DisableFlush 0
6867 #define EnableFlush 1
6868 uint32_t RenderTargetCacheFlushEnable;
6869 uint32_t InstructionCacheInvalidateEnable;
6870 uint32_t TextureCacheInvalidationEnable;
6871 uint32_t IndirectStatePointersDisable;
6872 uint32_t NotifyEnable;
6873 uint32_t PipeControlFlushEnable;
6874 uint32_t DCFlushEnable;
6875 uint32_t VFCacheInvalidationEnable;
6876 uint32_t ConstantCacheInvalidationEnable;
6877 uint32_t StateCacheInvalidationEnable;
6878 uint32_t StallAtPixelScoreboard;
6879 #define FlushDisabled 0
6880 #define FlushEnabled 1
6881 uint32_t DepthCacheFlushEnable;
6882 __gen_address_type Address;
6883 uint32_t ImmediateData;
6884 uint32_t ImmediateData0;
6885 };
6886
6887 static inline void
6888 GEN75_PIPE_CONTROL_pack(__gen_user_data *data, void * restrict dst,
6889 const struct GEN75_PIPE_CONTROL * restrict values)
6890 {
6891 uint32_t *dw = (uint32_t * restrict) dst;
6892
6893 dw[0] =
6894 __gen_field(values->CommandType, 29, 31) |
6895 __gen_field(values->CommandSubType, 27, 28) |
6896 __gen_field(values->_3DCommandOpcode, 24, 26) |
6897 __gen_field(values->_3DCommandSubOpcode, 16, 23) |
6898 __gen_field(values->DwordLength, 0, 7) |
6899 0;
6900
6901 dw[1] =
6902 __gen_field(values->DestinationAddressType, 24, 24) |
6903 __gen_field(values->LRIPostSyncOperation, 23, 23) |
6904 __gen_field(values->StoreDataIndex, 21, 21) |
6905 __gen_field(values->CommandStreamerStallEnable, 20, 20) |
6906 __gen_field(values->GlobalSnapshotCountReset, 19, 19) |
6907 __gen_field(values->TLBInvalidate, 18, 18) |
6908 __gen_field(values->GenericMediaStateClear, 16, 16) |
6909 __gen_field(values->PostSyncOperation, 14, 15) |
6910 __gen_field(values->DepthStallEnable, 13, 13) |
6911 __gen_field(values->RenderTargetCacheFlushEnable, 12, 12) |
6912 __gen_field(values->InstructionCacheInvalidateEnable, 11, 11) |
6913 __gen_field(values->TextureCacheInvalidationEnable, 10, 10) |
6914 __gen_field(values->IndirectStatePointersDisable, 9, 9) |
6915 __gen_field(values->NotifyEnable, 8, 8) |
6916 __gen_field(values->PipeControlFlushEnable, 7, 7) |
6917 __gen_field(values->DCFlushEnable, 5, 5) |
6918 __gen_field(values->VFCacheInvalidationEnable, 4, 4) |
6919 __gen_field(values->ConstantCacheInvalidationEnable, 3, 3) |
6920 __gen_field(values->StateCacheInvalidationEnable, 2, 2) |
6921 __gen_field(values->StallAtPixelScoreboard, 1, 1) |
6922 __gen_field(values->DepthCacheFlushEnable, 0, 0) |
6923 0;
6924
6925 uint32_t dw2 =
6926 0;
6927
6928 dw[2] =
6929 __gen_combine_address(data, &dw[2], values->Address, dw2);
6930
6931 dw[3] =
6932 __gen_field(values->ImmediateData, 0, 31) |
6933 0;
6934
6935 dw[4] =
6936 __gen_field(values->ImmediateData, 0, 31) |
6937 0;
6938
6939 }
6940
6941 #define GEN75_3DSTATE_CONSTANT_BODY_length 0x00000006
6942
6943 #define GEN75_BINDING_TABLE_EDIT_ENTRY_length 0x00000001
6944
6945 #define GEN75_GATHER_CONSTANT_ENTRY_length 0x00000001
6946
6947 #define GEN75_VERTEX_BUFFER_STATE_length 0x00000004
6948
6949 #define GEN75_VERTEX_ELEMENT_STATE_length 0x00000002
6950
6951 #define GEN75_SO_DECL_ENTRY_length 0x00000002
6952
6953 #define GEN75_SO_DECL_length 0x00000001
6954
6955 #define GEN75_SCISSOR_RECT_length 0x00000002
6956
6957 struct GEN75_SCISSOR_RECT {
6958 uint32_t ScissorRectangleYMin;
6959 uint32_t ScissorRectangleXMin;
6960 uint32_t ScissorRectangleYMax;
6961 uint32_t ScissorRectangleXMax;
6962 };
6963
6964 static inline void
6965 GEN75_SCISSOR_RECT_pack(__gen_user_data *data, void * restrict dst,
6966 const struct GEN75_SCISSOR_RECT * restrict values)
6967 {
6968 uint32_t *dw = (uint32_t * restrict) dst;
6969
6970 dw[0] =
6971 __gen_field(values->ScissorRectangleYMin, 16, 31) |
6972 __gen_field(values->ScissorRectangleXMin, 0, 15) |
6973 0;
6974
6975 dw[1] =
6976 __gen_field(values->ScissorRectangleYMax, 16, 31) |
6977 __gen_field(values->ScissorRectangleXMax, 0, 15) |
6978 0;
6979
6980 }
6981
6982 #define GEN75_SF_CLIP_VIEWPORT_length 0x00000010
6983
6984 struct GEN75_SF_CLIP_VIEWPORT {
6985 float ViewportMatrixElementm00;
6986 float ViewportMatrixElementm11;
6987 float ViewportMatrixElementm22;
6988 float ViewportMatrixElementm30;
6989 float ViewportMatrixElementm31;
6990 float ViewportMatrixElementm32;
6991 float XMinClipGuardband;
6992 float XMaxClipGuardband;
6993 float YMinClipGuardband;
6994 float YMaxClipGuardband;
6995 };
6996
6997 static inline void
6998 GEN75_SF_CLIP_VIEWPORT_pack(__gen_user_data *data, void * restrict dst,
6999 const struct GEN75_SF_CLIP_VIEWPORT * restrict values)
7000 {
7001 uint32_t *dw = (uint32_t * restrict) dst;
7002
7003 dw[0] =
7004 __gen_float(values->ViewportMatrixElementm00) |
7005 0;
7006
7007 dw[1] =
7008 __gen_float(values->ViewportMatrixElementm11) |
7009 0;
7010
7011 dw[2] =
7012 __gen_float(values->ViewportMatrixElementm22) |
7013 0;
7014
7015 dw[3] =
7016 __gen_float(values->ViewportMatrixElementm30) |
7017 0;
7018
7019 dw[4] =
7020 __gen_float(values->ViewportMatrixElementm31) |
7021 0;
7022
7023 dw[5] =
7024 __gen_float(values->ViewportMatrixElementm32) |
7025 0;
7026
7027 dw[6] =
7028 0;
7029
7030 dw[7] =
7031 0;
7032
7033 dw[8] =
7034 __gen_float(values->XMinClipGuardband) |
7035 0;
7036
7037 dw[9] =
7038 __gen_float(values->XMaxClipGuardband) |
7039 0;
7040
7041 dw[10] =
7042 __gen_float(values->YMinClipGuardband) |
7043 0;
7044
7045 dw[11] =
7046 __gen_float(values->YMaxClipGuardband) |
7047 0;
7048
7049 dw[12] =
7050 0;
7051
7052 }
7053
7054 #define GEN75_BLEND_STATE_length 0x00000002
7055
7056 struct GEN75_BLEND_STATE {
7057 uint32_t ColorBufferBlendEnable;
7058 uint32_t IndependentAlphaBlendEnable;
7059 #define BLENDFUNCTION_ADD 0
7060 #define BLENDFUNCTION_SUBTRACT 1
7061 #define BLENDFUNCTION_REVERSE_SUBTRACT 2
7062 #define BLENDFUNCTION_MIN 3
7063 #define BLENDFUNCTION_MAX 4
7064 uint32_t AlphaBlendFunction;
7065 #define BLENDFACTOR_ONE 1
7066 #define BLENDFACTOR_SRC_COLOR 2
7067 #define BLENDFACTOR_SRC_ALPHA 3
7068 #define BLENDFACTOR_DST_ALPHA 4
7069 #define BLENDFACTOR_DST_COLOR 5
7070 #define BLENDFACTOR_SRC_ALPHA_SATURATE 6
7071 #define BLENDFACTOR_CONST_COLOR 7
7072 #define BLENDFACTOR_CONST_ALPHA 8
7073 #define BLENDFACTOR_SRC1_COLOR 9
7074 #define BLENDFACTOR_SRC1_ALPHA 10
7075 #define BLENDFACTOR_ZERO 17
7076 #define BLENDFACTOR_INV_SRC_COLOR 18
7077 #define BLENDFACTOR_INV_SRC_ALPHA 19
7078 #define BLENDFACTOR_INV_DST_ALPHA 20
7079 #define BLENDFACTOR_INV_DST_COLOR 21
7080 #define BLENDFACTOR_INV_CONST_COLOR 23
7081 #define BLENDFACTOR_INV_CONST_ALPHA 24
7082 #define BLENDFACTOR_INV_SRC1_COLOR 25
7083 #define BLENDFACTOR_INV_SRC1_ALPHA 26
7084 uint32_t SourceAlphaBlendFactor;
7085 uint32_t DestinationAlphaBlendFactor;
7086 #define BLENDFUNCTION_ADD 0
7087 #define BLENDFUNCTION_SUBTRACT 1
7088 #define BLENDFUNCTION_REVERSE_SUBTRACT 2
7089 #define BLENDFUNCTION_MIN 3
7090 #define BLENDFUNCTION_MAX 4
7091 uint32_t ColorBlendFunction;
7092 uint32_t SourceBlendFactor;
7093 uint32_t DestinationBlendFactor;
7094 uint32_t AlphaToCoverageEnable;
7095 uint32_t AlphaToOneEnable;
7096 uint32_t AlphaToCoverageDitherEnable;
7097 uint32_t WriteDisableAlpha;
7098 uint32_t WriteDisableRed;
7099 uint32_t WriteDisableGreen;
7100 uint32_t WriteDisableBlue;
7101 uint32_t LogicOpEnable;
7102 #define LOGICOP_CLEAR 0
7103 #define LOGICOP_NOR 1
7104 #define LOGICOP_AND_INVERTED 2
7105 #define LOGICOP_COPY_INVERTED 3
7106 #define LOGICOP_AND_REVERSE 4
7107 #define LOGICOP_INVERT 5
7108 #define LOGICOP_XOR 6
7109 #define LOGICOP_NAND 7
7110 #define LOGICOP_AND 8
7111 #define LOGICOP_EQUIV 9
7112 #define LOGICOP_NOOP 10
7113 #define LOGICOP_OR_INVERTED 11
7114 #define LOGICOP_COPY 12
7115 #define LOGICOP_OR_REVERSE 13
7116 #define LOGICOP_OR 14
7117 #define LOGICOP_SET 15
7118 uint32_t LogicOpFunction;
7119 uint32_t AlphaTestEnable;
7120 #define COMPAREFUNCTION_ALWAYS 0
7121 #define COMPAREFUNCTION_NEVER 1
7122 #define COMPAREFUNCTION_LESS 2
7123 #define COMPAREFUNCTION_EQUAL 3
7124 #define COMPAREFUNCTION_LEQUAL 4
7125 #define COMPAREFUNCTION_GREATER 5
7126 #define COMPAREFUNCTION_NOTEQUAL 6
7127 #define COMPAREFUNCTION_GEQUAL 7
7128 uint32_t AlphaTestFunction;
7129 uint32_t ColorDitherEnable;
7130 uint32_t XDitherOffset;
7131 uint32_t YDitherOffset;
7132 #define COLORCLAMP_UNORM 0
7133 #define COLORCLAMP_SNORM 1
7134 #define COLORCLAMP_RTFORMAT 2
7135 uint32_t ColorClampRange;
7136 uint32_t PreBlendColorClampEnable;
7137 uint32_t PostBlendColorClampEnable;
7138 };
7139
7140 static inline void
7141 GEN75_BLEND_STATE_pack(__gen_user_data *data, void * restrict dst,
7142 const struct GEN75_BLEND_STATE * restrict values)
7143 {
7144 uint32_t *dw = (uint32_t * restrict) dst;
7145
7146 dw[0] =
7147 __gen_field(values->ColorBufferBlendEnable, 31, 31) |
7148 __gen_field(values->IndependentAlphaBlendEnable, 30, 30) |
7149 __gen_field(values->AlphaBlendFunction, 26, 28) |
7150 __gen_field(values->SourceAlphaBlendFactor, 20, 24) |
7151 __gen_field(values->DestinationAlphaBlendFactor, 15, 19) |
7152 __gen_field(values->ColorBlendFunction, 11, 13) |
7153 __gen_field(values->SourceBlendFactor, 5, 9) |
7154 __gen_field(values->DestinationBlendFactor, 0, 4) |
7155 0;
7156
7157 dw[1] =
7158 __gen_field(values->AlphaToCoverageEnable, 31, 31) |
7159 __gen_field(values->AlphaToOneEnable, 30, 30) |
7160 __gen_field(values->AlphaToCoverageDitherEnable, 29, 29) |
7161 __gen_field(values->WriteDisableAlpha, 27, 27) |
7162 __gen_field(values->WriteDisableRed, 26, 26) |
7163 __gen_field(values->WriteDisableGreen, 25, 25) |
7164 __gen_field(values->WriteDisableBlue, 24, 24) |
7165 __gen_field(values->LogicOpEnable, 22, 22) |
7166 __gen_field(values->LogicOpFunction, 18, 21) |
7167 __gen_field(values->AlphaTestEnable, 16, 16) |
7168 __gen_field(values->AlphaTestFunction, 13, 15) |
7169 __gen_field(values->ColorDitherEnable, 12, 12) |
7170 __gen_field(values->XDitherOffset, 10, 11) |
7171 __gen_field(values->YDitherOffset, 8, 9) |
7172 __gen_field(values->ColorClampRange, 2, 3) |
7173 __gen_field(values->PreBlendColorClampEnable, 1, 1) |
7174 __gen_field(values->PostBlendColorClampEnable, 0, 0) |
7175 0;
7176
7177 }
7178
7179 #define GEN75_CC_VIEWPORT_length 0x00000002
7180
7181 struct GEN75_CC_VIEWPORT {
7182 float MinimumDepth;
7183 float MaximumDepth;
7184 };
7185
7186 static inline void
7187 GEN75_CC_VIEWPORT_pack(__gen_user_data *data, void * restrict dst,
7188 const struct GEN75_CC_VIEWPORT * restrict values)
7189 {
7190 uint32_t *dw = (uint32_t * restrict) dst;
7191
7192 dw[0] =
7193 __gen_float(values->MinimumDepth) |
7194 0;
7195
7196 dw[1] =
7197 __gen_float(values->MaximumDepth) |
7198 0;
7199
7200 }
7201
7202 #define GEN75_COLOR_CALC_STATE_length 0x00000006
7203
7204 struct GEN75_COLOR_CALC_STATE {
7205 uint32_t StencilReferenceValue;
7206 uint32_t BackFaceStencilReferenceValue;
7207 #define Cancelled 0
7208 #define NotCancelled 1
7209 uint32_t RoundDisableFunctionDisable;
7210 #define ALPHATEST_UNORM8 0
7211 #define ALPHATEST_FLOAT32 1
7212 uint32_t AlphaTestFormat;
7213 uint32_t AlphaReferenceValueAsUNORM8;
7214 float AlphaReferenceValueAsFLOAT32;
7215 float BlendConstantColorRed;
7216 float BlendConstantColorGreen;
7217 float BlendConstantColorBlue;
7218 float BlendConstantColorAlpha;
7219 };
7220
7221 static inline void
7222 GEN75_COLOR_CALC_STATE_pack(__gen_user_data *data, void * restrict dst,
7223 const struct GEN75_COLOR_CALC_STATE * restrict values)
7224 {
7225 uint32_t *dw = (uint32_t * restrict) dst;
7226
7227 dw[0] =
7228 __gen_field(values->StencilReferenceValue, 24, 31) |
7229 __gen_field(values->BackFaceStencilReferenceValue, 16, 23) |
7230 __gen_field(values->RoundDisableFunctionDisable, 15, 15) |
7231 __gen_field(values->AlphaTestFormat, 0, 0) |
7232 0;
7233
7234 dw[1] =
7235 __gen_field(values->AlphaReferenceValueAsUNORM8, 0, 31) |
7236 __gen_float(values->AlphaReferenceValueAsFLOAT32) |
7237 0;
7238
7239 dw[2] =
7240 __gen_float(values->BlendConstantColorRed) |
7241 0;
7242
7243 dw[3] =
7244 __gen_float(values->BlendConstantColorGreen) |
7245 0;
7246
7247 dw[4] =
7248 __gen_float(values->BlendConstantColorBlue) |
7249 0;
7250
7251 dw[5] =
7252 __gen_float(values->BlendConstantColorAlpha) |
7253 0;
7254
7255 }
7256
7257 #define GEN75_DEPTH_STENCIL_STATE_length 0x00000003
7258
7259 struct GEN75_DEPTH_STENCIL_STATE {
7260 uint32_t StencilTestEnable;
7261 #define COMPAREFUNCTION_ALWAYS 0
7262 #define COMPAREFUNCTION_NEVER 1
7263 #define COMPAREFUNCTION_LESS 2
7264 #define COMPAREFUNCTION_EQUAL 3
7265 #define COMPAREFUNCTION_LEQUAL 4
7266 #define COMPAREFUNCTION_GREATER 5
7267 #define COMPAREFUNCTION_NOTEQUAL 6
7268 #define COMPAREFUNCTION_GEQUAL 7
7269 uint32_t StencilTestFunction;
7270 #define STENCILOP_KEEP 0
7271 #define STENCILOP_ZERO 1
7272 #define STENCILOP_REPLACE 2
7273 #define STENCILOP_INCRSAT 3
7274 #define STENCILOP_DECRSAT 4
7275 #define STENCILOP_INCR 5
7276 #define STENCILOP_DECR 6
7277 #define STENCILOP_INVERT 7
7278 uint32_t StencilFailOp;
7279 uint32_t StencilPassDepthFailOp;
7280 uint32_t StencilPassDepthPassOp;
7281 uint32_t StencilBufferWriteEnable;
7282 uint32_t DoubleSidedStencilEnable;
7283 #define COMPAREFUNCTION_ALWAYS 0
7284 #define COMPAREFUNCTION_NEVER 1
7285 #define COMPAREFUNCTION_LESS 2
7286 #define COMPAREFUNCTION_EQUAL 3
7287 #define COMPAREFUNCTION_LEQUAL 4
7288 #define COMPAREFUNCTION_GREATER 5
7289 #define COMPAREFUNCTION_NOTEQUAL 6
7290 #define COMPAREFUNCTION_GEQUAL 7
7291 uint32_t BackFaceStencilTestFunction;
7292 #define STENCILOP_KEEP 0
7293 #define STENCILOP_ZERO 1
7294 #define STENCILOP_REPLACE 2
7295 #define STENCILOP_INCRSAT 3
7296 #define STENCILOP_DECRSAT 4
7297 #define STENCILOP_INCR 5
7298 #define STENCILOP_DECR 6
7299 #define STENCILOP_INVERT 7
7300 uint32_t BackfaceStencilFailOp;
7301 uint32_t BackfaceStencilPassDepthFailOp;
7302 uint32_t BackfaceStencilPassDepthPassOp;
7303 uint32_t StencilTestMask;
7304 uint32_t StencilWriteMask;
7305 uint32_t BackfaceStencilTestMask;
7306 uint32_t BackfaceStencilWriteMask;
7307 uint32_t DepthTestEnable;
7308 #define COMPAREFUNCTION_ALWAYS 0
7309 #define COMPAREFUNCTION_NEVER 1
7310 #define COMPAREFUNCTION_LESS 2
7311 #define COMPAREFUNCTION_EQUAL 3
7312 #define COMPAREFUNCTION_LEQUAL 4
7313 #define COMPAREFUNCTION_GREATER 5
7314 #define COMPAREFUNCTION_NOTEQUAL 6
7315 #define COMPAREFUNCTION_GEQUAL 7
7316 uint32_t DepthTestFunction;
7317 uint32_t DepthBufferWriteEnable;
7318 };
7319
7320 static inline void
7321 GEN75_DEPTH_STENCIL_STATE_pack(__gen_user_data *data, void * restrict dst,
7322 const struct GEN75_DEPTH_STENCIL_STATE * restrict values)
7323 {
7324 uint32_t *dw = (uint32_t * restrict) dst;
7325
7326 dw[0] =
7327 __gen_field(values->StencilTestEnable, 31, 31) |
7328 __gen_field(values->StencilTestFunction, 28, 30) |
7329 __gen_field(values->StencilFailOp, 25, 27) |
7330 __gen_field(values->StencilPassDepthFailOp, 22, 24) |
7331 __gen_field(values->StencilPassDepthPassOp, 19, 21) |
7332 __gen_field(values->StencilBufferWriteEnable, 18, 18) |
7333 __gen_field(values->DoubleSidedStencilEnable, 15, 15) |
7334 __gen_field(values->BackFaceStencilTestFunction, 12, 14) |
7335 __gen_field(values->BackfaceStencilFailOp, 9, 11) |
7336 __gen_field(values->BackfaceStencilPassDepthFailOp, 6, 8) |
7337 __gen_field(values->BackfaceStencilPassDepthPassOp, 3, 5) |
7338 0;
7339
7340 dw[1] =
7341 __gen_field(values->StencilTestMask, 24, 31) |
7342 __gen_field(values->StencilWriteMask, 16, 23) |
7343 __gen_field(values->BackfaceStencilTestMask, 8, 15) |
7344 __gen_field(values->BackfaceStencilWriteMask, 0, 7) |
7345 0;
7346
7347 dw[2] =
7348 __gen_field(values->DepthTestEnable, 31, 31) |
7349 __gen_field(values->DepthTestFunction, 27, 29) |
7350 __gen_field(values->DepthBufferWriteEnable, 26, 26) |
7351 0;
7352
7353 }
7354
7355 #define GEN75_MEMORY_OBJECT_CONTROL_STATE_length 0x00000001
7356
7357 #define GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_length 0x00000001
7358
7359 struct GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS {
7360 #define Highestpriority 0
7361 #define Secondhighestpriority 1
7362 #define Thirdhighestpriority 2
7363 #define Lowestpriority 3
7364 uint32_t ArbitrationPriorityControl;
7365 #define PTE 0
7366 #define UC 1
7367 #define LLCeLLCWBcacheable 2
7368 #define eLLCWBcacheable 3
7369 uint32_t LLCeLLCCacheabilityControlLLCCC;
7370 uint32_t L3CacheabilityControlL3CC;
7371 };
7372
7373 static inline void
7374 GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_pack(__gen_user_data *data, void * restrict dst,
7375 const struct GEN75_VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS * restrict values)
7376 {
7377 uint32_t *dw = (uint32_t * restrict) dst;
7378
7379 dw[0] =
7380 __gen_field(values->ArbitrationPriorityControl, 4, 5) |
7381 __gen_field(values->LLCeLLCCacheabilityControlLLCCC, 1, 2) |
7382 __gen_field(values->L3CacheabilityControlL3CC, 0, 0) |
7383 0;
7384
7385 }
7386
7387 #define GEN75_INTERFACE_DESCRIPTOR_DATA_length 0x00000008
7388
7389 struct GEN75_INTERFACE_DESCRIPTOR_DATA {
7390 uint32_t KernelStartPointer;
7391 #define Multiple 0
7392 #define Single 1
7393 uint32_t SingleProgramFlow;
7394 #define NormalPriority 0
7395 #define HighPriority 1
7396 uint32_t ThreadPriority;
7397 #define IEEE754 0
7398 #define Alternate 1
7399 uint32_t FloatingPointMode;
7400 uint32_t IllegalOpcodeExceptionEnable;
7401 uint32_t MaskStackExceptionEnable;
7402 uint32_t SoftwareExceptionEnable;
7403 uint32_t SamplerStatePointer;
7404 #define Nosamplersused 0
7405 #define Between1and4samplersused 1
7406 #define Between5and8samplersused 2
7407 #define Between9and12samplersused 3
7408 #define Between13and16samplersused 4
7409 uint32_t SamplerCount;
7410 uint32_t BindingTablePointer;
7411 uint32_t BindingTableEntryCount;
7412 uint32_t ConstantURBEntryReadLength;
7413 #define RTNE 0
7414 #define RU 1
7415 #define RD 2
7416 #define RTZ 3
7417 uint32_t RoundingMode;
7418 uint32_t BarrierEnable;
7419 uint32_t SharedLocalMemorySize;
7420 uint32_t NumberofThreadsinGPGPUThreadGroup;
7421 uint32_t CrossThreadConstantDataReadLength;
7422 };
7423
7424 static inline void
7425 GEN75_INTERFACE_DESCRIPTOR_DATA_pack(__gen_user_data *data, void * restrict dst,
7426 const struct GEN75_INTERFACE_DESCRIPTOR_DATA * restrict values)
7427 {
7428 uint32_t *dw = (uint32_t * restrict) dst;
7429
7430 dw[0] =
7431 __gen_offset(values->KernelStartPointer, 6, 31) |
7432 0;
7433
7434 dw[1] =
7435 __gen_field(values->SingleProgramFlow, 18, 18) |
7436 __gen_field(values->ThreadPriority, 17, 17) |
7437 __gen_field(values->FloatingPointMode, 16, 16) |
7438 __gen_field(values->IllegalOpcodeExceptionEnable, 13, 13) |
7439 __gen_field(values->MaskStackExceptionEnable, 11, 11) |
7440 __gen_field(values->SoftwareExceptionEnable, 7, 7) |
7441 0;
7442
7443 dw[2] =
7444 __gen_offset(values->SamplerStatePointer, 5, 31) |
7445 __gen_field(values->SamplerCount, 2, 4) |
7446 0;
7447
7448 dw[3] =
7449 __gen_offset(values->BindingTablePointer, 5, 15) |
7450 __gen_field(values->BindingTableEntryCount, 0, 4) |
7451 0;
7452
7453 dw[4] =
7454 __gen_field(values->ConstantURBEntryReadLength, 16, 31) |
7455 0;
7456
7457 dw[5] =
7458 __gen_field(values->RoundingMode, 22, 23) |
7459 __gen_field(values->BarrierEnable, 21, 21) |
7460 __gen_field(values->SharedLocalMemorySize, 16, 20) |
7461 __gen_field(values->NumberofThreadsinGPGPUThreadGroup, 0, 7) |
7462 0;
7463
7464 dw[6] =
7465 __gen_field(values->CrossThreadConstantDataReadLength, 0, 7) |
7466 0;
7467
7468 dw[7] =
7469 0;
7470
7471 }
7472
7473 #define GEN75_PALETTE_ENTRY_length 0x00000001
7474
7475 #define GEN75_RENDER_SURFACE_STATE_length 0x00000008
7476
7477 struct GEN75_RENDER_SURFACE_STATE {
7478 #define SURFTYPE_1D 0
7479 #define SURFTYPE_2D 1
7480 #define SURFTYPE_3D 2
7481 #define SURFTYPE_CUBE 3
7482 #define SURFTYPE_BUFFER 4
7483 #define SURFTYPE_STRBUF 5
7484 #define SURFTYPE_NULL 7
7485 uint32_t SurfaceType;
7486 uint32_t SurfaceArray;
7487 uint32_t SurfaceFormat;
7488 uint32_t SurfaceVerticalAlignment;
7489 #define HALIGN_4 0
7490 #define HALIGN_8 1
7491 uint32_t SurfaceHorizontalAlignment;
7492 uint32_t TiledSurface;
7493 #define TILEWALK_XMAJOR 0
7494 #define TILEWALK_YMAJOR 1
7495 uint32_t TileWalk;
7496 uint32_t VerticalLineStride;
7497 uint32_t VerticalLineStrideOffset;
7498 #define ARYSPC_FULL 0
7499 #define ARYSPC_LOD0 1
7500 uint32_t SurfaceArraySpacing;
7501 uint32_t RenderCacheReadWriteMode;
7502 #define NORMAL_MODE 0
7503 #define PROGRESSIVE_FRAME 2
7504 #define INTERLACED_FRAME 3
7505 uint32_t MediaBoundaryPixelMode;
7506 uint32_t CubeFaceEnables;
7507 __gen_address_type SurfaceBaseAddress;
7508 uint32_t Height;
7509 uint32_t Width;
7510 uint32_t Depth;
7511 uint32_t IntegerSurfaceFormat;
7512 uint32_t SurfacePitch;
7513 #define RTROTATE_0DEG 0
7514 #define RTROTATE_90DEG 1
7515 #define RTROTATE_270DEG 3
7516 uint32_t RenderTargetRotation;
7517 uint32_t MinimumArrayElement;
7518 uint32_t RenderTargetViewExtent;
7519 #define MSFMT_MSS 0
7520 #define MSFMT_DEPTH_STENCIL 1
7521 uint32_t MultisampledSurfaceStorageFormat;
7522 #define MULTISAMPLECOUNT_1 0
7523 #define MULTISAMPLECOUNT_4 2
7524 #define MULTISAMPLECOUNT_8 3
7525 uint32_t NumberofMultisamples;
7526 uint32_t MultisamplePositionPaletteIndex;
7527 uint32_t MinimumArrayElement0;
7528 uint32_t XOffset;
7529 uint32_t YOffset;
7530 struct GEN75_MEMORY_OBJECT_CONTROL_STATE SurfaceObjectControlState;
7531 uint32_t SurfaceMinLOD;
7532 uint32_t MIPCountLOD;
7533 __gen_address_type MCSBaseAddress;
7534 uint32_t MCSSurfacePitch;
7535 __gen_address_type AppendCounterAddress;
7536 uint32_t AppendCounterEnable;
7537 uint32_t MCSEnable;
7538 uint32_t ReservedMBZ;
7539 uint32_t XOffsetforUVPlane;
7540 uint32_t YOffsetforUVPlane;
7541 #define SCS_ZERO 0
7542 #define SCS_ONE 1
7543 #define SCS_RED 4
7544 #define SCS_GREEN 5
7545 #define SCS_BLUE 6
7546 #define SCS_ALPHA 7
7547 uint32_t ShaderChannelSelectR;
7548 uint32_t ShaderChannelSelectG;
7549 uint32_t ShaderChannelSelectB;
7550 uint32_t ShaderChannelSelectA;
7551 float ResourceMinLOD;
7552 };
7553
7554 static inline void
7555 GEN75_RENDER_SURFACE_STATE_pack(__gen_user_data *data, void * restrict dst,
7556 const struct GEN75_RENDER_SURFACE_STATE * restrict values)
7557 {
7558 uint32_t *dw = (uint32_t * restrict) dst;
7559
7560 dw[0] =
7561 __gen_field(values->SurfaceType, 29, 31) |
7562 __gen_field(values->SurfaceArray, 28, 28) |
7563 __gen_field(values->SurfaceFormat, 18, 26) |
7564 __gen_field(values->SurfaceVerticalAlignment, 16, 17) |
7565 __gen_field(values->SurfaceHorizontalAlignment, 15, 15) |
7566 __gen_field(values->TiledSurface, 14, 14) |
7567 __gen_field(values->TileWalk, 13, 13) |
7568 __gen_field(values->VerticalLineStride, 12, 12) |
7569 __gen_field(values->VerticalLineStrideOffset, 11, 11) |
7570 __gen_field(values->SurfaceArraySpacing, 10, 10) |
7571 __gen_field(values->RenderCacheReadWriteMode, 8, 8) |
7572 __gen_field(values->MediaBoundaryPixelMode, 6, 7) |
7573 __gen_field(values->CubeFaceEnables, 0, 5) |
7574 0;
7575
7576 uint32_t dw1 =
7577 0;
7578
7579 dw[1] =
7580 __gen_combine_address(data, &dw[1], values->SurfaceBaseAddress, dw1);
7581
7582 dw[2] =
7583 __gen_field(values->Height, 16, 29) |
7584 __gen_field(values->Width, 0, 13) |
7585 0;
7586
7587 dw[3] =
7588 __gen_field(values->Depth, 21, 31) |
7589 __gen_field(values->IntegerSurfaceFormat, 18, 20) |
7590 __gen_field(values->SurfacePitch, 0, 17) |
7591 0;
7592
7593 dw[4] =
7594 __gen_field(values->RenderTargetRotation, 29, 30) |
7595 __gen_field(values->MinimumArrayElement, 18, 28) |
7596 __gen_field(values->RenderTargetViewExtent, 7, 17) |
7597 __gen_field(values->MultisampledSurfaceStorageFormat, 6, 6) |
7598 __gen_field(values->NumberofMultisamples, 3, 5) |
7599 __gen_field(values->MultisamplePositionPaletteIndex, 0, 2) |
7600 __gen_field(values->MinimumArrayElement, 0, 26) |
7601 0;
7602
7603 uint32_t dw_SurfaceObjectControlState;
7604 GEN75_MEMORY_OBJECT_CONTROL_STATE_pack(data, &dw_SurfaceObjectControlState, &values->SurfaceObjectControlState);
7605 dw[5] =
7606 __gen_offset(values->XOffset, 25, 31) |
7607 __gen_offset(values->YOffset, 20, 23) |
7608 __gen_field(dw_SurfaceObjectControlState, 16, 19) |
7609 __gen_field(values->SurfaceMinLOD, 4, 7) |
7610 __gen_field(values->MIPCountLOD, 0, 3) |
7611 0;
7612
7613 uint32_t dw6 =
7614 __gen_field(values->MCSSurfacePitch, 3, 11) |
7615 __gen_field(values->AppendCounterEnable, 1, 1) |
7616 __gen_field(values->MCSEnable, 0, 0) |
7617 __gen_field(values->ReservedMBZ, 30, 31) |
7618 __gen_field(values->XOffsetforUVPlane, 16, 29) |
7619 __gen_field(values->YOffsetforUVPlane, 0, 13) |
7620 0;
7621
7622 dw[6] =
7623 __gen_combine_address(data, &dw[6], values->AppendCounterAddress, dw6);
7624
7625 dw[7] =
7626 __gen_field(values->ShaderChannelSelectR, 25, 27) |
7627 __gen_field(values->ShaderChannelSelectG, 22, 24) |
7628 __gen_field(values->ShaderChannelSelectB, 19, 21) |
7629 __gen_field(values->ShaderChannelSelectA, 16, 18) |
7630 __gen_field(values->ResourceMinLOD * (1 << 8), 0, 11) |
7631 0;
7632
7633 }
7634
7635 #define GEN75_SAMPLER_BORDER_COLOR_STATE_length 0x00000014
7636
7637 struct GEN75_SAMPLER_BORDER_COLOR_STATE {
7638 uint32_t BorderColorRedDX100GL;
7639 uint32_t BorderColorAlpha;
7640 uint32_t BorderColorBlue;
7641 uint32_t BorderColorGreen;
7642 uint32_t BorderColorRedDX9;
7643 uint32_t BorderColorGreen0;
7644 uint32_t BorderColorBlue0;
7645 uint32_t BorderColorAlpha0;
7646 uint64_t BorderColor;
7647 uint64_t BorderColor0;
7648 uint64_t BorderColor1;
7649 };
7650
7651 static inline void
7652 GEN75_SAMPLER_BORDER_COLOR_STATE_pack(__gen_user_data *data, void * restrict dst,
7653 const struct GEN75_SAMPLER_BORDER_COLOR_STATE * restrict values)
7654 {
7655 uint32_t *dw = (uint32_t * restrict) dst;
7656
7657 dw[0] =
7658 __gen_field(values->BorderColorRedDX100GL, 0, 31) |
7659 __gen_field(values->BorderColorAlpha, 24, 31) |
7660 __gen_field(values->BorderColorBlue, 16, 23) |
7661 __gen_field(values->BorderColorGreen, 8, 15) |
7662 __gen_field(values->BorderColorRedDX9, 0, 7) |
7663 0;
7664
7665 dw[1] =
7666 __gen_field(values->BorderColorGreen, 0, 31) |
7667 0;
7668
7669 dw[2] =
7670 __gen_field(values->BorderColorBlue, 0, 31) |
7671 0;
7672
7673 dw[3] =
7674 __gen_field(values->BorderColorAlpha, 0, 31) |
7675 0;
7676
7677 dw[4] =
7678 0;
7679
7680 dw[16] =
7681 __gen_field(values->BorderColor, 0, 127) |
7682 __gen_field(values->BorderColor, 0, 127) |
7683 __gen_field(values->BorderColor, 0, 127) |
7684 0;
7685
7686 }
7687
7688 #define GEN75_SAMPLER_STATE_length 0x00000004
7689
7690 struct GEN75_SAMPLER_STATE {
7691 uint32_t SamplerDisable;
7692 #define DX10OGL 0
7693 #define DX9 1
7694 uint32_t TextureBorderColorMode;
7695 #define OGL 1
7696 uint32_t LODPreClampEnable;
7697 float BaseMipLevel;
7698 #define MIPFILTER_NONE 0
7699 #define MIPFILTER_NEAREST 1
7700 #define MIPFILTER_LINEAR 3
7701 uint32_t MipModeFilter;
7702 #define MAPFILTER_NEAREST 0
7703 #define MAPFILTER_LINEAR 1
7704 #define MAPFILTER_ANISOTROPIC 2
7705 #define MAPFILTER_MONO 6
7706 uint32_t MagModeFilter;
7707 #define MAPFILTER_NEAREST 0
7708 #define MAPFILTER_LINEAR 1
7709 #define MAPFILTER_ANISOTROPIC 2
7710 #define MAPFILTER_MONO 6
7711 uint32_t MinModeFilter;
7712 uint32_t TextureLODBias;
7713 #define LEGACY 0
7714 #define EWAApproximation 1
7715 uint32_t AnisotropicAlgorithm;
7716 float MinLOD;
7717 float MaxLOD;
7718 #define PREFILTEROPALWAYS 0
7719 #define PREFILTEROPNEVER 1
7720 #define PREFILTEROPLESS 2
7721 #define PREFILTEROPEQUAL 3
7722 #define PREFILTEROPLEQUAL 4
7723 #define PREFILTEROPGREATER 5
7724 #define PREFILTEROPNOTEQUAL 6
7725 #define PREFILTEROPGEQUAL 7
7726 uint32_t ShadowFunction;
7727 #define PROGRAMMED 0
7728 #define OVERRIDE 1
7729 uint32_t CubeSurfaceControlMode;
7730 uint32_t BorderColorPointer;
7731 uint32_t ChromaKeyEnable;
7732 uint32_t ChromaKeyIndex;
7733 #define KEYFILTER_KILL_ON_ANY_MATCH 0
7734 #define KEYFILTER_REPLACE_BLACK 1
7735 uint32_t ChromaKeyMode;
7736 #define RATIO21 0
7737 #define RATIO41 1
7738 #define RATIO61 2
7739 #define RATIO81 3
7740 #define RATIO101 4
7741 #define RATIO121 5
7742 #define RATIO141 6
7743 #define RATIO161 7
7744 uint32_t MaximumAnisotropy;
7745 uint32_t RAddressMinFilterRoundingEnable;
7746 uint32_t RAddressMagFilterRoundingEnable;
7747 uint32_t VAddressMinFilterRoundingEnable;
7748 uint32_t VAddressMagFilterRoundingEnable;
7749 uint32_t UAddressMinFilterRoundingEnable;
7750 uint32_t UAddressMagFilterRoundingEnable;
7751 #define FULL 0
7752 #define TRIQUAL_HIGHMAG_CLAMP_MIPFILTER 1
7753 #define MED 2
7754 #define LOW 3
7755 uint32_t TrilinearFilterQuality;
7756 uint32_t NonnormalizedCoordinateEnable;
7757 uint32_t TCXAddressControlMode;
7758 uint32_t TCYAddressControlMode;
7759 uint32_t TCZAddressControlMode;
7760 };
7761
7762 static inline void
7763 GEN75_SAMPLER_STATE_pack(__gen_user_data *data, void * restrict dst,
7764 const struct GEN75_SAMPLER_STATE * restrict values)
7765 {
7766 uint32_t *dw = (uint32_t * restrict) dst;
7767
7768 dw[0] =
7769 __gen_field(values->SamplerDisable, 31, 31) |
7770 __gen_field(values->TextureBorderColorMode, 29, 29) |
7771 __gen_field(values->LODPreClampEnable, 28, 28) |
7772 __gen_field(values->BaseMipLevel * (1 << 1), 22, 26) |
7773 __gen_field(values->MipModeFilter, 20, 21) |
7774 __gen_field(values->MagModeFilter, 17, 19) |
7775 __gen_field(values->MinModeFilter, 14, 16) |
7776 __gen_field(values->TextureLODBias, 1, 13) |
7777 __gen_field(values->AnisotropicAlgorithm, 0, 0) |
7778 0;
7779
7780 dw[1] =
7781 __gen_field(values->MinLOD * (1 << 8), 20, 31) |
7782 __gen_field(values->MaxLOD * (1 << 8), 8, 19) |
7783 __gen_field(values->ShadowFunction, 1, 3) |
7784 __gen_field(values->CubeSurfaceControlMode, 0, 0) |
7785 0;
7786
7787 dw[2] =
7788 __gen_offset(values->BorderColorPointer, 5, 31) |
7789 0;
7790
7791 dw[3] =
7792 __gen_field(values->ChromaKeyEnable, 25, 25) |
7793 __gen_field(values->ChromaKeyIndex, 23, 24) |
7794 __gen_field(values->ChromaKeyMode, 22, 22) |
7795 __gen_field(values->MaximumAnisotropy, 19, 21) |
7796 __gen_field(values->RAddressMinFilterRoundingEnable, 13, 13) |
7797 __gen_field(values->RAddressMagFilterRoundingEnable, 14, 14) |
7798 __gen_field(values->VAddressMinFilterRoundingEnable, 15, 15) |
7799 __gen_field(values->VAddressMagFilterRoundingEnable, 16, 16) |
7800 __gen_field(values->UAddressMinFilterRoundingEnable, 17, 17) |
7801 __gen_field(values->UAddressMagFilterRoundingEnable, 18, 18) |
7802 __gen_field(values->TrilinearFilterQuality, 11, 12) |
7803 __gen_field(values->NonnormalizedCoordinateEnable, 10, 10) |
7804 __gen_field(values->TCXAddressControlMode, 6, 8) |
7805 __gen_field(values->TCYAddressControlMode, 3, 5) |
7806 __gen_field(values->TCZAddressControlMode, 0, 2) |
7807 0;
7808
7809 }
7810
7811 /* Enum 3D_Prim_Topo_Type */
7812 #define _3DPRIM_POINTLIST 1
7813 #define _3DPRIM_LINELIST 2
7814 #define _3DPRIM_LINESTRIP 3
7815 #define _3DPRIM_TRILIST 4
7816 #define _3DPRIM_TRISTRIP 5
7817 #define _3DPRIM_TRIFAN 6
7818 #define _3DPRIM_QUADLIST 7
7819 #define _3DPRIM_QUADSTRIP 8
7820 #define _3DPRIM_LINELIST_ADJ 9
7821 #define _3DPRIM_LISTSTRIP_ADJ 10
7822 #define _3DPRIM_TRILIST_ADJ 11
7823 #define _3DPRIM_TRISTRIP_ADJ 12
7824 #define _3DPRIM_TRISTRIP_REVERSE 13
7825 #define _3DPRIM_POLYGON 14
7826 #define _3DPRIM_RECTLIST 15
7827 #define _3DPRIM_LINELOOP 16
7828 #define _3DPRIM_POINTLIST_BF 17
7829 #define _3DPRIM_LINESTRIP_CONT 18
7830 #define _3DPRIM_LINESTRIP_BF 19
7831 #define _3DPRIM_LINESTRIP_CONT_BF 20
7832 #define _3DPRIM_TRIFAN_NOSTIPPLE 22
7833 #define _3DPRIM_PATCHLIST_1 32
7834 #define _3DPRIM_PATCHLIST_2 33
7835 #define _3DPRIM_PATCHLIST_3 34
7836 #define _3DPRIM_PATCHLIST_4 35
7837 #define _3DPRIM_PATCHLIST_5 36
7838 #define _3DPRIM_PATCHLIST_6 37
7839 #define _3DPRIM_PATCHLIST_7 38
7840 #define _3DPRIM_PATCHLIST_8 39
7841 #define _3DPRIM_PATCHLIST_9 40
7842 #define _3DPRIM_PATCHLIST_10 41
7843 #define _3DPRIM_PATCHLIST_11 42
7844 #define _3DPRIM_PATCHLIST_12 43
7845 #define _3DPRIM_PATCHLIST_13 44
7846 #define _3DPRIM_PATCHLIST_14 45
7847 #define _3DPRIM_PATCHLIST_15 46
7848 #define _3DPRIM_PATCHLIST_16 47
7849 #define _3DPRIM_PATCHLIST_17 48
7850 #define _3DPRIM_PATCHLIST_18 49
7851 #define _3DPRIM_PATCHLIST_19 50
7852 #define _3DPRIM_PATCHLIST_20 51
7853 #define _3DPRIM_PATCHLIST_21 52
7854 #define _3DPRIM_PATCHLIST_22 53
7855 #define _3DPRIM_PATCHLIST_23 54
7856 #define _3DPRIM_PATCHLIST_24 55
7857 #define _3DPRIM_PATCHLIST_25 56
7858 #define _3DPRIM_PATCHLIST_26 57
7859 #define _3DPRIM_PATCHLIST_27 58
7860 #define _3DPRIM_PATCHLIST_28 59
7861 #define _3DPRIM_PATCHLIST_29 60
7862 #define _3DPRIM_PATCHLIST_30 61
7863 #define _3DPRIM_PATCHLIST_31 62
7864 #define _3DPRIM_PATCHLIST_32 63
7865
7866 /* Enum 3D_Vertex_Component_Control */
7867 #define VFCOMP_NOSTORE 0
7868 #define VFCOMP_STORE_SRC 1
7869 #define VFCOMP_STORE_0 2
7870 #define VFCOMP_STORE_1_FP 3
7871 #define VFCOMP_STORE_1_INT 4
7872 #define VFCOMP_STORE_VID 5
7873 #define VFCOMP_STORE_IID 6
7874 #define VFCOMP_STORE_PID 7
7875
7876 /* Enum 3D_Compare_Function */
7877 #define COMPAREFUNCTION_ALWAYS 0
7878 #define COMPAREFUNCTION_NEVER 1
7879 #define COMPAREFUNCTION_LESS 2
7880 #define COMPAREFUNCTION_EQUAL 3
7881 #define COMPAREFUNCTION_LEQUAL 4
7882 #define COMPAREFUNCTION_GREATER 5
7883 #define COMPAREFUNCTION_NOTEQUAL 6
7884 #define COMPAREFUNCTION_GEQUAL 7
7885
7886 /* Enum SURFACE_FORMAT */
7887 #define R32G32B32A32_FLOAT 0
7888 #define R32G32B32A32_SINT 1
7889 #define R32G32B32A32_UINT 2
7890 #define R32G32B32A32_UNORM 3
7891 #define R32G32B32A32_SNORM 4
7892 #define R64G64_FLOAT 5
7893 #define R32G32B32X32_FLOAT 6
7894 #define R32G32B32A32_SSCALED 7
7895 #define R32G32B32A32_USCALED 8
7896 #define R32G32B32A32_SFIXED 32
7897 #define R64G64_PASSTHRU 33
7898 #define R32G32B32_FLOAT 64
7899 #define R32G32B32_SINT 65
7900 #define R32G32B32_UINT 66
7901 #define R32G32B32_UNORM 67
7902 #define R32G32B32_SNORM 68
7903 #define R32G32B32_SSCALED 69
7904 #define R32G32B32_USCALED 70
7905 #define R32G32B32_SFIXED 80
7906 #define R16G16B16A16_UNORM 128
7907 #define R16G16B16A16_SNORM 129
7908 #define R16G16B16A16_SINT 130
7909 #define R16G16B16A16_UINT 131
7910 #define R16G16B16A16_FLOAT 132
7911 #define R32G32_FLOAT 133
7912 #define R32G32_SINT 134
7913 #define R32G32_UINT 135
7914 #define R32_FLOAT_X8X24_TYPELESS 136
7915 #define X32_TYPELESS_G8X24_UINT 137
7916 #define L32A32_FLOAT 138
7917 #define R32G32_UNORM 139
7918 #define R32G32_SNORM 140
7919 #define R64_FLOAT 141
7920 #define R16G16B16X16_UNORM 142
7921 #define R16G16B16X16_FLOAT 143
7922 #define A32X32_FLOAT 144
7923 #define L32X32_FLOAT 145
7924 #define I32X32_FLOAT 146
7925 #define R16G16B16A16_SSCALED 147
7926 #define R16G16B16A16_USCALED 148
7927 #define R32G32_SSCALED 149
7928 #define R32G32_USCALED 150
7929 #define R32G32_SFIXED 160
7930 #define R64_PASSTHRU 161
7931 #define B8G8R8A8_UNORM 192
7932 #define B8G8R8A8_UNORM_SRGB 193
7933 #define R10G10B10A2_UNORM 194
7934 #define R10G10B10A2_UNORM_SRGB 195
7935 #define R10G10B10A2_UINT 196
7936 #define R10G10B10_SNORM_A2_UNORM 197
7937 #define R8G8B8A8_UNORM 199
7938 #define R8G8B8A8_UNORM_SRGB 200
7939 #define R8G8B8A8_SNORM 201
7940 #define R8G8B8A8_SINT 202
7941 #define R8G8B8A8_UINT 203
7942 #define R16G16_UNORM 204
7943 #define R16G16_SNORM 205
7944 #define R16G16_SINT 206
7945 #define R16G16_UINT 207
7946 #define R16G16_FLOAT 208
7947 #define B10G10R10A2_UNORM 209
7948 #define B10G10R10A2_UNORM_SRGB 210
7949 #define R11G11B10_FLOAT 211
7950 #define R32_SINT 214
7951 #define R32_UINT 215
7952 #define R32_FLOAT 216
7953 #define R24_UNORM_X8_TYPELESS 217
7954 #define X24_TYPELESS_G8_UINT 218
7955 #define L32_UNORM 221
7956 #define A32_UNORM 222
7957 #define L16A16_UNORM 223
7958 #define I24X8_UNORM 224
7959 #define L24X8_UNORM 225
7960 #define A24X8_UNORM 226
7961 #define I32_FLOAT 227
7962 #define L32_FLOAT 228
7963 #define A32_FLOAT 229
7964 #define X8B8_UNORM_G8R8_SNORM 230
7965 #define A8X8_UNORM_G8R8_SNORM 231
7966 #define B8X8_UNORM_G8R8_SNORM 232
7967 #define B8G8R8X8_UNORM 233
7968 #define B8G8R8X8_UNORM_SRGB 234
7969 #define R8G8B8X8_UNORM 235
7970 #define R8G8B8X8_UNORM_SRGB 236
7971 #define R9G9B9E5_SHAREDEXP 237
7972 #define B10G10R10X2_UNORM 238
7973 #define L16A16_FLOAT 240
7974 #define R32_UNORM 241
7975 #define R32_SNORM 242
7976 #define R10G10B10X2_USCALED 243
7977 #define R8G8B8A8_SSCALED 244
7978 #define R8G8B8A8_USCALED 245
7979 #define R16G16_SSCALED 246
7980 #define R16G16_USCALED 247
7981 #define R32_SSCALED 248
7982 #define R32_USCALED 249
7983 #define B5G6R5_UNORM 256
7984 #define B5G6R5_UNORM_SRGB 257
7985 #define B5G5R5A1_UNORM 258
7986 #define B5G5R5A1_UNORM_SRGB 259
7987 #define B4G4R4A4_UNORM 260
7988 #define B4G4R4A4_UNORM_SRGB 261
7989 #define R8G8_UNORM 262
7990 #define R8G8_SNORM 263
7991 #define R8G8_SINT 264
7992 #define R8G8_UINT 265
7993 #define R16_UNORM 266
7994 #define R16_SNORM 267
7995 #define R16_SINT 268
7996 #define R16_UINT 269
7997 #define R16_FLOAT 270
7998 #define A8P8_UNORM_PALETTE0 271
7999 #define A8P8_UNORM_PALETTE1 272
8000 #define I16_UNORM 273
8001 #define L16_UNORM 274
8002 #define A16_UNORM 275
8003 #define L8A8_UNORM 276
8004 #define I16_FLOAT 277
8005 #define L16_FLOAT 278
8006 #define A16_FLOAT 279
8007 #define L8A8_UNORM_SRGB 280
8008 #define R5G5_SNORM_B6_UNORM 281
8009 #define B5G5R5X1_UNORM 282
8010 #define B5G5R5X1_UNORM_SRGB 283
8011 #define R8G8_SSCALED 284
8012 #define R8G8_USCALED 285
8013 #define R16_SSCALED 286
8014 #define R16_USCALED 287
8015 #define P8A8_UNORM_PALETTE0 290
8016 #define P8A8_UNORM_PALETTE1 291
8017 #define A1B5G5R5_UNORM 292
8018 #define A4B4G4R4_UNORM 293
8019 #define L8A8_UINT 294
8020 #define L8A8_SINT 295
8021 #define R8_UNORM 320
8022 #define R8_SNORM 321
8023 #define R8_SINT 322
8024 #define R8_UINT 323
8025 #define A8_UNORM 324
8026 #define I8_UNORM 325
8027 #define L8_UNORM 326
8028 #define P4A4_UNORM_PALETTE0 327
8029 #define A4P4_UNORM_PALETTE0 328
8030 #define R8_SSCALED 329
8031 #define R8_USCALED 330
8032 #define P8_UNORM_PALETTE0 331
8033 #define L8_UNORM_SRGB 332
8034 #define P8_UNORM_PALETTE1 333
8035 #define P4A4_UNORM_PALETTE1 334
8036 #define A4P4_UNORM_PALETTE1 335
8037 #define Y8_UNORM 336
8038 #define L8_UINT 338
8039 #define L8_SINT 339
8040 #define I8_UINT 340
8041 #define I8_SINT 341
8042 #define DXT1_RGB_SRGB 384
8043 #define R1_UNORM 385
8044 #define YCRCB_NORMAL 386
8045 #define YCRCB_SWAPUVY 387
8046 #define P2_UNORM_PALETTE0 388
8047 #define P2_UNORM_PALETTE1 389
8048 #define BC1_UNORM 390
8049 #define BC2_UNORM 391
8050 #define BC3_UNORM 392
8051 #define BC4_UNORM 393
8052 #define BC5_UNORM 394
8053 #define BC1_UNORM_SRGB 395
8054 #define BC2_UNORM_SRGB 396
8055 #define BC3_UNORM_SRGB 397
8056 #define MONO8 398
8057 #define YCRCB_SWAPUV 399
8058 #define YCRCB_SWAPY 400
8059 #define DXT1_RGB 401
8060 #define FXT1 402
8061 #define R8G8B8_UNORM 403
8062 #define R8G8B8_SNORM 404
8063 #define R8G8B8_SSCALED 405
8064 #define R8G8B8_USCALED 406
8065 #define R64G64B64A64_FLOAT 407
8066 #define R64G64B64_FLOAT 408
8067 #define BC4_SNORM 409
8068 #define BC5_SNORM 410
8069 #define R16G16B16_FLOAT 411
8070 #define R16G16B16_UNORM 412
8071 #define R16G16B16_SNORM 413
8072 #define R16G16B16_SSCALED 414
8073 #define R16G16B16_USCALED 415
8074 #define BC6H_SF16 417
8075 #define BC7_UNORM 418
8076 #define BC7_UNORM_SRGB 419
8077 #define BC6H_UF16 420
8078 #define PLANAR_420_8 421
8079 #define R8G8B8_UNORM_SRGB 424
8080 #define ETC1_RGB8 425
8081 #define ETC2_RGB8 426
8082 #define EAC_R11 427
8083 #define EAC_RG11 428
8084 #define EAC_SIGNED_R11 429
8085 #define EAC_SIGNED_RG11 430
8086 #define ETC2_SRGB8 431
8087 #define R16G16B16_UINT 432
8088 #define R16G16B16_SINT 433
8089 #define R32_SFIXED 434
8090 #define R10G10B10A2_SNORM 435
8091 #define R10G10B10A2_USCALED 436
8092 #define R10G10B10A2_SSCALED 437
8093 #define R10G10B10A2_SINT 438
8094 #define B10G10R10A2_SNORM 439
8095 #define B10G10R10A2_USCALED 440
8096 #define B10G10R10A2_SSCALED 441
8097 #define B10G10R10A2_UINT 442
8098 #define B10G10R10A2_SINT 443
8099 #define R64G64B64A64_PASSTHRU 444
8100 #define R64G64B64_PASSTHRU 445
8101 #define ETC2_RGB8_PTA 448
8102 #define ETC2_SRGB8_PTA 449
8103 #define ETC2_EAC_RGBA8 450
8104 #define ETC2_EAC_SRGB8_A8 451
8105 #define R8G8B8_UINT 456
8106 #define R8G8B8_SINT 457
8107 #define RAW 511
8108
8109 /* Enum Texture Coordinate Mode */
8110 #define TCM_WRAP 0
8111 #define TCM_MIRROR 1
8112 #define TCM_CLAMP 2
8113 #define TCM_CUBE 3
8114 #define TCM_CLAMP_BORDER 4
8115 #define TCM_MIRROR_ONCE 5
8116