src/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
  37 {
  38    static const uint32_t push_constant_opcodes[] = {
  39       [VK_SHADER_STAGE_VERTEX]                  = 21,
  40       [VK_SHADER_STAGE_TESS_CONTROL]            = 25, /* HS */
  41       [VK_SHADER_STAGE_TESS_EVALUATION]         = 26, /* DS */
  42       [VK_SHADER_STAGE_GEOMETRY]                = 22,
  43       [VK_SHADER_STAGE_FRAGMENT]                = 23,
  44       [VK_SHADER_STAGE_COMPUTE]                 = 0,
  45    };
  46
  47    VkShaderStage stage;
  48    VkShaderStageFlags flushed = 0;
  49
  50    for_each_bit(stage, cmd_buffer->state.push_constants_dirty) {
  51       struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
  52
  53       if (state.offset == 0)
  54          continue;
  55
  56       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CONSTANT_VS,
  57                      ._3DCommandSubOpcode = push_constant_opcodes[stage],
  58                      .ConstantBody = {
  59                         .PointerToConstantBuffer0 = { .offset = state.offset },
  60                         .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
  61                      });
  62
  63       flushed |= 1 << stage;
  64    }
  65
  66    cmd_buffer->state.push_constants_dirty &= ~flushed;
  67 }
  68
  69 GENX_FUNC(GEN7, GEN7) void
  70 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
  71 {
  72    struct anv_device *device = cmd_buffer->device;
  73    struct anv_bo *scratch_bo = NULL;
  74
  75    cmd_buffer->state.scratch_size =
  76       anv_block_pool_size(&device->scratch_block_pool);
  77    if (cmd_buffer->state.scratch_size > 0)
  78       scratch_bo = &device->scratch_block_pool.bo;
  79
  80    anv_batch_emit(&cmd_buffer->batch, GEN7_STATE_BASE_ADDRESS,
  81       .GeneralStateBaseAddress                  = { scratch_bo, 0 },
  82       .GeneralStateMemoryObjectControlState     = GEN7_MOCS,
  83       .GeneralStateBaseAddressModifyEnable      = true,
  84       .GeneralStateAccessUpperBound             = { scratch_bo, scratch_bo->size },
  85       .GeneralStateAccessUpperBoundModifyEnable = true,
  86
  87       .SurfaceStateBaseAddress                  = anv_cmd_buffer_surface_base_address(cmd_buffer),
  88       .SurfaceStateMemoryObjectControlState     = GEN7_MOCS,
  89       .SurfaceStateBaseAddressModifyEnable      = true,
  90
  91       .DynamicStateBaseAddress                  = { &device->dynamic_state_block_pool.bo, 0 },
  92       .DynamicStateMemoryObjectControlState     = GEN7_MOCS,
  93       .DynamicStateBaseAddressModifyEnable      = true,
  94
  95       .IndirectObjectBaseAddress                = { NULL, 0 },
  96       .IndirectObjectMemoryObjectControlState   = GEN7_MOCS,
  97       .IndirectObjectBaseAddressModifyEnable    = true,
  98
  99       .IndirectObjectAccessUpperBound           = { NULL, 0xffffffff },
 100       .IndirectObjectAccessUpperBoundModifyEnable = true,
 101
 102       .InstructionBaseAddress                   = { &device->instruction_block_pool.bo, 0 },
 103       .InstructionMemoryObjectControlState      = GEN7_MOCS,
 104       .InstructionBaseAddressModifyEnable       = true,
 105       .InstructionAccessUpperBound              =  { &device->instruction_block_pool.bo,
 106                                                      device->instruction_block_pool.bo.size },
 107       .InstructionAccessUpperBoundModifyEnable  = true);
 108
 109    /* After re-setting the surface state base address, we have to do some
 110     * cache flusing so that the sampler engine will pick up the new
 111     * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
 112     * Shared Function > 3D Sampler > State > State Caching (page 96):
 113     *
 114     *    Coherency with system memory in the state cache, like the texture
 115     *    cache is handled partially by software. It is expected that the
 116     *    command stream or shader will issue Cache Flush operation or
 117     *    Cache_Flush sampler message to ensure that the L1 cache remains
 118     *    coherent with system memory.
 119     *
 120     *    [...]
 121     *
 122     *    Whenever the value of the Dynamic_State_Base_Addr,
 123     *    Surface_State_Base_Addr are altered, the L1 state cache must be
 124     *    invalidated to ensure the new surface or sampler state is fetched
 125     *    from system memory.
 126     *
 127     * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
 128     * which, according the PIPE_CONTROL instruction documentation in the
 129     * Broadwell PRM:
 130     *
 131     *    Setting this bit is independent of any other bit in this packet.
 132     *    This bit controls the invalidation of the L1 and L2 state caches
 133     *    at the top of the pipe i.e. at the parsing time.
 134     *
 135     * Unfortunately, experimentation seems to indicate that state cache
 136     * invalidation through a PIPE_CONTROL does nothing whatsoever in
 137     * regards to surface state and binding tables.  In stead, it seems that
 138     * invalidating the texture cache is what is actually needed.
 139     *
 140     * XXX:  As far as we have been able to determine through
 141     * experimentation, shows that flush the texture cache appears to be
 142     * sufficient.  The theory here is that all of the sampling/rendering
 143     * units cache the binding table in the texture cache.  However, we have
 144     * yet to be able to actually confirm this.
 145     */
 146    anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
 147                   .TextureCacheInvalidationEnable = true);
 148 }
 149
 150 static VkResult
 151 flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, VkShaderStage stage)
 152 {
 153    struct anv_state surfaces = { 0, }, samplers = { 0, };
 154    VkResult result;
 155
 156    result = anv_cmd_buffer_emit_samplers(cmd_buffer, stage, &samplers);
 157    if (result != VK_SUCCESS)
 158       return result;
 159    result = anv_cmd_buffer_emit_binding_table(cmd_buffer, stage, &surfaces);
 160    if (result != VK_SUCCESS)
 161       return result;
 162
 163    static const uint32_t sampler_state_opcodes[] = {
 164       [VK_SHADER_STAGE_VERTEX]                  = 43,
 165       [VK_SHADER_STAGE_TESS_CONTROL]            = 44, /* HS */
 166       [VK_SHADER_STAGE_TESS_EVALUATION]         = 45, /* DS */
 167       [VK_SHADER_STAGE_GEOMETRY]                = 46,
 168       [VK_SHADER_STAGE_FRAGMENT]                = 47,
 169       [VK_SHADER_STAGE_COMPUTE]                 = 0,
 170    };
 171
 172    static const uint32_t binding_table_opcodes[] = {
 173       [VK_SHADER_STAGE_VERTEX]                  = 38,
 174       [VK_SHADER_STAGE_TESS_CONTROL]            = 39,
 175       [VK_SHADER_STAGE_TESS_EVALUATION]         = 40,
 176       [VK_SHADER_STAGE_GEOMETRY]                = 41,
 177       [VK_SHADER_STAGE_FRAGMENT]                = 42,
 178       [VK_SHADER_STAGE_COMPUTE]                 = 0,
 179    };
 180
 181    if (samplers.alloc_size > 0) {
 182       anv_batch_emit(&cmd_buffer->batch,
 183                      GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
 184                      ._3DCommandSubOpcode  = sampler_state_opcodes[stage],
 185                      .PointertoVSSamplerState = samplers.offset);
 186    }
 187
 188    if (surfaces.alloc_size > 0) {
 189       anv_batch_emit(&cmd_buffer->batch,
 190                      GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
 191                      ._3DCommandSubOpcode  = binding_table_opcodes[stage],
 192                      .PointertoVSBindingTable = surfaces.offset);
 193    }
 194
 195    return VK_SUCCESS;
 196 }
 197
 198 GENX_FUNC(GEN7, GEN7) void
 199 genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer)
 200 {
 201    VkShaderStage s;
 202    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
 203                               cmd_buffer->state.pipeline->active_stages;
 204
 205    VkResult result = VK_SUCCESS;
 206    for_each_bit(s, dirty) {
 207       result = flush_descriptor_set(cmd_buffer, s);
 208       if (result != VK_SUCCESS)
 209          break;
 210    }
 211
 212    if (result != VK_SUCCESS) {
 213       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
 214
 215       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
 216       assert(result == VK_SUCCESS);
 217
 218       /* Re-emit state base addresses so we get the new surface state base
 219        * address before we start emitting binding tables etc.
 220        */
 221       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 222
 223       /* Re-emit all active binding tables */
 224       for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
 225          result = flush_descriptor_set(cmd_buffer, s);
 226
 227          /* It had better succeed this time */
 228          assert(result == VK_SUCCESS);
 229       }
 230    }
 231
 232    cmd_buffer->state.descriptors_dirty &= ~cmd_buffer->state.pipeline->active_stages;
 233 }
 234
 235 static inline int64_t
 236 clamp_int64(int64_t x, int64_t min, int64_t max)
 237 {
 238    if (x < min)
 239       return min;
 240    else if (x < max)
 241       return x;
 242    else
 243       return max;
 244 }
 245
 246 static void
 247 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
 248                    uint32_t count, const VkRect2D *scissors)
 249 {
 250    struct anv_state scissor_state =
 251       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 32, 32);
 252
 253    for (uint32_t i = 0; i < count; i++) {
 254       const VkRect2D *s = &scissors[i];
 255
 256       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 257        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 258        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 259        * what we want. Just special case empty clips and produce a canonical
 260        * empty clip. */
 261       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 262          .ScissorRectangleYMin = 1,
 263          .ScissorRectangleXMin = 1,
 264          .ScissorRectangleYMax = 0,
 265          .ScissorRectangleXMax = 0
 266       };
 267
 268       const int max = 0xffff;
 269       struct GEN7_SCISSOR_RECT scissor = {
 270          /* Do this math using int64_t so overflow gets clamped correctly. */
 271          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 272          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 273          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 274          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 275       };
 276
 277       if (s->extent.width <= 0 || s->extent.height <= 0) {
 278          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32,
 279                                 &empty_scissor);
 280       } else {
 281          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32, &scissor);
 282       }
 283    }
 284
 285    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
 286                   .ScissorRectPointer = scissor_state.offset);
 287 }
 288
 289 GENX_FUNC(GEN7, GEN7) void
 290 genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
 291 {
 292    if (cmd_buffer->state.dynamic.scissor.count > 0) {
 293       emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
 294                          cmd_buffer->state.dynamic.scissor.scissors);
 295    } else {
 296       /* Emit a default scissor based on the currently bound framebuffer */
 297       emit_scissor_state(cmd_buffer, 1,
 298                          &(VkRect2D) {
 299                             .offset = { .x = 0, .y = 0, },
 300                             .extent = {
 301                                .width = cmd_buffer->state.framebuffer->width,
 302                                .height = cmd_buffer->state.framebuffer->height,
 303                             },
 304                          });
 305    }
 306 }
 307
 308 static const uint32_t vk_to_gen_index_type[] = {
 309    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 310    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 311 };
 312
 313 static const uint32_t restart_index_for_type[] = {
 314    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 315    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 316 };
 317
 318 void genX(CmdBindIndexBuffer)(
 319     VkCmdBuffer                                 cmdBuffer,
 320     VkBuffer                                    _buffer,
 321     VkDeviceSize                                offset,
 322     VkIndexType                                 indexType)
 323 {
 324    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 325    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 326
 327    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 328    if (ANV_IS_HASWELL)
 329       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 330    cmd_buffer->state.gen7.index_buffer = buffer;
 331    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 332    cmd_buffer->state.gen7.index_offset = offset;
 333 }
 334
 335 static VkResult
 336 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 337 {
 338    struct anv_device *device = cmd_buffer->device;
 339    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 340    struct anv_state surfaces = { 0, }, samplers = { 0, };
 341    VkResult result;
 342
 343    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 344                                          VK_SHADER_STAGE_COMPUTE, &samplers);
 345    if (result != VK_SUCCESS)
 346       return result;
 347    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 348                                                VK_SHADER_STAGE_COMPUTE, &surfaces);
 349    if (result != VK_SUCCESS)
 350       return result;
 351
 352    struct GEN7_INTERFACE_DESCRIPTOR_DATA desc = {
 353       .KernelStartPointer = pipeline->cs_simd,
 354       .BindingTablePointer = surfaces.offset,
 355       .SamplerStatePointer = samplers.offset,
 356       .NumberofThreadsinGPGPUThreadGroup = 0 /* FIXME: Really? */
 357    };
 358
 359    uint32_t size = GEN7_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
 360    struct anv_state state =
 361       anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
 362
 363    GEN7_INTERFACE_DESCRIPTOR_DATA_pack(NULL, state.map, &desc);
 364
 365    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
 366                   .InterfaceDescriptorTotalLength = size,
 367                   .InterfaceDescriptorDataStartAddress = state.offset);
 368
 369    return VK_SUCCESS;
 370 }
 371
 372 static void
 373 cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
 374 {
 375    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 376    VkResult result;
 377
 378    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 379
 380    if (cmd_buffer->state.current_pipeline != GPGPU) {
 381       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
 382                      .PipelineSelection = GPGPU);
 383       cmd_buffer->state.current_pipeline = GPGPU;
 384    }
 385
 386    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 387       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 388
 389    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 390        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 391       /* FIXME: figure out descriptors for gen7 */
 392       result = flush_compute_descriptor_set(cmd_buffer);
 393       assert(result == VK_SUCCESS);
 394       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE;
 395    }
 396
 397    cmd_buffer->state.compute_dirty = 0;
 398 }
 399
 400 static void
 401 cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
 402 {
 403    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 404    uint32_t *p;
 405
 406    uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
 407
 408    assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 409
 410    if (cmd_buffer->state.current_pipeline != _3D) {
 411       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
 412                      .PipelineSelection = _3D);
 413       cmd_buffer->state.current_pipeline = _3D;
 414    }
 415
 416    if (vb_emit) {
 417       const uint32_t num_buffers = __builtin_popcount(vb_emit);
 418       const uint32_t num_dwords = 1 + num_buffers * 4;
 419
 420       p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
 421                           GEN7_3DSTATE_VERTEX_BUFFERS);
 422       uint32_t vb, i = 0;
 423       for_each_bit(vb, vb_emit) {
 424          struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
 425          uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
 426
 427          struct GEN7_VERTEX_BUFFER_STATE state = {
 428             .VertexBufferIndex = vb,
 429             .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
 430             .VertexBufferMemoryObjectControlState = GEN7_MOCS,
 431             .AddressModifyEnable = true,
 432             .BufferPitch = pipeline->binding_stride[vb],
 433             .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 434             .EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
 435             .InstanceDataStepRate = 1
 436          };
 437
 438          GEN7_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
 439          i++;
 440       }
 441    }
 442
 443    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
 444       /* If somebody compiled a pipeline after starting a command buffer the
 445        * scratch bo may have grown since we started this cmd buffer (and
 446        * emitted STATE_BASE_ADDRESS).  If we're binding that pipeline now,
 447        * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
 448       if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
 449          gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
 450
 451       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 452    }
 453
 454    if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
 455        cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
 456       /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 457        *
 458        *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 459        *    stall needs to be sent just prior to any 3DSTATE_VS,
 460        *    3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
 461        *    3DSTATE_BINDING_TABLE_POINTER_VS,
 462        *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one
 463        *    PIPE_CONTROL needs to be sent before any combination of VS
 464        *    associated 3DSTATE."
 465        */
 466       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
 467                      .DepthStallEnable = true,
 468                      .PostSyncOperation = WriteImmediateData,
 469                      .Address = { &cmd_buffer->device->workaround_bo, 0 });
 470    }
 471
 472    if (cmd_buffer->state.descriptors_dirty)
 473       gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
 474
 475    if (cmd_buffer->state.push_constants_dirty)
 476       cmd_buffer_flush_push_constants(cmd_buffer);
 477
 478    /* We use the gen8 state here because it only contains the additional
 479     * min/max fields and, since they occur at the end of the packet and
 480     * don't change the stride, they work on gen7 too.
 481     */
 482    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
 483       gen8_cmd_buffer_emit_viewport(cmd_buffer);
 484
 485    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
 486       gen7_cmd_buffer_emit_scissor(cmd_buffer);
 487
 488    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 489                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 490                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 491
 492       bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
 493          cmd_buffer->state.dynamic.depth_bias.slope_scaled != 0.0f;
 494
 495       uint32_t sf_dw[GEN7_3DSTATE_SF_length];
 496       struct GEN7_3DSTATE_SF sf = {
 497          GEN7_3DSTATE_SF_header,
 498          .LineWidth = cmd_buffer->state.dynamic.line_width,
 499          .GlobalDepthOffsetEnableSolid = enable_bias,
 500          .GlobalDepthOffsetEnableWireframe = enable_bias,
 501          .GlobalDepthOffsetEnablePoint = enable_bias,
 502          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 503          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope_scaled,
 504          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 505       };
 506       GEN7_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 507
 508       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 509    }
 510
 511    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 512                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 513       struct anv_state cc_state =
 514          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 515                                             GEN7_COLOR_CALC_STATE_length, 64);
 516       struct GEN7_COLOR_CALC_STATE cc = {
 517          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 518          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 519          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 520          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 521          .StencilReferenceValue =
 522             cmd_buffer->state.dynamic.stencil_reference.front,
 523          .BackFaceStencilReferenceValue =
 524             cmd_buffer->state.dynamic.stencil_reference.back,
 525       };
 526       GEN7_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 527
 528       anv_batch_emit(&cmd_buffer->batch,
 529                      GEN7_3DSTATE_CC_STATE_POINTERS,
 530                      .ColorCalcStatePointer = cc_state.offset);
 531    }
 532
 533    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 534                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 535                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 536       uint32_t depth_stencil_dw[GEN7_DEPTH_STENCIL_STATE_length];
 537
 538       struct GEN7_DEPTH_STENCIL_STATE depth_stencil = {
 539          /* Is this what we need to do? */
 540          .StencilBufferWriteEnable =
 541             cmd_buffer->state.dynamic.stencil_write_mask.front != 0,
 542
 543          .StencilTestMask =
 544             cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
 545          .StencilWriteMask =
 546             cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
 547
 548          .BackfaceStencilTestMask =
 549             cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
 550          .BackfaceStencilWriteMask =
 551             cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
 552       };
 553       GEN7_DEPTH_STENCIL_STATE_pack(NULL, depth_stencil_dw, &depth_stencil);
 554
 555       struct anv_state ds_state =
 556          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 557                                       pipeline->gen7.depth_stencil_state,
 558                                       GEN7_DEPTH_STENCIL_STATE_length, 64);
 559
 560       anv_batch_emit(&cmd_buffer->batch,
 561                      GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
 562                      .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
 563    }
 564
 565    if (cmd_buffer->state.gen7.index_buffer &&
 566        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 567                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 568       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 569       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 570
 571       if (ANV_IS_HASWELL) {
 572          anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
 573                         .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 574                         .CutIndex = cmd_buffer->state.restart_index);
 575       }
 576
 577       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
 578                      .CutIndexEnable = pipeline->primitive_restart,
 579                      .IndexFormat = cmd_buffer->state.gen7.index_type,
 580                      .MemoryObjectControlState = GEN7_MOCS,
 581                      .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 582                      .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
 583    }
 584
 585    cmd_buffer->state.vb_dirty &= ~vb_emit;
 586    cmd_buffer->state.dirty = 0;
 587 }
 588
 589 void genX(CmdDraw)(
 590     VkCmdBuffer                                 cmdBuffer,
 591     uint32_t                                    vertexCount,
 592     uint32_t                                    instanceCount,
 593     uint32_t                                    firstVertex,
 594     uint32_t                                    firstInstance)
 595 {
 596    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 597    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 598
 599    cmd_buffer_flush_state(cmd_buffer);
 600
 601    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 602                   .VertexAccessType = SEQUENTIAL,
 603                   .PrimitiveTopologyType = pipeline->topology,
 604                   .VertexCountPerInstance = vertexCount,
 605                   .StartVertexLocation = firstVertex,
 606                   .InstanceCount = instanceCount,
 607                   .StartInstanceLocation = firstInstance,
 608                   .BaseVertexLocation = 0);
 609 }
 610
 611 void genX(CmdDrawIndexed)(
 612     VkCmdBuffer                                 cmdBuffer,
 613     uint32_t                                    indexCount,
 614     uint32_t                                    instanceCount,
 615     uint32_t                                    firstIndex,
 616     int32_t                                     vertexOffset,
 617     uint32_t                                    firstInstance)
 618 {
 619    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 620    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 621
 622    cmd_buffer_flush_state(cmd_buffer);
 623
 624    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 625                   .VertexAccessType = RANDOM,
 626                   .PrimitiveTopologyType = pipeline->topology,
 627                   .VertexCountPerInstance = indexCount,
 628                   .StartVertexLocation = firstIndex,
 629                   .InstanceCount = instanceCount,
 630                   .StartInstanceLocation = firstInstance,
 631                   .BaseVertexLocation = vertexOffset);
 632 }
 633
 634 static void
 635 gen7_batch_lrm(struct anv_batch *batch,
 636               uint32_t reg, struct anv_bo *bo, uint32_t offset)
 637 {
 638    anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_MEM,
 639                   .RegisterAddress = reg,
 640                   .MemoryAddress = { bo, offset });
 641 }
 642
 643 static void
 644 gen7_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
 645 {
 646    anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_IMM,
 647                   .RegisterOffset = reg,
 648                   .DataDWord = imm);
 649 }
 650
 651 /* Auto-Draw / Indirect Registers */
 652 #define GEN7_3DPRIM_END_OFFSET          0x2420
 653 #define GEN7_3DPRIM_START_VERTEX        0x2430
 654 #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
 655 #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
 656 #define GEN7_3DPRIM_START_INSTANCE      0x243C
 657 #define GEN7_3DPRIM_BASE_VERTEX         0x2440
 658
 659 void genX(CmdDrawIndirect)(
 660     VkCmdBuffer                                 cmdBuffer,
 661     VkBuffer                                    _buffer,
 662     VkDeviceSize                                offset,
 663     uint32_t                                    count,
 664     uint32_t                                    stride)
 665 {
 666    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 667    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 668    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 669    struct anv_bo *bo = buffer->bo;
 670    uint32_t bo_offset = buffer->offset + offset;
 671
 672    cmd_buffer_flush_state(cmd_buffer);
 673
 674    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
 675    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
 676    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
 677    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
 678    gen7_batch_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
 679
 680    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 681                   .IndirectParameterEnable = true,
 682                   .VertexAccessType = SEQUENTIAL,
 683                   .PrimitiveTopologyType = pipeline->topology);
 684 }
 685
 686 void genX(CmdDrawIndexedIndirect)(
 687     VkCmdBuffer                                 cmdBuffer,
 688     VkBuffer                                    _buffer,
 689     VkDeviceSize                                offset,
 690     uint32_t                                    count,
 691     uint32_t                                    stride)
 692 {
 693    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 694    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 695    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 696    struct anv_bo *bo = buffer->bo;
 697    uint32_t bo_offset = buffer->offset + offset;
 698
 699    cmd_buffer_flush_state(cmd_buffer);
 700
 701    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
 702    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
 703    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
 704    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
 705    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
 706
 707    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 708                   .IndirectParameterEnable = true,
 709                   .VertexAccessType = RANDOM,
 710                   .PrimitiveTopologyType = pipeline->topology);
 711 }
 712
 713 void genX(CmdDispatch)(
 714     VkCmdBuffer                                 cmdBuffer,
 715     uint32_t                                    x,
 716     uint32_t                                    y,
 717     uint32_t                                    z)
 718 {
 719    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 720    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 721    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 722
 723    cmd_buffer_flush_compute_state(cmd_buffer);
 724
 725    anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
 726                   .SIMDSize = prog_data->simd_size / 16,
 727                   .ThreadDepthCounterMaximum = 0,
 728                   .ThreadHeightCounterMaximum = 0,
 729                   .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
 730                   .ThreadGroupIDXDimension = x,
 731                   .ThreadGroupIDYDimension = y,
 732                   .ThreadGroupIDZDimension = z,
 733                   .RightExecutionMask = pipeline->cs_right_mask,
 734                   .BottomExecutionMask = 0xffffffff);
 735
 736    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
 737 }
 738
 739 #define GPGPU_DISPATCHDIMX 0x2500
 740 #define GPGPU_DISPATCHDIMY 0x2504
 741 #define GPGPU_DISPATCHDIMZ 0x2508
 742
 743 void genX(CmdDispatchIndirect)(
 744     VkCmdBuffer                                 cmdBuffer,
 745     VkBuffer                                    _buffer,
 746     VkDeviceSize                                offset)
 747 {
 748    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 749    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 750    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 751    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 752    struct anv_bo *bo = buffer->bo;
 753    uint32_t bo_offset = buffer->offset + offset;
 754
 755    cmd_buffer_flush_compute_state(cmd_buffer);
 756
 757    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
 758    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
 759    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
 760
 761    anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
 762                   .IndirectParameterEnable = true,
 763                   .SIMDSize = prog_data->simd_size / 16,
 764                   .ThreadDepthCounterMaximum = 0,
 765                   .ThreadHeightCounterMaximum = 0,
 766                   .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
 767                   .RightExecutionMask = pipeline->cs_right_mask,
 768                   .BottomExecutionMask = 0xffffffff);
 769
 770    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
 771 }
 772
 773 void genX(CmdPipelineBarrier)(
 774     VkCmdBuffer                                 cmdBuffer,
 775     VkPipelineStageFlags                        srcStageMask,
 776     VkPipelineStageFlags                        destStageMask,
 777     VkBool32                                    byRegion,
 778     uint32_t                                    memBarrierCount,
 779     const void* const*                          ppMemBarriers)
 780 {
 781    stub();
 782 }
 783
 784 static void
 785 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
 786 {
 787    const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
 788    const struct anv_image_view *iview =
 789       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 790    const struct anv_image *image = iview ? iview->image : NULL;
 791    const bool has_depth = iview && iview->format->depth_format;
 792    const bool has_stencil = iview && iview->format->has_stencil;
 793
 794    /* Emit 3DSTATE_DEPTH_BUFFER */
 795    if (has_depth) {
 796       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DEPTH_BUFFER,
 797          .SurfaceType = SURFTYPE_2D,
 798          .DepthWriteEnable = iview->format->depth_format,
 799          .StencilWriteEnable = has_stencil,
 800          .HierarchicalDepthBufferEnable = false,
 801          .SurfaceFormat = iview->format->depth_format,
 802          .SurfacePitch = image->depth_surface.stride - 1,
 803          .SurfaceBaseAddress = {
 804             .bo = image->bo,
 805             .offset = image->depth_surface.offset,
 806          },
 807          .Height = fb->height - 1,
 808          .Width = fb->width - 1,
 809          .LOD = 0,
 810          .Depth = 1 - 1,
 811          .MinimumArrayElement = 0,
 812          .DepthBufferObjectControlState = GEN7_MOCS,
 813          .RenderTargetViewExtent = 1 - 1);
 814    } else {
 815       /* Even when no depth buffer is present, the hardware requires that
 816        * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
 817        *
 818        *    If a null depth buffer is bound, the driver must instead bind depth as:
 819        *       3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
 820        *       3DSTATE_DEPTH.Width = 1
 821        *       3DSTATE_DEPTH.Height = 1
 822        *       3DSTATE_DEPTH.SuraceFormat = D16_UNORM
 823        *       3DSTATE_DEPTH.SurfaceBaseAddress = 0
 824        *       3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
 825        *       3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
 826        *       3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
 827        *
 828        * The PRM is wrong, though. The width and height must be programmed to
 829        * actual framebuffer's width and height, even when neither depth buffer
 830        * nor stencil buffer is present.
 831        */
 832       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DEPTH_BUFFER,
 833          .SurfaceType = SURFTYPE_2D,
 834          .SurfaceFormat = D16_UNORM,
 835          .Width = fb->width - 1,
 836          .Height = fb->height - 1,
 837          .StencilWriteEnable = has_stencil);
 838    }
 839
 840    /* Emit 3DSTATE_STENCIL_BUFFER */
 841    if (has_stencil) {
 842       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER,
 843          .StencilBufferObjectControlState = GEN7_MOCS,
 844
 845          /* Stencil buffers have strange pitch. The PRM says:
 846           *
 847           *    The pitch must be set to 2x the value computed based on width,
 848           *    as the stencil buffer is stored with two rows interleaved.
 849           */
 850          .SurfacePitch = 2 * image->stencil_surface.stride - 1,
 851
 852          .SurfaceBaseAddress = {
 853             .bo = image->bo,
 854             .offset = image->offset + image->stencil_surface.offset,
 855          });
 856    } else {
 857       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER);
 858    }
 859
 860    /* Disable hierarchial depth buffers. */
 861    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER);
 862
 863    /* Clear the clear params. */
 864    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS);
 865 }
 866
 867 GENX_FUNC(GEN7, GEN7) void
 868 genX(cmd_buffer_begin_subpass)(struct anv_cmd_buffer *cmd_buffer,
 869                                struct anv_subpass *subpass)
 870 {
 871    cmd_buffer->state.subpass = subpass;
 872    cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
 873
 874    cmd_buffer_emit_depth_stencil(cmd_buffer);
 875 }
 876
 877 static void
 878 begin_render_pass(struct anv_cmd_buffer *cmd_buffer,
 879                   const VkRenderPassBeginInfo* pRenderPassBegin)
 880 {
 881    ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
 882    ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
 883
 884    cmd_buffer->state.framebuffer = framebuffer;
 885    cmd_buffer->state.pass = pass;
 886
 887    const VkRect2D *render_area = &pRenderPassBegin->renderArea;
 888
 889    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DRAWING_RECTANGLE,
 890                   .ClippedDrawingRectangleYMin = render_area->offset.y,
 891                   .ClippedDrawingRectangleXMin = render_area->offset.x,
 892                   .ClippedDrawingRectangleYMax =
 893                      render_area->offset.y + render_area->extent.height - 1,
 894                   .ClippedDrawingRectangleXMax =
 895                      render_area->offset.x + render_area->extent.width - 1,
 896                   .DrawingRectangleOriginY = 0,
 897                   .DrawingRectangleOriginX = 0);
 898
 899    anv_cmd_buffer_clear_attachments(cmd_buffer, pass,
 900                                     pRenderPassBegin->pClearValues);
 901 }
 902
 903 void genX(CmdBeginRenderPass)(
 904     VkCmdBuffer                                 cmdBuffer,
 905     const VkRenderPassBeginInfo*                pRenderPassBegin,
 906     VkRenderPassContents                        contents)
 907 {
 908    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 909    ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
 910
 911    begin_render_pass(cmd_buffer, pRenderPassBegin);
 912
 913    gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
 914 }
 915
 916 void genX(CmdNextSubpass)(
 917     VkCmdBuffer                                 cmdBuffer,
 918     VkRenderPassContents                        contents)
 919 {
 920    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 921
 922    assert(cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
 923
 924    gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
 925 }
 926
 927 void genX(CmdEndRenderPass)(
 928     VkCmdBuffer                                 cmdBuffer)
 929 {
 930    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
 931
 932    /* Emit a flushing pipe control at the end of a pass.  This is kind of a
 933     * hack but it ensures that render targets always actually get written.
 934     * Eventually, we should do flushing based on image format transitions
 935     * or something of that nature.
 936     */
 937    anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
 938                   .PostSyncOperation = NoWrite,
 939                   .RenderTargetCacheFlushEnable = true,
 940                   .InstructionCacheInvalidateEnable = true,
 941                   .DepthCacheFlushEnable = true,
 942                   .VFCacheInvalidationEnable = true,
 943                   .TextureCacheInvalidationEnable = true,
 944                   .CommandStreamerStallEnable = true);
 945 }