src/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
  37 {
  38    static const uint32_t push_constant_opcodes[] = {
  39       [MESA_SHADER_VERTEX]                      = 21,
  40       [MESA_SHADER_TESS_CTRL]                   = 25, /* HS */
  41       [MESA_SHADER_TESS_EVAL]                   = 26, /* DS */
  42       [MESA_SHADER_GEOMETRY]                    = 22,
  43       [MESA_SHADER_FRAGMENT]                    = 23,
  44       [MESA_SHADER_COMPUTE]                     = 0,
  45    };
  46
  47    VkShaderStageFlags flushed = 0;
  48
  49    anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
  50       struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
  51
  52       if (state.offset == 0)
  53          continue;
  54
  55       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CONSTANT_VS,
  56                      ._3DCommandSubOpcode = push_constant_opcodes[stage],
  57                      .ConstantBody = {
  58                         .PointerToConstantBuffer0 = { .offset = state.offset },
  59                         .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
  60                      });
  61
  62       flushed |= mesa_to_vk_shader_stage(stage);
  63    }
  64
  65    cmd_buffer->state.push_constants_dirty &= ~flushed;
  66 }
  67
  68 static VkResult
  69 flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, gl_shader_stage stage)
  70 {
  71    struct anv_state surfaces = { 0, }, samplers = { 0, };
  72    VkResult result;
  73
  74    result = anv_cmd_buffer_emit_samplers(cmd_buffer, stage, &samplers);
  75    if (result != VK_SUCCESS)
  76       return result;
  77    result = anv_cmd_buffer_emit_binding_table(cmd_buffer, stage, &surfaces);
  78    if (result != VK_SUCCESS)
  79       return result;
  80
  81    static const uint32_t sampler_state_opcodes[] = {
  82       [MESA_SHADER_VERTEX]                      = 43,
  83       [MESA_SHADER_TESS_CTRL]                   = 44, /* HS */
  84       [MESA_SHADER_TESS_EVAL]                   = 45, /* DS */
  85       [MESA_SHADER_GEOMETRY]                    = 46,
  86       [MESA_SHADER_FRAGMENT]                    = 47,
  87       [MESA_SHADER_COMPUTE]                     = 0,
  88    };
  89
  90    static const uint32_t binding_table_opcodes[] = {
  91       [MESA_SHADER_VERTEX]                      = 38,
  92       [MESA_SHADER_TESS_CTRL]                   = 39,
  93       [MESA_SHADER_TESS_EVAL]                   = 40,
  94       [MESA_SHADER_GEOMETRY]                    = 41,
  95       [MESA_SHADER_FRAGMENT]                    = 42,
  96       [MESA_SHADER_COMPUTE]                     = 0,
  97    };
  98
  99    if (samplers.alloc_size > 0) {
 100       anv_batch_emit(&cmd_buffer->batch,
 101                      GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS,
 102                      ._3DCommandSubOpcode  = sampler_state_opcodes[stage],
 103                      .PointertoVSSamplerState = samplers.offset);
 104    }
 105
 106    if (surfaces.alloc_size > 0) {
 107       anv_batch_emit(&cmd_buffer->batch,
 108                      GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS,
 109                      ._3DCommandSubOpcode  = binding_table_opcodes[stage],
 110                      .PointertoVSBindingTable = surfaces.offset);
 111    }
 112
 113    return VK_SUCCESS;
 114 }
 115
 116 GENX_FUNC(GEN7, GEN7) void
 117 genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer)
 118 {
 119    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
 120                               cmd_buffer->state.pipeline->active_stages;
 121
 122    VkResult result = VK_SUCCESS;
 123    anv_foreach_stage(s, dirty) {
 124       result = flush_descriptor_set(cmd_buffer, s);
 125       if (result != VK_SUCCESS)
 126          break;
 127    }
 128
 129    if (result != VK_SUCCESS) {
 130       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
 131
 132       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
 133       assert(result == VK_SUCCESS);
 134
 135       /* Re-emit state base addresses so we get the new surface state base
 136        * address before we start emitting binding tables etc.
 137        */
 138       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 139
 140       /* Re-emit all active binding tables */
 141       anv_foreach_stage(s, cmd_buffer->state.pipeline->active_stages) {
 142          result = flush_descriptor_set(cmd_buffer, s);
 143
 144          /* It had better succeed this time */
 145          assert(result == VK_SUCCESS);
 146       }
 147    }
 148
 149    cmd_buffer->state.descriptors_dirty &= ~cmd_buffer->state.pipeline->active_stages;
 150 }
 151
 152 static inline int64_t
 153 clamp_int64(int64_t x, int64_t min, int64_t max)
 154 {
 155    if (x < min)
 156       return min;
 157    else if (x < max)
 158       return x;
 159    else
 160       return max;
 161 }
 162
 163 static void
 164 emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
 165                    uint32_t count, const VkRect2D *scissors)
 166 {
 167    struct anv_state scissor_state =
 168       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 32, 32);
 169
 170    for (uint32_t i = 0; i < count; i++) {
 171       const VkRect2D *s = &scissors[i];
 172
 173       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 174        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 175        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 176        * what we want. Just special case empty clips and produce a canonical
 177        * empty clip. */
 178       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 179          .ScissorRectangleYMin = 1,
 180          .ScissorRectangleXMin = 1,
 181          .ScissorRectangleYMax = 0,
 182          .ScissorRectangleXMax = 0
 183       };
 184
 185       const int max = 0xffff;
 186       struct GEN7_SCISSOR_RECT scissor = {
 187          /* Do this math using int64_t so overflow gets clamped correctly. */
 188          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 189          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 190          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 191          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 192       };
 193
 194       if (s->extent.width <= 0 || s->extent.height <= 0) {
 195          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32,
 196                                 &empty_scissor);
 197       } else {
 198          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 32, &scissor);
 199       }
 200    }
 201
 202    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
 203                   .ScissorRectPointer = scissor_state.offset);
 204
 205    if (!cmd_buffer->device->info.has_llc)
 206       anv_state_clflush(scissor_state);
 207 }
 208
 209 GENX_FUNC(GEN7, GEN7) void
 210 genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
 211 {
 212    if (cmd_buffer->state.dynamic.scissor.count > 0) {
 213       emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
 214                          cmd_buffer->state.dynamic.scissor.scissors);
 215    } else {
 216       /* Emit a default scissor based on the currently bound framebuffer */
 217       emit_scissor_state(cmd_buffer, 1,
 218                          &(VkRect2D) {
 219                             .offset = { .x = 0, .y = 0, },
 220                             .extent = {
 221                                .width = cmd_buffer->state.framebuffer->width,
 222                                .height = cmd_buffer->state.framebuffer->height,
 223                             },
 224                          });
 225    }
 226 }
 227
 228 static const uint32_t vk_to_gen_index_type[] = {
 229    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 230    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 231 };
 232
 233 static const uint32_t restart_index_for_type[] = {
 234    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 235    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 236 };
 237
 238 void genX(CmdBindIndexBuffer)(
 239     VkCommandBuffer                             commandBuffer,
 240     VkBuffer                                    _buffer,
 241     VkDeviceSize                                offset,
 242     VkIndexType                                 indexType)
 243 {
 244    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 245    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 246
 247    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 248    if (ANV_IS_HASWELL)
 249       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 250    cmd_buffer->state.gen7.index_buffer = buffer;
 251    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 252    cmd_buffer->state.gen7.index_offset = offset;
 253 }
 254
 255 static VkResult
 256 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 257 {
 258    struct anv_device *device = cmd_buffer->device;
 259    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 260    struct anv_state surfaces = { 0, }, samplers = { 0, };
 261    VkResult result;
 262
 263    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 264                                          MESA_SHADER_COMPUTE, &samplers);
 265    if (result != VK_SUCCESS)
 266       return result;
 267    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 268                                               MESA_SHADER_COMPUTE, &surfaces);
 269    if (result != VK_SUCCESS)
 270       return result;
 271
 272    struct anv_state state =
 273       anv_state_pool_emit(&device->dynamic_state_pool,
 274                           GEN7_INTERFACE_DESCRIPTOR_DATA, 64,
 275                           .KernelStartPointer = pipeline->cs_simd,
 276                           .BindingTablePointer = surfaces.offset,
 277                           .SamplerStatePointer = samplers.offset,
 278                           .NumberofThreadsinGPGPUThreadGroup = 0);
 279
 280    const uint32_t size = GEN7_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
 281    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
 282                   .InterfaceDescriptorTotalLength = size,
 283                   .InterfaceDescriptorDataStartAddress = state.offset);
 284
 285    return VK_SUCCESS;
 286 }
 287
 288 static void
 289 cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
 290 {
 291    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 292    VkResult result;
 293
 294    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 295
 296    if (cmd_buffer->state.current_pipeline != GPGPU) {
 297       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
 298                      .PipelineSelection = GPGPU);
 299       cmd_buffer->state.current_pipeline = GPGPU;
 300    }
 301
 302    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 303       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 304
 305    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 306        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 307       /* FIXME: figure out descriptors for gen7 */
 308       result = flush_compute_descriptor_set(cmd_buffer);
 309       assert(result == VK_SUCCESS);
 310       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 311    }
 312
 313    cmd_buffer->state.compute_dirty = 0;
 314 }
 315
 316 static void
 317 cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
 318 {
 319    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 320    uint32_t *p;
 321
 322    uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
 323
 324    assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 325
 326    if (cmd_buffer->state.current_pipeline != _3D) {
 327       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPELINE_SELECT,
 328                      .PipelineSelection = _3D);
 329       cmd_buffer->state.current_pipeline = _3D;
 330    }
 331
 332    if (vb_emit) {
 333       const uint32_t num_buffers = __builtin_popcount(vb_emit);
 334       const uint32_t num_dwords = 1 + num_buffers * 4;
 335
 336       p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
 337                           GEN7_3DSTATE_VERTEX_BUFFERS);
 338       uint32_t vb, i = 0;
 339       for_each_bit(vb, vb_emit) {
 340          struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
 341          uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
 342
 343          struct GEN7_VERTEX_BUFFER_STATE state = {
 344             .VertexBufferIndex = vb,
 345             .BufferAccessType = pipeline->instancing_enable[vb] ? INSTANCEDATA : VERTEXDATA,
 346             .VertexBufferMemoryObjectControlState = GEN7_MOCS,
 347             .AddressModifyEnable = true,
 348             .BufferPitch = pipeline->binding_stride[vb],
 349             .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 350             .EndAddress = { buffer->bo, buffer->offset + buffer->size - 1},
 351             .InstanceDataStepRate = 1
 352          };
 353
 354          GEN7_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
 355          i++;
 356       }
 357    }
 358
 359    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
 360       /* If somebody compiled a pipeline after starting a command buffer the
 361        * scratch bo may have grown since we started this cmd buffer (and
 362        * emitted STATE_BASE_ADDRESS).  If we're binding that pipeline now,
 363        * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
 364       if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
 365          gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
 366
 367       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 368    }
 369
 370    if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
 371        cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
 372       /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 373        *
 374        *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 375        *    stall needs to be sent just prior to any 3DSTATE_VS,
 376        *    3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
 377        *    3DSTATE_BINDING_TABLE_POINTER_VS,
 378        *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one
 379        *    PIPE_CONTROL needs to be sent before any combination of VS
 380        *    associated 3DSTATE."
 381        */
 382       anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
 383                      .DepthStallEnable = true,
 384                      .PostSyncOperation = WriteImmediateData,
 385                      .Address = { &cmd_buffer->device->workaround_bo, 0 });
 386    }
 387
 388    if (cmd_buffer->state.descriptors_dirty)
 389       gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
 390
 391    if (cmd_buffer->state.push_constants_dirty)
 392       cmd_buffer_flush_push_constants(cmd_buffer);
 393
 394    /* We use the gen8 state here because it only contains the additional
 395     * min/max fields and, since they occur at the end of the packet and
 396     * don't change the stride, they work on gen7 too.
 397     */
 398    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
 399       gen8_cmd_buffer_emit_viewport(cmd_buffer);
 400
 401    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
 402       gen7_cmd_buffer_emit_scissor(cmd_buffer);
 403
 404    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 405                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 406                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 407
 408       bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
 409          cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
 410
 411       uint32_t sf_dw[GEN7_3DSTATE_SF_length];
 412       struct GEN7_3DSTATE_SF sf = {
 413          GEN7_3DSTATE_SF_header,
 414          .LineWidth = cmd_buffer->state.dynamic.line_width,
 415          .GlobalDepthOffsetEnableSolid = enable_bias,
 416          .GlobalDepthOffsetEnableWireframe = enable_bias,
 417          .GlobalDepthOffsetEnablePoint = enable_bias,
 418          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 419          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 420          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 421       };
 422       GEN7_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 423
 424       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 425    }
 426
 427    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 428                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 429       struct anv_state cc_state =
 430          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 431                                             GEN7_COLOR_CALC_STATE_length * 4,
 432                                             64);
 433       struct GEN7_COLOR_CALC_STATE cc = {
 434          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 435          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 436          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 437          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 438          .StencilReferenceValue =
 439             cmd_buffer->state.dynamic.stencil_reference.front,
 440          .BackFaceStencilReferenceValue =
 441             cmd_buffer->state.dynamic.stencil_reference.back,
 442       };
 443       GEN7_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 444       if (!cmd_buffer->device->info.has_llc)
 445          anv_state_clflush(cc_state);
 446
 447       anv_batch_emit(&cmd_buffer->batch,
 448                      GEN7_3DSTATE_CC_STATE_POINTERS,
 449                      .ColorCalcStatePointer = cc_state.offset);
 450    }
 451
 452    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 453                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 454                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 455                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 456       uint32_t depth_stencil_dw[GEN7_DEPTH_STENCIL_STATE_length];
 457
 458       const struct anv_image_view *iview =
 459          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 460
 461       struct GEN7_DEPTH_STENCIL_STATE depth_stencil = {
 462          .StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
 463
 464          .StencilTestMask =
 465             cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
 466          .StencilWriteMask =
 467             cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
 468
 469          .BackfaceStencilTestMask =
 470             cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
 471          .BackfaceStencilWriteMask =
 472             cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
 473       };
 474       GEN7_DEPTH_STENCIL_STATE_pack(NULL, depth_stencil_dw, &depth_stencil);
 475
 476       struct anv_state ds_state =
 477          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 478                                       pipeline->gen7.depth_stencil_state,
 479                                       GEN7_DEPTH_STENCIL_STATE_length, 64);
 480
 481       anv_batch_emit(&cmd_buffer->batch,
 482                      GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
 483                      .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
 484    }
 485
 486    if (cmd_buffer->state.gen7.index_buffer &&
 487        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 488                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 489       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 490       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 491
 492       if (ANV_IS_HASWELL) {
 493          anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
 494                         .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 495                         .CutIndex = cmd_buffer->state.restart_index);
 496       }
 497
 498       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
 499                      .CutIndexEnable = pipeline->primitive_restart,
 500                      .IndexFormat = cmd_buffer->state.gen7.index_type,
 501                      .MemoryObjectControlState = GEN7_MOCS,
 502                      .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 503                      .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
 504    }
 505
 506    cmd_buffer->state.vb_dirty &= ~vb_emit;
 507    cmd_buffer->state.dirty = 0;
 508 }
 509
 510 void genX(CmdDraw)(
 511     VkCommandBuffer                             commandBuffer,
 512     uint32_t                                    vertexCount,
 513     uint32_t                                    instanceCount,
 514     uint32_t                                    firstVertex,
 515     uint32_t                                    firstInstance)
 516 {
 517    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 518    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 519
 520    cmd_buffer_flush_state(cmd_buffer);
 521
 522    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 523                   .VertexAccessType = SEQUENTIAL,
 524                   .PrimitiveTopologyType = pipeline->topology,
 525                   .VertexCountPerInstance = vertexCount,
 526                   .StartVertexLocation = firstVertex,
 527                   .InstanceCount = instanceCount,
 528                   .StartInstanceLocation = firstInstance,
 529                   .BaseVertexLocation = 0);
 530 }
 531
 532 void genX(CmdDrawIndexed)(
 533     VkCommandBuffer                             commandBuffer,
 534     uint32_t                                    indexCount,
 535     uint32_t                                    instanceCount,
 536     uint32_t                                    firstIndex,
 537     int32_t                                     vertexOffset,
 538     uint32_t                                    firstInstance)
 539 {
 540    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 541    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 542
 543    cmd_buffer_flush_state(cmd_buffer);
 544
 545    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 546                   .VertexAccessType = RANDOM,
 547                   .PrimitiveTopologyType = pipeline->topology,
 548                   .VertexCountPerInstance = indexCount,
 549                   .StartVertexLocation = firstIndex,
 550                   .InstanceCount = instanceCount,
 551                   .StartInstanceLocation = firstInstance,
 552                   .BaseVertexLocation = vertexOffset);
 553 }
 554
 555 static void
 556 gen7_batch_lrm(struct anv_batch *batch,
 557               uint32_t reg, struct anv_bo *bo, uint32_t offset)
 558 {
 559    anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_MEM,
 560                   .RegisterAddress = reg,
 561                   .MemoryAddress = { bo, offset });
 562 }
 563
 564 static void
 565 gen7_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
 566 {
 567    anv_batch_emit(batch, GEN7_MI_LOAD_REGISTER_IMM,
 568                   .RegisterOffset = reg,
 569                   .DataDWord = imm);
 570 }
 571
 572 /* Auto-Draw / Indirect Registers */
 573 #define GEN7_3DPRIM_END_OFFSET          0x2420
 574 #define GEN7_3DPRIM_START_VERTEX        0x2430
 575 #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
 576 #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
 577 #define GEN7_3DPRIM_START_INSTANCE      0x243C
 578 #define GEN7_3DPRIM_BASE_VERTEX         0x2440
 579
 580 void genX(CmdDrawIndirect)(
 581     VkCommandBuffer                             commandBuffer,
 582     VkBuffer                                    _buffer,
 583     VkDeviceSize                                offset,
 584     uint32_t                                    drawCount,
 585     uint32_t                                    stride)
 586 {
 587    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 588    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 589    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 590    struct anv_bo *bo = buffer->bo;
 591    uint32_t bo_offset = buffer->offset + offset;
 592
 593    cmd_buffer_flush_state(cmd_buffer);
 594
 595    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
 596    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
 597    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
 598    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
 599    gen7_batch_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
 600
 601    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 602                   .IndirectParameterEnable = true,
 603                   .VertexAccessType = SEQUENTIAL,
 604                   .PrimitiveTopologyType = pipeline->topology);
 605 }
 606
 607 void genX(CmdDrawIndexedIndirect)(
 608     VkCommandBuffer                             commandBuffer,
 609     VkBuffer                                    _buffer,
 610     VkDeviceSize                                offset,
 611     uint32_t                                    drawCount,
 612     uint32_t                                    stride)
 613 {
 614    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 615    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 616    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 617    struct anv_bo *bo = buffer->bo;
 618    uint32_t bo_offset = buffer->offset + offset;
 619
 620    cmd_buffer_flush_state(cmd_buffer);
 621
 622    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
 623    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
 624    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
 625    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
 626    gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
 627
 628    anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
 629                   .IndirectParameterEnable = true,
 630                   .VertexAccessType = RANDOM,
 631                   .PrimitiveTopologyType = pipeline->topology);
 632 }
 633
 634 void genX(CmdDispatch)(
 635     VkCommandBuffer                             commandBuffer,
 636     uint32_t                                    x,
 637     uint32_t                                    y,
 638     uint32_t                                    z)
 639 {
 640    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 641    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 642    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 643
 644    cmd_buffer_flush_compute_state(cmd_buffer);
 645
 646    anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
 647                   .SIMDSize = prog_data->simd_size / 16,
 648                   .ThreadDepthCounterMaximum = 0,
 649                   .ThreadHeightCounterMaximum = 0,
 650                   .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
 651                   .ThreadGroupIDXDimension = x,
 652                   .ThreadGroupIDYDimension = y,
 653                   .ThreadGroupIDZDimension = z,
 654                   .RightExecutionMask = pipeline->cs_right_mask,
 655                   .BottomExecutionMask = 0xffffffff);
 656
 657    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
 658 }
 659
 660 #define GPGPU_DISPATCHDIMX 0x2500
 661 #define GPGPU_DISPATCHDIMY 0x2504
 662 #define GPGPU_DISPATCHDIMZ 0x2508
 663
 664 void genX(CmdDispatchIndirect)(
 665     VkCommandBuffer                             commandBuffer,
 666     VkBuffer                                    _buffer,
 667     VkDeviceSize                                offset)
 668 {
 669    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 670    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 671    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 672    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 673    struct anv_bo *bo = buffer->bo;
 674    uint32_t bo_offset = buffer->offset + offset;
 675
 676    cmd_buffer_flush_compute_state(cmd_buffer);
 677
 678    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
 679    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
 680    gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
 681
 682    anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
 683                   .IndirectParameterEnable = true,
 684                   .SIMDSize = prog_data->simd_size / 16,
 685                   .ThreadDepthCounterMaximum = 0,
 686                   .ThreadHeightCounterMaximum = 0,
 687                   .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
 688                   .RightExecutionMask = pipeline->cs_right_mask,
 689                   .BottomExecutionMask = 0xffffffff);
 690
 691    anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
 692 }
 693
 694 static void
 695 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
 696 {
 697    const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
 698    const struct anv_image_view *iview =
 699       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 700    const struct anv_image *image = iview ? iview->image : NULL;
 701
 702    /* XXX: isl needs to grow depth format support */
 703    const struct anv_format *anv_format =
 704       iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
 705
 706    const bool has_depth = iview && anv_format->depth_format;
 707    const bool has_stencil = iview && anv_format->has_stencil;
 708
 709    /* Emit 3DSTATE_DEPTH_BUFFER */
 710    if (has_depth) {
 711       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
 712          .SurfaceType = SURFTYPE_2D,
 713          .DepthWriteEnable = true,
 714          .StencilWriteEnable = has_stencil,
 715          .HierarchicalDepthBufferEnable = false,
 716          .SurfaceFormat = anv_format->depth_format,
 717          .SurfacePitch = image->depth_surface.isl.row_pitch - 1,
 718          .SurfaceBaseAddress = {
 719             .bo = image->bo,
 720             .offset = image->depth_surface.offset,
 721          },
 722          .Height = fb->height - 1,
 723          .Width = fb->width - 1,
 724          .LOD = 0,
 725          .Depth = 1 - 1,
 726          .MinimumArrayElement = 0,
 727          .DepthBufferObjectControlState = GENX(MOCS),
 728          .RenderTargetViewExtent = 1 - 1);
 729    } else {
 730       /* Even when no depth buffer is present, the hardware requires that
 731        * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
 732        *
 733        *    If a null depth buffer is bound, the driver must instead bind depth as:
 734        *       3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
 735        *       3DSTATE_DEPTH.Width = 1
 736        *       3DSTATE_DEPTH.Height = 1
 737        *       3DSTATE_DEPTH.SuraceFormat = D16_UNORM
 738        *       3DSTATE_DEPTH.SurfaceBaseAddress = 0
 739        *       3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
 740        *       3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
 741        *       3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
 742        *
 743        * The PRM is wrong, though. The width and height must be programmed to
 744        * actual framebuffer's width and height, even when neither depth buffer
 745        * nor stencil buffer is present.
 746        */
 747       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
 748          .SurfaceType = SURFTYPE_2D,
 749          .SurfaceFormat = D16_UNORM,
 750          .Width = fb->width - 1,
 751          .Height = fb->height - 1,
 752          .StencilWriteEnable = has_stencil);
 753    }
 754
 755    /* Emit 3DSTATE_STENCIL_BUFFER */
 756    if (has_stencil) {
 757       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
 758 #     if (ANV_IS_HASWELL)
 759          .StencilBufferEnable = true,
 760 #     endif
 761          .StencilBufferObjectControlState = GENX(MOCS),
 762
 763          /* Stencil buffers have strange pitch. The PRM says:
 764           *
 765           *    The pitch must be set to 2x the value computed based on width,
 766           *    as the stencil buffer is stored with two rows interleaved.
 767           */
 768          .SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
 769
 770          .SurfaceBaseAddress = {
 771             .bo = image->bo,
 772             .offset = image->offset + image->stencil_surface.offset,
 773          });
 774    } else {
 775       anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_STENCIL_BUFFER);
 776    }
 777
 778    /* Disable hierarchial depth buffers. */
 779    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_HIER_DEPTH_BUFFER);
 780
 781    /* Clear the clear params. */
 782    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS);
 783 }
 784
 785 GENX_FUNC(GEN7, GEN7) void
 786 genX(cmd_buffer_begin_subpass)(struct anv_cmd_buffer *cmd_buffer,
 787                                struct anv_subpass *subpass)
 788 {
 789    cmd_buffer->state.subpass = subpass;
 790    cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
 791    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
 792
 793    cmd_buffer_emit_depth_stencil(cmd_buffer);
 794 }
 795
 796 static void
 797 begin_render_pass(struct anv_cmd_buffer *cmd_buffer,
 798                   const VkRenderPassBeginInfo* pRenderPassBegin)
 799 {
 800    ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
 801    ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
 802
 803    cmd_buffer->state.framebuffer = framebuffer;
 804    cmd_buffer->state.pass = pass;
 805
 806    const VkRect2D *render_area = &pRenderPassBegin->renderArea;
 807
 808    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_DRAWING_RECTANGLE,
 809                   .ClippedDrawingRectangleYMin = render_area->offset.y,
 810                   .ClippedDrawingRectangleXMin = render_area->offset.x,
 811                   .ClippedDrawingRectangleYMax =
 812                      render_area->offset.y + render_area->extent.height - 1,
 813                   .ClippedDrawingRectangleXMax =
 814                      render_area->offset.x + render_area->extent.width - 1,
 815                   .DrawingRectangleOriginY = 0,
 816                   .DrawingRectangleOriginX = 0);
 817
 818    anv_cmd_buffer_clear_attachments(cmd_buffer, pass,
 819                                     pRenderPassBegin->pClearValues);
 820 }
 821
 822 void genX(CmdBeginRenderPass)(
 823     VkCommandBuffer                             commandBuffer,
 824     const VkRenderPassBeginInfo*                pRenderPassBegin,
 825     VkSubpassContents                           contents)
 826 {
 827    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 828    ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
 829
 830    begin_render_pass(cmd_buffer, pRenderPassBegin);
 831
 832    gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
 833 }
 834
 835 void genX(CmdNextSubpass)(
 836     VkCommandBuffer                             commandBuffer,
 837     VkSubpassContents                           contents)
 838 {
 839    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 840
 841    assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
 842
 843    gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
 844 }
 845
 846 void genX(CmdEndRenderPass)(
 847     VkCommandBuffer                             commandBuffer)
 848 {
 849    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 850
 851    /* Emit a flushing pipe control at the end of a pass.  This is kind of a
 852     * hack but it ensures that render targets always actually get written.
 853     * Eventually, we should do flushing based on image format transitions
 854     * or something of that nature.
 855     */
 856    anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
 857                   .PostSyncOperation = NoWrite,
 858                   .RenderTargetCacheFlushEnable = true,
 859                   .InstructionCacheInvalidateEnable = true,
 860                   .DepthCacheFlushEnable = true,
 861                   .VFCacheInvalidationEnable = true,
 862                   .TextureCacheInvalidationEnable = true,
 863                   .CommandStreamerStallEnable = true);
 864 }
 865
 866 void genX(CmdSetEvent)(
 867     VkCommandBuffer                             commandBuffer,
 868     VkEvent                                     event,
 869     VkPipelineStageFlags                        stageMask)
 870 {
 871    stub();
 872 }
 873
 874 void genX(CmdResetEvent)(
 875     VkCommandBuffer                             commandBuffer,
 876     VkEvent                                     event,
 877     VkPipelineStageFlags                        stageMask)
 878 {
 879    stub();
 880 }
 881
 882 void genX(CmdWaitEvents)(
 883     VkCommandBuffer                             commandBuffer,
 884     uint32_t                                    eventCount,
 885     const VkEvent*                              pEvents,
 886     VkPipelineStageFlags                        srcStageMask,
 887     VkPipelineStageFlags                        destStageMask,
 888     uint32_t                                    memBarrierCount,
 889     const void* const*                          ppMemBarriers)
 890 {
 891    stub();
 892 }