src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 static void
  33 gen7_emit_vertex_input(struct anv_pipeline *pipeline,
  34                        const VkPipelineVertexInputStateCreateInfo *info)
  35 {
  36    const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
  37       pipeline->vs_prog_data.uses_instanceid;
  38    const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0);
  39    const uint32_t num_dwords = 1 + element_count * 2;
  40    uint32_t *p;
  41
  42    if (info->attributeCount == 0 && !sgvs)
  43       return;
  44
  45    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  46                        GEN7_3DSTATE_VERTEX_ELEMENTS);
  47
  48    for (uint32_t i = 0; i < info->attributeCount; i++) {
  49       const VkVertexInputAttributeDescription *desc =
  50          &info->pVertexAttributeDescriptions[i];
  51       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  52
  53       struct GEN7_VERTEX_ELEMENT_STATE element = {
  54          .VertexBufferIndex = desc->binding,
  55          .Valid = true,
  56          .SourceElementFormat = format->surface_format,
  57          .EdgeFlagEnable = false,
  58          .SourceElementOffset = desc->offsetInBytes,
  59          .Component0Control = VFCOMP_STORE_SRC,
  60          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  61          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  62          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  63       };
  64       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  65    }
  66
  67    if (sgvs) {
  68       struct GEN7_VERTEX_ELEMENT_STATE element = {
  69          .Valid = true,
  70          /* FIXME: Do we need to provide the base vertex as component 0 here
  71           * to support the correct base vertex ID? */
  72          .Component0Control = VFCOMP_STORE_0,
  73          .Component1Control = VFCOMP_STORE_0,
  74          .Component2Control = VFCOMP_STORE_VID,
  75          .Component3Control = VFCOMP_STORE_IID
  76       };
  77       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element);
  78    }
  79 }
  80
  81 static const uint32_t vk_to_gen_cullmode[] = {
  82    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
  83    [VK_CULL_MODE_FRONT]                         = CULLMODE_FRONT,
  84    [VK_CULL_MODE_BACK]                          = CULLMODE_BACK,
  85    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
  86 };
  87
  88 static const uint32_t vk_to_gen_fillmode[] = {
  89    [VK_FILL_MODE_POINTS]                        = RASTER_POINT,
  90    [VK_FILL_MODE_WIREFRAME]                     = RASTER_WIREFRAME,
  91    [VK_FILL_MODE_SOLID]                         = RASTER_SOLID
  92 };
  93
  94 static const uint32_t vk_to_gen_front_face[] = {
  95    [VK_FRONT_FACE_CCW]                          = CounterClockwise,
  96    [VK_FRONT_FACE_CW]                           = Clockwise
  97 };
  98
  99 static void
 100 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 101                    const VkPipelineRasterStateCreateInfo *info,
 102                    const struct anv_graphics_pipeline_create_info *extra)
 103 {
 104    struct GEN7_3DSTATE_SF sf = {
 105       GEN7_3DSTATE_SF_header,
 106
 107       /* FIXME: Get this from pass info */
 108       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 109
 110       /* LegacyGlobalDepthBiasEnable */
 111
 112       .StatisticsEnable                         = true,
 113       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->fillMode],
 114       .BackFaceFillMode                         = vk_to_gen_fillmode[info->fillMode],
 115       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 116       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 117       /* bool                                         AntiAliasingEnable; */
 118
 119       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 120
 121       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 122       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 123
 124       /* uint32_t                                     MultisampleRasterizationMode; */
 125       /* bool                                         LastPixelEnable; */
 126
 127       .TriangleStripListProvokingVertexSelect   = 0,
 128       .LineStripListProvokingVertexSelect       = 0,
 129       .TriangleFanProvokingVertexSelect         = 0,
 130
 131       /* uint32_t                                     AALineDistanceMode; */
 132       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 133       .UsePointWidthState                       = !pipeline->writes_point_size,
 134       .PointWidth                               = 1.0,
 135    };
 136
 137    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 138 }
 139
 140 static const uint32_t vk_to_gen_compare_op[] = {
 141    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 142    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 143    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 144    [VK_COMPARE_OP_LESS_EQUAL]                   = PREFILTEROPLEQUAL,
 145    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 146    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 147    [VK_COMPARE_OP_GREATER_EQUAL]                = PREFILTEROPGEQUAL,
 148    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 149 };
 150
 151 static const uint32_t vk_to_gen_stencil_op[] = {
 152    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 153    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 154    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 155    [VK_STENCIL_OP_INC_CLAMP]                    = STENCILOP_INCRSAT,
 156    [VK_STENCIL_OP_DEC_CLAMP]                    = STENCILOP_DECRSAT,
 157    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 158    [VK_STENCIL_OP_INC_WRAP]                     = STENCILOP_INCR,
 159    [VK_STENCIL_OP_DEC_WRAP]                     = STENCILOP_DECR,
 160 };
 161
 162 static const uint32_t vk_to_gen_blend_op[] = {
 163    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 164    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 165    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 166    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 167    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 168 };
 169
 170 static const uint32_t vk_to_gen_logic_op[] = {
 171    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 172    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 173    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 174    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 175    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 176    [VK_LOGIC_OP_NOOP]                           = LOGICOP_NOOP,
 177    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 178    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 179    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 180    [VK_LOGIC_OP_EQUIV]                          = LOGICOP_EQUIV,
 181    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 182    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 183    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 184    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 185    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 186    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 187 };
 188
 189 static const uint32_t vk_to_gen_blend[] = {
 190    [VK_BLEND_ZERO]                              = BLENDFACTOR_ZERO,
 191    [VK_BLEND_ONE]                               = BLENDFACTOR_ONE,
 192    [VK_BLEND_SRC_COLOR]                         = BLENDFACTOR_SRC_COLOR,
 193    [VK_BLEND_ONE_MINUS_SRC_COLOR]               = BLENDFACTOR_INV_SRC_COLOR,
 194    [VK_BLEND_DEST_COLOR]                        = BLENDFACTOR_DST_COLOR,
 195    [VK_BLEND_ONE_MINUS_DEST_COLOR]              = BLENDFACTOR_INV_DST_COLOR,
 196    [VK_BLEND_SRC_ALPHA]                         = BLENDFACTOR_SRC_ALPHA,
 197    [VK_BLEND_ONE_MINUS_SRC_ALPHA]               = BLENDFACTOR_INV_SRC_ALPHA,
 198    [VK_BLEND_DEST_ALPHA]                        = BLENDFACTOR_DST_ALPHA,
 199    [VK_BLEND_ONE_MINUS_DEST_ALPHA]              = BLENDFACTOR_INV_DST_ALPHA,
 200    [VK_BLEND_CONSTANT_COLOR]                    = BLENDFACTOR_CONST_COLOR,
 201    [VK_BLEND_ONE_MINUS_CONSTANT_COLOR]          = BLENDFACTOR_INV_CONST_COLOR,
 202    [VK_BLEND_CONSTANT_ALPHA]                    = BLENDFACTOR_CONST_ALPHA,
 203    [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA]          = BLENDFACTOR_INV_CONST_ALPHA,
 204    [VK_BLEND_SRC_ALPHA_SATURATE]                = BLENDFACTOR_SRC_ALPHA_SATURATE,
 205    [VK_BLEND_SRC1_COLOR]                        = BLENDFACTOR_SRC1_COLOR,
 206    [VK_BLEND_ONE_MINUS_SRC1_COLOR]              = BLENDFACTOR_INV_SRC1_COLOR,
 207    [VK_BLEND_SRC1_ALPHA]                        = BLENDFACTOR_SRC1_ALPHA,
 208    [VK_BLEND_ONE_MINUS_SRC1_ALPHA]              = BLENDFACTOR_INV_SRC1_ALPHA,
 209 };
 210
 211 static void
 212 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 213                    const VkPipelineDepthStencilStateCreateInfo *info)
 214 {
 215    if (info == NULL) {
 216       /* We're going to OR this together with the dynamic state.  We need
 217        * to make sure it's initialized to something useful.
 218        */
 219       memset(pipeline->gen7.depth_stencil_state, 0,
 220              sizeof(pipeline->gen7.depth_stencil_state));
 221       return;
 222    }
 223
 224    bool has_stencil = false;  /* enable if subpass has stencil? */
 225
 226    struct GEN7_DEPTH_STENCIL_STATE state = {
 227       /* Is this what we need to do? */
 228       .StencilBufferWriteEnable = has_stencil,
 229
 230       .StencilTestEnable = info->stencilTestEnable,
 231       .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
 232       .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
 233       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
 234       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
 235
 236       .DoubleSidedStencilEnable = true,
 237
 238       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
 239       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
 240       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
 241       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
 242
 243       .DepthTestEnable = info->depthTestEnable,
 244       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 245       .DepthBufferWriteEnable = info->depthWriteEnable,
 246    };
 247
 248    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 249 }
 250
 251 static void
 252 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 253                    const VkPipelineColorBlendStateCreateInfo *info)
 254 {
 255    struct anv_device *device = pipeline->device;
 256
 257    uint32_t num_dwords = GEN7_BLEND_STATE_length;
 258    pipeline->blend_state =
 259       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 260
 261    if (info->pAttachments == NULL) {
 262       struct GEN7_BLEND_STATE blend_state = {
 263          .ColorBufferBlendEnable = false,
 264          .WriteDisableAlpha = false,
 265          .WriteDisableRed = false,
 266          .WriteDisableGreen = false,
 267          .WriteDisableBlue = false,
 268       };
 269
 270       GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 271    } else {
 272       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 273        * can't implement this.
 274        */
 275       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 276
 277       struct GEN7_BLEND_STATE blend_state = {
 278          .ColorBufferBlendEnable = a->blendEnable,
 279          .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 280          .AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
 281
 282          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
 283          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
 284
 285          .ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
 286          .SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
 287          .DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
 288          .AlphaToCoverageEnable = info->alphaToCoverageEnable,
 289
 290 #     if 0
 291          bool                                         AlphaToOneEnable;
 292          bool                                         AlphaToCoverageDitherEnable;
 293 #     endif
 294
 295          .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
 296          .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
 297          .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
 298          .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
 299
 300          .LogicOpEnable = info->logicOpEnable,
 301          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 302
 303 #     if 0
 304          bool                                         AlphaTestEnable;
 305          uint32_t                                     AlphaTestFunction;
 306          bool                                         ColorDitherEnable;
 307          uint32_t                                     XDitherOffset;
 308          uint32_t                                     YDitherOffset;
 309          uint32_t                                     ColorClampRange;
 310          bool                                         PreBlendColorClampEnable;
 311          bool                                         PostBlendColorClampEnable;
 312 #     endif
 313       };
 314
 315       GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 316     }
 317
 318    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 319                   .BlendStatePointer = pipeline->blend_state.offset);
 320 }
 321
 322 static const uint32_t vk_to_gen_primitive_type[] = {
 323    [VK_PRIMITIVE_TOPOLOGY_POINT_LIST]           = _3DPRIM_POINTLIST,
 324    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST]            = _3DPRIM_LINELIST,
 325    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP]           = _3DPRIM_LINESTRIP,
 326    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST]        = _3DPRIM_TRILIST,
 327    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP]       = _3DPRIM_TRISTRIP,
 328    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN]         = _3DPRIM_TRIFAN,
 329    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ]        = _3DPRIM_LINELIST_ADJ,
 330    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ]       = _3DPRIM_LINESTRIP_ADJ,
 331    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ]    = _3DPRIM_TRILIST_ADJ,
 332    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ]   = _3DPRIM_TRISTRIP_ADJ,
 333    [VK_PRIMITIVE_TOPOLOGY_PATCH]                = _3DPRIM_PATCHLIST_1
 334 };
 335
 336 static inline uint32_t
 337 scratch_space(const struct brw_stage_prog_data *prog_data)
 338 {
 339    return ffs(prog_data->total_scratch / 1024);
 340 }
 341
 342 VkResult
 343 gen7_graphics_pipeline_create(
 344     VkDevice                                    _device,
 345     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 346     const struct anv_graphics_pipeline_create_info *extra,
 347     VkPipeline*                                 pPipeline)
 348 {
 349    ANV_FROM_HANDLE(anv_device, device, _device);
 350    struct anv_pipeline *pipeline;
 351    VkResult result;
 352
 353    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 354
 355    pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
 356                                VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 357    if (pipeline == NULL)
 358       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 359
 360    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
 361    if (result != VK_SUCCESS) {
 362       anv_device_free(device, pipeline);
 363       return result;
 364    }
 365
 366    assert(pCreateInfo->pVertexInputState);
 367    gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 368
 369    assert(pCreateInfo->pRasterState);
 370    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
 371
 372    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 373
 374    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
 375
 376    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 377                    .StatisticsEnable = true);
 378    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 379    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 380    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 381    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 382
 383    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 384     *
 385     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 386     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 387     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 388     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 389     *    needs to be sent before any combination of VS associated 3DSTATE."
 390     */
 391    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 392                   .DepthStallEnable = true,
 393                   .PostSyncOperation = WriteImmediateData,
 394                   .Address = { &device->workaround_bo, 0 });
 395
 396    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 397                   .ConstantBufferOffset = 0,
 398                   .ConstantBufferSize = 4);
 399    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 400                   .ConstantBufferOffset = 4,
 401                   .ConstantBufferSize = 4);
 402    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 403                   .ConstantBufferOffset = 8,
 404                   .ConstantBufferSize = 4);
 405
 406    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 407
 408    const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
 409
 410    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 411       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 412       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 413       .ClipEnable                               = true,
 414       .APIMode                                  = APIMODE_OGL,
 415       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 416       .ClipMode                                 = CLIPMODE_NORMAL,
 417       .TriangleStripListProvokingVertexSelect   = 0,
 418       .LineStripListProvokingVertexSelect       = 0,
 419       .TriangleFanProvokingVertexSelect         = 0,
 420       .MinimumPointWidth                        = 0.125,
 421       .MaximumPointWidth                        = 255.875);
 422
 423    uint32_t samples = 1;
 424    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 425
 426    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 427       .PixelLocation                            = PIXLOC_CENTER,
 428       .NumberofMultisamples                     = log2_samples);
 429
 430    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 431       .SampleMask                               = 0xff);
 432
 433    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 434       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 435       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 436       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 437
 438    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 439       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 440       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 441       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 442
 443    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 444       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 445       .HSURBEntryAllocationSize                 = 0,
 446       .HSNumberofURBEntries                     = 0);
 447
 448    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 449       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 450       .DSURBEntryAllocationSize                 = 0,
 451       .DSNumberofURBEntries                     = 0);
 452
 453    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 454    /* The last geometry producing stage will set urb_offset and urb_length,
 455     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 456    uint32_t urb_offset = 1;
 457    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 458
 459 #if 0
 460    /* From gen7_vs_state.c */
 461
 462    /**
 463     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 464     * Geometry > Geometry Shader > State:
 465     *
 466     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 467     *     whole fixed function pipeline when the GS enable changes value in
 468     *     the 3DSTATE_GS."
 469     *
 470     * The hardware architects have clarified that in this context "flush the
 471     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 472     * Stall" bit set.
 473     */
 474    if (!brw->is_haswell && !brw->is_baytrail)
 475       gen7_emit_vs_workaround_flush(brw);
 476 #endif
 477
 478    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 479       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false);
 480    else
 481       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS,
 482          .KernelStartPointer                    = pipeline->vs_vec4,
 483          .ScratchSpaceBaseOffset                = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
 484          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 485
 486          .DispatchGRFStartRegisterforURBData    =
 487             vue_prog_data->base.dispatch_grf_start_reg,
 488          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 489          .VertexURBEntryReadOffset              = 0,
 490
 491          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 492          .StatisticsEnable                      = true,
 493          .VSFunctionEnable                      = true);
 494
 495    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 496
 497    if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
 498       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false);
 499    } else {
 500       urb_offset = 1;
 501       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 502
 503       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS,
 504          .KernelStartPointer                    = pipeline->gs_vec4,
 505          .ScratchSpaceBasePointer               = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
 506          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 507
 508          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 509          .OutputTopology                        = gs_prog_data->output_topology,
 510          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 511          .DispatchGRFStartRegisterforURBData    =
 512             gs_prog_data->base.base.dispatch_grf_start_reg,
 513
 514          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 515          /* This in the next dword on HSW. */
 516          .ControlDataFormat                     = gs_prog_data->control_data_format,
 517          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 518          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 519          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 520          .GSStatisticsEnable                    = true,
 521          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 522          .ReorderEnable                         = true,
 523          .GSEnable                              = true);
 524    }
 525
 526    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 527    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 528        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 529       anv_finishme("two-sided color needs sbe swizzling setup");
 530    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 531       anv_finishme("primitive_id needs sbe swizzling setup");
 532
 533    /* FIXME: generated header doesn't emit attr swizzle fields */
 534    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 535       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 536       .VertexURBEntryReadLength                 = urb_length,
 537       .VertexURBEntryReadOffset                 = urb_offset,
 538       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 539
 540    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS,
 541       .KernelStartPointer0                      = pipeline->ps_ksp0,
 542       .ScratchSpaceBasePointer                  = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
 543       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 544
 545       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 546       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 547       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 548       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 549
 550       .RenderTargetFastClearEnable              = false,
 551       .DualSourceBlendEnable                    = false,
 552       .RenderTargetResolveEnable                = false,
 553
 554       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 555          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 556
 557       ._32PixelDispatchEnable                   = false,
 558       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 559       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 560
 561       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 562       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 563       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 564
 565 #if 0
 566    /* Haswell requires the sample mask to be set in this packet as well as
 567     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 568    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 569 #endif
 570
 571       .KernelStartPointer1                      = 0,
 572       .KernelStartPointer2                      = pipeline->ps_ksp2);
 573
 574    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 575    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 576       .StatisticsEnable                         = true,
 577       .ThreadDispatchEnable                     = true,
 578       .LineEndCapAntialiasingRegionWidth        = _05pixels,
 579       .LineAntialiasingRegionWidth              = _10pixels,
 580       .EarlyDepthStencilControl                 = NORMAL,
 581       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 582       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 583       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 584
 585    *pPipeline = anv_pipeline_to_handle(pipeline);
 586
 587    return VK_SUCCESS;
 588 }
 589
 590 VkResult gen7_compute_pipeline_create(
 591     VkDevice                                    _device,
 592     const VkComputePipelineCreateInfo*          pCreateInfo,
 593     VkPipeline*                                 pPipeline)
 594 {
 595    anv_finishme("primitive_id needs sbe swizzling setup");
 596    abort();
 597 }