src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 gen7_emit_vertex_input(struct anv_pipeline *pipeline,
  37                        const VkPipelineVertexInputStateCreateInfo *info)
  38 {
  39    const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
  40       pipeline->vs_prog_data.uses_instanceid;
  41    const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0);
  42    const uint32_t num_dwords = 1 + element_count * 2;
  43    uint32_t *p;
  44
  45    if (info->attributeCount == 0 && !sgvs)
  46       return;
  47
  48    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  49                        GEN7_3DSTATE_VERTEX_ELEMENTS);
  50
  51    for (uint32_t i = 0; i < info->attributeCount; i++) {
  52       const VkVertexInputAttributeDescription *desc =
  53          &info->pVertexAttributeDescriptions[i];
  54       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  55
  56       struct GEN7_VERTEX_ELEMENT_STATE element = {
  57          .VertexBufferIndex = desc->binding,
  58          .Valid = true,
  59          .SourceElementFormat = format->surface_format,
  60          .EdgeFlagEnable = false,
  61          .SourceElementOffset = desc->offsetInBytes,
  62          .Component0Control = VFCOMP_STORE_SRC,
  63          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  64          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  65          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  66       };
  67       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  68    }
  69
  70    if (sgvs) {
  71       struct GEN7_VERTEX_ELEMENT_STATE element = {
  72          .Valid = true,
  73          /* FIXME: Do we need to provide the base vertex as component 0 here
  74           * to support the correct base vertex ID? */
  75          .Component0Control = VFCOMP_STORE_0,
  76          .Component1Control = VFCOMP_STORE_0,
  77          .Component2Control = VFCOMP_STORE_VID,
  78          .Component3Control = VFCOMP_STORE_IID
  79       };
  80       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element);
  81    }
  82 }
  83
  84 static const uint32_t vk_to_gen_cullmode[] = {
  85    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
  86    [VK_CULL_MODE_FRONT_BIT]                     = CULLMODE_FRONT,
  87    [VK_CULL_MODE_BACK_BIT]                      = CULLMODE_BACK,
  88    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
  89 };
  90
  91 static const uint32_t vk_to_gen_fillmode[] = {
  92    [VK_POLYGON_MODE_FILL]                       = RASTER_SOLID,
  93    [VK_POLYGON_MODE_LINE]                       = RASTER_WIREFRAME,
  94    [VK_POLYGON_MODE_POINT]                      = RASTER_POINT,
  95 };
  96
  97 static const uint32_t vk_to_gen_front_face[] = {
  98    [VK_FRONT_FACE_COUNTER_CLOCKWISE]            = 1,
  99    [VK_FRONT_FACE_CLOCKWISE]                    = 0
 100 };
 101
 102 static void
 103 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 104                    const VkPipelineRasterStateCreateInfo *info,
 105                    const struct anv_graphics_pipeline_create_info *extra)
 106 {
 107    struct GEN7_3DSTATE_SF sf = {
 108       GEN7_3DSTATE_SF_header,
 109
 110       /* FIXME: Get this from pass info */
 111       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 112
 113       /* LegacyGlobalDepthBiasEnable */
 114
 115       .StatisticsEnable                         = true,
 116       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 117       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 118       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 119       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 120       /* bool                                         AntiAliasingEnable; */
 121
 122       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 123
 124       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 125       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 126
 127       /* uint32_t                                     MultisampleRasterizationMode; */
 128       /* bool                                         LastPixelEnable; */
 129
 130       .TriangleStripListProvokingVertexSelect   = 0,
 131       .LineStripListProvokingVertexSelect       = 0,
 132       .TriangleFanProvokingVertexSelect         = 0,
 133
 134       /* uint32_t                                     AALineDistanceMode; */
 135       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 136       .UsePointWidthState                       = !pipeline->writes_point_size,
 137       .PointWidth                               = 1.0,
 138    };
 139
 140    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 141 }
 142
 143 static const uint32_t vk_to_gen_compare_op[] = {
 144    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 145    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 146    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 147    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 148    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 149    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 150    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 151    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 152 };
 153
 154 static const uint32_t vk_to_gen_stencil_op[] = {
 155    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 156    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 157    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 158    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 159    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 160    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 161    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 162    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 163 };
 164
 165 static const uint32_t vk_to_gen_blend_op[] = {
 166    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 167    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 168    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 169    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 170    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 171 };
 172
 173 static const uint32_t vk_to_gen_logic_op[] = {
 174    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 175    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 176    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 177    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 178    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 179    [VK_LOGIC_OP_NO_OP]                          = LOGICOP_NOOP,
 180    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 181    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 182    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 183    [VK_LOGIC_OP_EQUIVALENT]                     = LOGICOP_EQUIV,
 184    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 185    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 186    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 187    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 188    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 189    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 190 };
 191
 192 static const uint32_t vk_to_gen_blend[] = {
 193    [VK_BLEND_FACTOR_ZERO]                       = BLENDFACTOR_ZERO,
 194    [VK_BLEND_FACTOR_ONE]                        = BLENDFACTOR_ONE,
 195    [VK_BLEND_FACTOR_SRC_COLOR]                  = BLENDFACTOR_SRC_COLOR,
 196    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]        = BLENDFACTOR_INV_SRC_COLOR,
 197    [VK_BLEND_FACTOR_DST_COLOR]                  = BLENDFACTOR_DST_COLOR,
 198    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]        = BLENDFACTOR_INV_DST_COLOR,
 199    [VK_BLEND_FACTOR_SRC_ALPHA]                  = BLENDFACTOR_SRC_ALPHA,
 200    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]        = BLENDFACTOR_INV_SRC_ALPHA,
 201    [VK_BLEND_FACTOR_DST_ALPHA]                  = BLENDFACTOR_DST_ALPHA,
 202    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]        = BLENDFACTOR_INV_DST_ALPHA,
 203    [VK_BLEND_FACTOR_CONSTANT_COLOR]             = BLENDFACTOR_CONST_COLOR,
 204    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]   = BLENDFACTOR_INV_CONST_COLOR,
 205    [VK_BLEND_FACTOR_CONSTANT_ALPHA]             = BLENDFACTOR_CONST_ALPHA,
 206    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]   = BLENDFACTOR_INV_CONST_ALPHA,
 207    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]         = BLENDFACTOR_SRC_ALPHA_SATURATE,
 208    [VK_BLEND_FACTOR_SRC1_COLOR]                 = BLENDFACTOR_SRC1_COLOR,
 209    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]       = BLENDFACTOR_INV_SRC1_COLOR,
 210    [VK_BLEND_FACTOR_SRC1_ALPHA]                 = BLENDFACTOR_SRC1_ALPHA,
 211    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]       = BLENDFACTOR_INV_SRC1_ALPHA,
 212 };
 213
 214 static void
 215 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 216                    const VkPipelineDepthStencilStateCreateInfo *info)
 217 {
 218    if (info == NULL) {
 219       /* We're going to OR this together with the dynamic state.  We need
 220        * to make sure it's initialized to something useful.
 221        */
 222       memset(pipeline->gen7.depth_stencil_state, 0,
 223              sizeof(pipeline->gen7.depth_stencil_state));
 224       return;
 225    }
 226
 227    struct GEN7_DEPTH_STENCIL_STATE state = {
 228       .DepthTestEnable = info->depthTestEnable,
 229       .DepthBufferWriteEnable = info->depthWriteEnable,
 230       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 231       .DoubleSidedStencilEnable = true,
 232
 233       .StencilTestEnable = info->stencilTestEnable,
 234       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 235       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 236       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 237       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 238
 239       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 240       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 241       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 242       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 243    };
 244
 245    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 246 }
 247
 248 static void
 249 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 250                    const VkPipelineColorBlendStateCreateInfo *info)
 251 {
 252    struct anv_device *device = pipeline->device;
 253
 254    uint32_t num_dwords = GEN7_BLEND_STATE_length;
 255    pipeline->blend_state =
 256       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 257
 258    if (info->pAttachments == NULL) {
 259       struct GEN7_BLEND_STATE blend_state = {
 260          .ColorBufferBlendEnable = false,
 261          .WriteDisableAlpha = false,
 262          .WriteDisableRed = false,
 263          .WriteDisableGreen = false,
 264          .WriteDisableBlue = false,
 265       };
 266
 267       GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 268    } else {
 269       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 270        * can't implement this.
 271        */
 272       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 273
 274       struct GEN7_BLEND_STATE blend_state = {
 275          .ColorBufferBlendEnable = a->blendEnable,
 276          .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 277          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 278
 279          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 280          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 281
 282          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 283          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 284          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 285          .AlphaToCoverageEnable = info->alphaToCoverageEnable,
 286
 287 #     if 0
 288          bool                                         AlphaToOneEnable;
 289          bool                                         AlphaToCoverageDitherEnable;
 290 #     endif
 291
 292          .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
 293          .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
 294          .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
 295          .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
 296
 297          .LogicOpEnable = info->logicOpEnable,
 298          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 299
 300 #     if 0
 301          bool                                         AlphaTestEnable;
 302          uint32_t                                     AlphaTestFunction;
 303          bool                                         ColorDitherEnable;
 304          uint32_t                                     XDitherOffset;
 305          uint32_t                                     YDitherOffset;
 306          uint32_t                                     ColorClampRange;
 307          bool                                         PreBlendColorClampEnable;
 308          bool                                         PostBlendColorClampEnable;
 309 #     endif
 310       };
 311
 312       GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 313     }
 314
 315    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 316                   .BlendStatePointer = pipeline->blend_state.offset);
 317 }
 318
 319 static inline uint32_t
 320 scratch_space(const struct brw_stage_prog_data *prog_data)
 321 {
 322    return ffs(prog_data->total_scratch / 1024);
 323 }
 324
 325 GENX_FUNC(GEN7, GEN75) VkResult
 326 genX(graphics_pipeline_create)(
 327     VkDevice                                    _device,
 328     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 329     const struct anv_graphics_pipeline_create_info *extra,
 330     VkPipeline*                                 pPipeline)
 331 {
 332    ANV_FROM_HANDLE(anv_device, device, _device);
 333    struct anv_pipeline *pipeline;
 334    VkResult result;
 335
 336    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 337
 338    pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
 339                                VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 340    if (pipeline == NULL)
 341       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 342
 343    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
 344    if (result != VK_SUCCESS) {
 345       anv_device_free(device, pipeline);
 346       return result;
 347    }
 348
 349    assert(pCreateInfo->pVertexInputState);
 350    gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 351
 352    assert(pCreateInfo->pRasterState);
 353    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
 354
 355    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 356
 357    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
 358
 359    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 360                    .StatisticsEnable = true);
 361    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 362    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 363    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 364    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 365
 366    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 367     *
 368     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 369     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 370     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 371     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 372     *    needs to be sent before any combination of VS associated 3DSTATE."
 373     */
 374    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 375                   .DepthStallEnable = true,
 376                   .PostSyncOperation = WriteImmediateData,
 377                   .Address = { &device->workaround_bo, 0 });
 378
 379    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 380                   .ConstantBufferOffset = 0,
 381                   .ConstantBufferSize = 4);
 382    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 383                   .ConstantBufferOffset = 4,
 384                   .ConstantBufferSize = 4);
 385    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 386                   .ConstantBufferOffset = 8,
 387                   .ConstantBufferSize = 4);
 388
 389    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 390
 391    const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
 392
 393    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 394       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 395       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 396       .ClipEnable                               = true,
 397       .APIMode                                  = APIMODE_OGL,
 398       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 399       .ClipMode                                 = CLIPMODE_NORMAL,
 400       .TriangleStripListProvokingVertexSelect   = 0,
 401       .LineStripListProvokingVertexSelect       = 0,
 402       .TriangleFanProvokingVertexSelect         = 0,
 403       .MinimumPointWidth                        = 0.125,
 404       .MaximumPointWidth                        = 255.875);
 405
 406    uint32_t samples = 1;
 407    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 408
 409    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 410       .PixelLocation                            = PIXLOC_CENTER,
 411       .NumberofMultisamples                     = log2_samples);
 412
 413    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 414       .SampleMask                               = 0xff);
 415
 416    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 417       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 418       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 419       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 420
 421    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 422       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 423       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 424       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 425
 426    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 427       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 428       .HSURBEntryAllocationSize                 = 0,
 429       .HSNumberofURBEntries                     = 0);
 430
 431    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 432       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 433       .DSURBEntryAllocationSize                 = 0,
 434       .DSNumberofURBEntries                     = 0);
 435
 436    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 437    /* The last geometry producing stage will set urb_offset and urb_length,
 438     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 439    uint32_t urb_offset = 1;
 440    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 441
 442 #if 0
 443    /* From gen7_vs_state.c */
 444
 445    /**
 446     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 447     * Geometry > Geometry Shader > State:
 448     *
 449     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 450     *     whole fixed function pipeline when the GS enable changes value in
 451     *     the 3DSTATE_GS."
 452     *
 453     * The hardware architects have clarified that in this context "flush the
 454     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 455     * Stall" bit set.
 456     */
 457    if (!brw->is_haswell && !brw->is_baytrail)
 458       gen7_emit_vs_workaround_flush(brw);
 459 #endif
 460
 461    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 462       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 463    else
 464       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 465          .KernelStartPointer                    = pipeline->vs_vec4,
 466          .ScratchSpaceBaseOffset                = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
 467          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 468
 469          .DispatchGRFStartRegisterforURBData    =
 470             vue_prog_data->base.dispatch_grf_start_reg,
 471          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 472          .VertexURBEntryReadOffset              = 0,
 473
 474          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 475          .StatisticsEnable                      = true,
 476          .VSFunctionEnable                      = true);
 477
 478    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 479
 480    if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
 481       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 482    } else {
 483       urb_offset = 1;
 484       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 485
 486       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 487          .KernelStartPointer                    = pipeline->gs_vec4,
 488          .ScratchSpaceBasePointer               = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
 489          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 490
 491          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 492          .OutputTopology                        = gs_prog_data->output_topology,
 493          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 494          .DispatchGRFStartRegisterforURBData    =
 495             gs_prog_data->base.base.dispatch_grf_start_reg,
 496
 497          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 498          /* This in the next dword on HSW. */
 499          .ControlDataFormat                     = gs_prog_data->control_data_format,
 500          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 501          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 502          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 503          .GSStatisticsEnable                    = true,
 504          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 505 #     if (ANV_IS_HASWELL)
 506          .ReorderMode                           = REORDER_TRAILING,
 507 #     else
 508          .ReorderEnable                         = true,
 509 #     endif
 510          .GSEnable                              = true);
 511    }
 512
 513    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 514    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 515        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 516       anv_finishme("two-sided color needs sbe swizzling setup");
 517    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 518       anv_finishme("primitive_id needs sbe swizzling setup");
 519
 520    /* FIXME: generated header doesn't emit attr swizzle fields */
 521    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 522       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 523       .VertexURBEntryReadLength                 = urb_length,
 524       .VertexURBEntryReadOffset                 = urb_offset,
 525       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 526
 527    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 528       .KernelStartPointer0                      = pipeline->ps_ksp0,
 529       .ScratchSpaceBasePointer                  = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
 530       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 531
 532       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 533       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 534       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 535       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 536
 537       .RenderTargetFastClearEnable              = false,
 538       .DualSourceBlendEnable                    = false,
 539       .RenderTargetResolveEnable                = false,
 540
 541       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 542          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 543
 544       ._32PixelDispatchEnable                   = false,
 545       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 546       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 547
 548       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 549       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 550       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 551
 552 #if 0
 553    /* Haswell requires the sample mask to be set in this packet as well as
 554     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 555    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 556 #endif
 557
 558       .KernelStartPointer1                      = 0,
 559       .KernelStartPointer2                      = pipeline->ps_ksp2);
 560
 561    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 562    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 563       .StatisticsEnable                         = true,
 564       .ThreadDispatchEnable                     = true,
 565       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 566       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 567       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 568       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 569       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 570       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 571
 572    *pPipeline = anv_pipeline_to_handle(pipeline);
 573
 574    return VK_SUCCESS;
 575 }
 576
 577 GENX_FUNC(GEN7, GEN75) VkResult
 578 genX(compute_pipeline_create)(
 579     VkDevice                                    _device,
 580     const VkComputePipelineCreateInfo*          pCreateInfo,
 581     VkPipeline*                                 pPipeline)
 582 {
 583    anv_finishme("primitive_id needs sbe swizzling setup");
 584    abort();
 585 }