src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 static void
  33 gen7_emit_vertex_input(struct anv_pipeline *pipeline,
  34                        const VkPipelineVertexInputStateCreateInfo *info)
  35 {
  36    const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
  37       pipeline->vs_prog_data.uses_instanceid;
  38    const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0);
  39    const uint32_t num_dwords = 1 + element_count * 2;
  40    uint32_t *p;
  41
  42    if (info->attributeCount > 0) {
  43       p = anv_batch_emitn(&pipeline->batch, num_dwords,
  44                           GEN7_3DSTATE_VERTEX_ELEMENTS);
  45    }
  46
  47    for (uint32_t i = 0; i < info->attributeCount; i++) {
  48       const VkVertexInputAttributeDescription *desc =
  49          &info->pVertexAttributeDescriptions[i];
  50       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  51
  52       struct GEN7_VERTEX_ELEMENT_STATE element = {
  53          .VertexBufferIndex = desc->binding,
  54          .Valid = true,
  55          .SourceElementFormat = format->surface_format,
  56          .EdgeFlagEnable = false,
  57          .SourceElementOffset = desc->offsetInBytes,
  58          .Component0Control = VFCOMP_STORE_SRC,
  59          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  60          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  61          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  62       };
  63       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  64    }
  65
  66    if (sgvs) {
  67       struct GEN7_VERTEX_ELEMENT_STATE element = {
  68          .Valid = true,
  69          /* FIXME: Do we need to provide the base vertex as component 0 here
  70           * to support the correct base vertex ID? */
  71          .Component0Control = VFCOMP_STORE_0,
  72          .Component1Control = VFCOMP_STORE_0,
  73          .Component2Control = VFCOMP_STORE_VID,
  74          .Component3Control = VFCOMP_STORE_IID
  75       };
  76       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element);
  77    }
  78 }
  79
  80 static const uint32_t vk_to_gen_cullmode[] = {
  81    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
  82    [VK_CULL_MODE_FRONT]                         = CULLMODE_FRONT,
  83    [VK_CULL_MODE_BACK]                          = CULLMODE_BACK,
  84    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
  85 };
  86
  87 static const uint32_t vk_to_gen_fillmode[] = {
  88    [VK_FILL_MODE_POINTS]                        = RASTER_POINT,
  89    [VK_FILL_MODE_WIREFRAME]                     = RASTER_WIREFRAME,
  90    [VK_FILL_MODE_SOLID]                         = RASTER_SOLID
  91 };
  92
  93 static const uint32_t vk_to_gen_front_face[] = {
  94    [VK_FRONT_FACE_CCW]                          = CounterClockwise,
  95    [VK_FRONT_FACE_CW]                           = Clockwise
  96 };
  97
  98 static void
  99 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 100                    const VkPipelineRasterStateCreateInfo *info,
 101                    const struct anv_graphics_pipeline_create_info *extra)
 102 {
 103    struct GEN7_3DSTATE_SF sf = {
 104       GEN7_3DSTATE_SF_header,
 105
 106       /* FIXME: Get this from pass info */
 107       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 108
 109       /* LegacyGlobalDepthBiasEnable */
 110
 111       .StatisticsEnable                         = true,
 112       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->fillMode],
 113       .BackFaceFillMode                         = vk_to_gen_fillmode[info->fillMode],
 114       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 115       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 116       /* bool                                         AntiAliasingEnable; */
 117
 118       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 119
 120       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 121       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 122
 123       /* uint32_t                                     MultisampleRasterizationMode; */
 124       /* bool                                         LastPixelEnable; */
 125
 126       .TriangleStripListProvokingVertexSelect   = 0,
 127       .LineStripListProvokingVertexSelect       = 0,
 128       .TriangleFanProvokingVertexSelect         = 0,
 129
 130       /* uint32_t                                     AALineDistanceMode; */
 131       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 132       .UsePointWidthState                       = !pipeline->writes_point_size,
 133       .PointWidth                               = 1.0,
 134    };
 135
 136    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 137 }
 138
 139 static const uint32_t vk_to_gen_compare_op[] = {
 140    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 141    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 142    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 143    [VK_COMPARE_OP_LESS_EQUAL]                   = PREFILTEROPLEQUAL,
 144    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 145    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 146    [VK_COMPARE_OP_GREATER_EQUAL]                = PREFILTEROPGEQUAL,
 147    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 148 };
 149
 150 static const uint32_t vk_to_gen_stencil_op[] = {
 151    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 152    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 153    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 154    [VK_STENCIL_OP_INC_CLAMP]                    = STENCILOP_INCRSAT,
 155    [VK_STENCIL_OP_DEC_CLAMP]                    = STENCILOP_DECRSAT,
 156    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 157    [VK_STENCIL_OP_INC_WRAP]                     = STENCILOP_INCR,
 158    [VK_STENCIL_OP_DEC_WRAP]                     = STENCILOP_DECR,
 159 };
 160
 161 static const uint32_t vk_to_gen_blend_op[] = {
 162    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 163    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 164    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 165    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 166    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 167 };
 168
 169 static const uint32_t vk_to_gen_logic_op[] = {
 170    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 171    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 172    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 173    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 174    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 175    [VK_LOGIC_OP_NOOP]                           = LOGICOP_NOOP,
 176    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 177    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 178    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 179    [VK_LOGIC_OP_EQUIV]                          = LOGICOP_EQUIV,
 180    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 181    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 182    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 183    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 184    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 185    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 186 };
 187
 188 static const uint32_t vk_to_gen_blend[] = {
 189    [VK_BLEND_ZERO]                              = BLENDFACTOR_ZERO,
 190    [VK_BLEND_ONE]                               = BLENDFACTOR_ONE,
 191    [VK_BLEND_SRC_COLOR]                         = BLENDFACTOR_SRC_COLOR,
 192    [VK_BLEND_ONE_MINUS_SRC_COLOR]               = BLENDFACTOR_INV_SRC_COLOR,
 193    [VK_BLEND_DEST_COLOR]                        = BLENDFACTOR_DST_COLOR,
 194    [VK_BLEND_ONE_MINUS_DEST_COLOR]              = BLENDFACTOR_INV_DST_COLOR,
 195    [VK_BLEND_SRC_ALPHA]                         = BLENDFACTOR_SRC_ALPHA,
 196    [VK_BLEND_ONE_MINUS_SRC_ALPHA]               = BLENDFACTOR_INV_SRC_ALPHA,
 197    [VK_BLEND_DEST_ALPHA]                        = BLENDFACTOR_DST_ALPHA,
 198    [VK_BLEND_ONE_MINUS_DEST_ALPHA]              = BLENDFACTOR_INV_DST_ALPHA,
 199    [VK_BLEND_CONSTANT_COLOR]                    = BLENDFACTOR_CONST_COLOR,
 200    [VK_BLEND_ONE_MINUS_CONSTANT_COLOR]          = BLENDFACTOR_INV_CONST_COLOR,
 201    [VK_BLEND_CONSTANT_ALPHA]                    = BLENDFACTOR_CONST_ALPHA,
 202    [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA]          = BLENDFACTOR_INV_CONST_ALPHA,
 203    [VK_BLEND_SRC_ALPHA_SATURATE]                = BLENDFACTOR_SRC_ALPHA_SATURATE,
 204    [VK_BLEND_SRC1_COLOR]                        = BLENDFACTOR_SRC1_COLOR,
 205    [VK_BLEND_ONE_MINUS_SRC1_COLOR]              = BLENDFACTOR_INV_SRC1_COLOR,
 206    [VK_BLEND_SRC1_ALPHA]                        = BLENDFACTOR_SRC1_ALPHA,
 207    [VK_BLEND_ONE_MINUS_SRC1_ALPHA]              = BLENDFACTOR_INV_SRC1_ALPHA,
 208 };
 209
 210 static void
 211 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 212                    const VkPipelineDepthStencilStateCreateInfo *info)
 213 {
 214    if (info == NULL) {
 215       /* We're going to OR this together with the dynamic state.  We need
 216        * to make sure it's initialized to something useful.
 217        */
 218       memset(pipeline->gen7.depth_stencil_state, 0,
 219              sizeof(pipeline->gen7.depth_stencil_state));
 220       return;
 221    }
 222
 223    bool has_stencil = false;  /* enable if subpass has stencil? */
 224
 225    struct GEN7_DEPTH_STENCIL_STATE state = {
 226       /* Is this what we need to do? */
 227       .StencilBufferWriteEnable = has_stencil,
 228
 229       .StencilTestEnable = info->stencilTestEnable,
 230       .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
 231       .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
 232       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
 233       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
 234
 235       .DoubleSidedStencilEnable = true,
 236
 237       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
 238       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
 239       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
 240       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
 241
 242       .DepthTestEnable = info->depthTestEnable,
 243       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 244       .DepthBufferWriteEnable = info->depthWriteEnable,
 245    };
 246
 247    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 248 }
 249
 250 static void
 251 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 252                    const VkPipelineColorBlendStateCreateInfo *info)
 253 {
 254    struct anv_device *device = pipeline->device;
 255
 256    /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 257     * can't implement this.
 258     */
 259    const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 260
 261    uint32_t num_dwords = GEN7_BLEND_STATE_length;
 262    pipeline->blend_state =
 263       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 264
 265    struct GEN7_BLEND_STATE blend_state = {
 266       .ColorBufferBlendEnable = a->blendEnable,
 267       .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 268       .AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
 269
 270       .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
 271       .DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
 272
 273       .ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
 274       .SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
 275       .DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
 276       .AlphaToCoverageEnable = info->alphaToCoverageEnable,
 277
 278 #if 0
 279    bool                                         AlphaToOneEnable;
 280    bool                                         AlphaToCoverageDitherEnable;
 281 #endif
 282
 283       .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
 284       .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
 285       .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
 286       .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
 287
 288       .LogicOpEnable = info->logicOpEnable,
 289       .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 290
 291 #if 0
 292    bool                                         AlphaTestEnable;
 293    uint32_t                                     AlphaTestFunction;
 294    bool                                         ColorDitherEnable;
 295    uint32_t                                     XDitherOffset;
 296    uint32_t                                     YDitherOffset;
 297    uint32_t                                     ColorClampRange;
 298    bool                                         PreBlendColorClampEnable;
 299    bool                                         PostBlendColorClampEnable;
 300 #endif
 301    };
 302
 303    GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 304
 305    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 306                   .BlendStatePointer = pipeline->blend_state.offset);
 307 }
 308
 309 static const uint32_t vk_to_gen_primitive_type[] = {
 310    [VK_PRIMITIVE_TOPOLOGY_POINT_LIST]           = _3DPRIM_POINTLIST,
 311    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST]            = _3DPRIM_LINELIST,
 312    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP]           = _3DPRIM_LINESTRIP,
 313    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST]        = _3DPRIM_TRILIST,
 314    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP]       = _3DPRIM_TRISTRIP,
 315    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN]         = _3DPRIM_TRIFAN,
 316    [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ]        = _3DPRIM_LINELIST_ADJ,
 317    [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ]       = _3DPRIM_LINESTRIP_ADJ,
 318    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ]    = _3DPRIM_TRILIST_ADJ,
 319    [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ]   = _3DPRIM_TRISTRIP_ADJ,
 320    [VK_PRIMITIVE_TOPOLOGY_PATCH]                = _3DPRIM_PATCHLIST_1
 321 };
 322
 323 static inline uint32_t
 324 scratch_space(const struct brw_stage_prog_data *prog_data)
 325 {
 326    return ffs(prog_data->total_scratch / 1024);
 327 }
 328
 329 VkResult
 330 gen7_graphics_pipeline_create(
 331     VkDevice                                    _device,
 332     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 333     const struct anv_graphics_pipeline_create_info *extra,
 334     VkPipeline*                                 pPipeline)
 335 {
 336    ANV_FROM_HANDLE(anv_device, device, _device);
 337    struct anv_pipeline *pipeline;
 338    VkResult result;
 339
 340    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 341
 342    pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
 343                                VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 344    if (pipeline == NULL)
 345       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 346
 347    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
 348    if (result != VK_SUCCESS) {
 349       anv_device_free(device, pipeline);
 350       return result;
 351    }
 352
 353    assert(pCreateInfo->pVertexInputState);
 354    gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 355
 356    assert(pCreateInfo->pRasterState);
 357    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
 358
 359    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 360
 361    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
 362
 363    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 364                    .StatisticsEnable = true);
 365    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 366    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 367    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 368    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 369
 370    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 371                   .ConstantBufferOffset = 0,
 372                   .ConstantBufferSize = 4);
 373    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 374                   .ConstantBufferOffset = 4,
 375                   .ConstantBufferSize = 4);
 376    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 377                   .ConstantBufferOffset = 8,
 378                   .ConstantBufferSize = 4);
 379
 380    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 381
 382    const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
 383
 384    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 385       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 386       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 387       .ClipEnable                               = true,
 388       .APIMode                                  = APIMODE_OGL,
 389       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 390       .ClipMode                                 = CLIPMODE_NORMAL,
 391       .TriangleStripListProvokingVertexSelect   = 0,
 392       .LineStripListProvokingVertexSelect       = 0,
 393       .TriangleFanProvokingVertexSelect         = 0,
 394       .MinimumPointWidth                        = 0.125,
 395       .MaximumPointWidth                        = 255.875);
 396
 397    uint32_t samples = 1;
 398    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 399
 400    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 401       .PixelLocation                            = PIXLOC_CENTER,
 402       .NumberofMultisamples                     = log2_samples);
 403
 404    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 405       .SampleMask                               = 0xff);
 406
 407    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 408       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 409       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 410       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 411
 412    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 413       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 414       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 415       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 416
 417    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 418       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 419       .HSURBEntryAllocationSize                 = 0,
 420       .HSNumberofURBEntries                     = 0);
 421
 422    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 423       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 424       .DSURBEntryAllocationSize                 = 0,
 425       .DSNumberofURBEntries                     = 0);
 426
 427    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 428    /* The last geometry producing stage will set urb_offset and urb_length,
 429     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 430    uint32_t urb_offset = 1;
 431    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 432
 433 #if 0
 434    /* From gen7_vs_state.c */
 435
 436    /**
 437     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 438     * Geometry > Geometry Shader > State:
 439     *
 440     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 441     *     whole fixed function pipeline when the GS enable changes value in
 442     *     the 3DSTATE_GS."
 443     *
 444     * The hardware architects have clarified that in this context "flush the
 445     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 446     * Stall" bit set.
 447     */
 448    if (!brw->is_haswell && !brw->is_baytrail)
 449       gen7_emit_vs_workaround_flush(brw);
 450 #endif
 451
 452    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 453       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false);
 454    else
 455       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS,
 456          .KernelStartPointer                    = pipeline->vs_vec4,
 457          .ScratchSpaceBaseOffset                = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
 458          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 459
 460          .DispatchGRFStartRegisterforURBData    =
 461             vue_prog_data->base.dispatch_grf_start_reg,
 462          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 463          .VertexURBEntryReadOffset              = 0,
 464
 465          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 466          .StatisticsEnable                      = true,
 467          .VSFunctionEnable                      = true);
 468
 469    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 470
 471    if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
 472       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false);
 473    } else {
 474       urb_offset = 1;
 475       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 476
 477       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS,
 478          .KernelStartPointer                    = pipeline->gs_vec4,
 479          .ScratchSpaceBasePointer               = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
 480          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 481
 482          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 483          .OutputTopology                        = gs_prog_data->output_topology,
 484          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 485          .DispatchGRFStartRegisterforURBData    =
 486             gs_prog_data->base.base.dispatch_grf_start_reg,
 487
 488          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 489          /* This in the next dword on HSW. */
 490          .ControlDataFormat                     = gs_prog_data->control_data_format,
 491          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 492          .InstanceControl                       = gs_prog_data->invocations - 1,
 493          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 494          .GSStatisticsEnable                    = true,
 495          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 496          .ReorderEnable                         = true,
 497          .GSEnable                              = true);
 498    }
 499
 500    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 501    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 502        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 503       anv_finishme("two-sided color needs sbe swizzling setup");
 504    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 505       anv_finishme("primitive_id needs sbe swizzling setup");
 506
 507    /* FIXME: generated header doesn't emit attr swizzle fields */
 508    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 509       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 510       .VertexURBEntryReadLength                 = urb_length,
 511       .VertexURBEntryReadOffset                 = urb_offset,
 512       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 513
 514    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS,
 515       .KernelStartPointer0                      = pipeline->ps_ksp0,
 516       .ScratchSpaceBasePointer                  = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
 517       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 518
 519       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 520       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 521       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 522       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 523
 524       .RenderTargetFastClearEnable              = false,
 525       .DualSourceBlendEnable                    = false,
 526       .RenderTargetResolveEnable                = false,
 527
 528       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 529          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 530
 531       ._32PixelDispatchEnable                   = false,
 532       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 533       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 534
 535       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 536       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 537       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 538
 539 #if 0
 540    /* Haswell requires the sample mask to be set in this packet as well as
 541     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 542    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 543 #endif
 544
 545       .KernelStartPointer1                      = 0,
 546       .KernelStartPointer2                      = pipeline->ps_ksp2);
 547
 548    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 549    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 550       .StatisticsEnable                         = true,
 551       .ThreadDispatchEnable                     = true,
 552       .LineEndCapAntialiasingRegionWidth        = _05pixels,
 553       .LineAntialiasingRegionWidth              = _10pixels,
 554       .EarlyDepthStencilControl                 = NORMAL,
 555       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 556       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 557       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 558
 559    *pPipeline = anv_pipeline_to_handle(pipeline);
 560
 561    return VK_SUCCESS;
 562 }
 563
 564 VkResult gen7_compute_pipeline_create(
 565     VkDevice                                    _device,
 566     const VkComputePipelineCreateInfo*          pCreateInfo,
 567     VkPipeline*                                 pPipeline)
 568 {
 569    anv_finishme("primitive_id needs sbe swizzling setup");
 570
 571    return vk_error(VK_ERROR_UNAVAILABLE);
 572 }