src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 gen7_emit_rs_state(struct anv_pipeline *pipeline,
  39                    const VkPipelineRasterizationStateCreateInfo *info,
  40                    const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    struct GEN7_3DSTATE_SF sf = {
  43       GEN7_3DSTATE_SF_header,
  44
  45       /* FIXME: Get this from pass info */
  46       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
  47
  48       /* LegacyGlobalDepthBiasEnable */
  49
  50       .StatisticsEnable                         = true,
  51       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
  52       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
  53       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
  54       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
  55       /* bool                                         AntiAliasingEnable; */
  56
  57       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
  58
  59       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
  60       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
  61
  62       /* uint32_t                                     MultisampleRasterizationMode; */
  63       /* bool                                         LastPixelEnable; */
  64
  65       .TriangleStripListProvokingVertexSelect   = 0,
  66       .LineStripListProvokingVertexSelect       = 0,
  67       .TriangleFanProvokingVertexSelect         = 0,
  68
  69       /* uint32_t                                     AALineDistanceMode; */
  70       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
  71       .UsePointWidthState                       = !pipeline->writes_point_size,
  72       .PointWidth                               = 1.0,
  73    };
  74
  75    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
  76 }
  77
  78 static void
  79 gen7_emit_ds_state(struct anv_pipeline *pipeline,
  80                    const VkPipelineDepthStencilStateCreateInfo *info)
  81 {
  82    if (info == NULL) {
  83       /* We're going to OR this together with the dynamic state.  We need
  84        * to make sure it's initialized to something useful.
  85        */
  86       memset(pipeline->gen7.depth_stencil_state, 0,
  87              sizeof(pipeline->gen7.depth_stencil_state));
  88       return;
  89    }
  90
  91    struct GEN7_DEPTH_STENCIL_STATE state = {
  92       .DepthTestEnable = info->depthTestEnable,
  93       .DepthBufferWriteEnable = info->depthWriteEnable,
  94       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
  95       .DoubleSidedStencilEnable = true,
  96
  97       .StencilTestEnable = info->stencilTestEnable,
  98       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
  99       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 100       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 101       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 102
 103       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 104       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 105       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 106       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 107    };
 108
 109    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 110 }
 111
 112 static void
 113 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 114                    const VkPipelineColorBlendStateCreateInfo *info,
 115                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 116 {
 117    struct anv_device *device = pipeline->device;
 118
 119    if (info->pAttachments == NULL) {
 120       pipeline->blend_state =
 121          anv_state_pool_emit(&device->dynamic_state_pool,
 122             GEN7_BLEND_STATE, 64,
 123             .ColorBufferBlendEnable = false,
 124             .WriteDisableAlpha = false,
 125             .WriteDisableRed = false,
 126             .WriteDisableGreen = false,
 127             .WriteDisableBlue = false);
 128    } else {
 129       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 130        * can't implement this.
 131        */
 132       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 133       pipeline->blend_state =
 134          anv_state_pool_emit(&device->dynamic_state_pool,
 135             GEN7_BLEND_STATE, 64,
 136
 137             .ColorBufferBlendEnable = a->blendEnable,
 138             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 139             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 140
 141             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 142             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 143
 144             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 145             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 146             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 147             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 148
 149 #     if 0
 150             bool                                AlphaToOneEnable;
 151             bool                                AlphaToCoverageDitherEnable;
 152 #     endif
 153
 154             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 155             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 156             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 157             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 158
 159             .LogicOpEnable = info->logicOpEnable,
 160             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 161
 162 #     if 0
 163             bool                                AlphaTestEnable;
 164             uint32_t                            AlphaTestFunction;
 165             bool                                ColorDitherEnable;
 166             uint32_t                            XDitherOffset;
 167             uint32_t                            YDitherOffset;
 168             uint32_t                            ColorClampRange;
 169             bool                                PreBlendColorClampEnable;
 170             bool                                PostBlendColorClampEnable;
 171 #     endif
 172             );
 173     }
 174
 175    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 176                   .BlendStatePointer = pipeline->blend_state.offset);
 177 }
 178
 179 GENX_FUNC(GEN7, GEN75) VkResult
 180 genX(graphics_pipeline_create)(
 181     VkDevice                                    _device,
 182     struct anv_pipeline_cache *                 cache,
 183     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 184     const struct anv_graphics_pipeline_create_info *extra,
 185     const VkAllocationCallbacks*                pAllocator,
 186     VkPipeline*                                 pPipeline)
 187 {
 188    ANV_FROM_HANDLE(anv_device, device, _device);
 189    struct anv_pipeline *pipeline;
 190    VkResult result;
 191
 192    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 193
 194    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 195                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 196    if (pipeline == NULL)
 197       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 198
 199    result = anv_pipeline_init(pipeline, device, cache,
 200                               pCreateInfo, extra, pAllocator);
 201    if (result != VK_SUCCESS) {
 202       anv_free2(&device->alloc, pAllocator, pipeline);
 203       return result;
 204    }
 205
 206    assert(pCreateInfo->pVertexInputState);
 207    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 208
 209    assert(pCreateInfo->pRasterizationState);
 210    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 211
 212    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 213
 214    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 215                                 pCreateInfo->pMultisampleState);
 216
 217    emit_urb_setup(pipeline);
 218
 219    const VkPipelineRasterizationStateCreateInfo *rs_info =
 220       pCreateInfo->pRasterizationState;
 221
 222    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 223       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 224       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 225       .ClipEnable                               = true,
 226       .APIMode                                  = APIMODE_OGL,
 227       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 228       .ClipMode                                 = CLIPMODE_NORMAL,
 229       .TriangleStripListProvokingVertexSelect   = 0,
 230       .LineStripListProvokingVertexSelect       = 0,
 231       .TriangleFanProvokingVertexSelect         = 0,
 232       .MinimumPointWidth                        = 0.125,
 233       .MaximumPointWidth                        = 255.875,
 234       .MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
 235
 236    if (pCreateInfo->pMultisampleState &&
 237        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 238       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 239
 240    uint32_t samples = 1;
 241    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 242
 243    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 244       .PixelLocation                            = PIXLOC_CENTER,
 245       .NumberofMultisamples                     = log2_samples);
 246
 247    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 248       .SampleMask                               = 0xff);
 249
 250    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 251    /* The last geometry producing stage will set urb_offset and urb_length,
 252     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 253    uint32_t urb_offset = 1;
 254    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 255
 256 #if 0
 257    /* From gen7_vs_state.c */
 258
 259    /**
 260     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 261     * Geometry > Geometry Shader > State:
 262     *
 263     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 264     *     whole fixed function pipeline when the GS enable changes value in
 265     *     the 3DSTATE_GS."
 266     *
 267     * The hardware architects have clarified that in this context "flush the
 268     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 269     * Stall" bit set.
 270     */
 271    if (!brw->is_haswell && !brw->is_baytrail)
 272       gen7_emit_vs_workaround_flush(brw);
 273 #endif
 274
 275    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 276       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 277    else
 278       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 279          .KernelStartPointer                    = pipeline->vs_vec4,
 280          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 281          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 282
 283          .DispatchGRFStartRegisterforURBData    =
 284             vue_prog_data->base.dispatch_grf_start_reg,
 285          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 286          .VertexURBEntryReadOffset              = 0,
 287
 288          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 289          .StatisticsEnable                      = true,
 290          .VSFunctionEnable                      = true);
 291
 292    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 293
 294    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 295       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 296    } else {
 297       urb_offset = 1;
 298       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 299
 300       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 301          .KernelStartPointer                    = pipeline->gs_kernel,
 302          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 303          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 304
 305          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 306          .OutputTopology                        = gs_prog_data->output_topology,
 307          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 308          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 309          .DispatchGRFStartRegisterforURBData    =
 310             gs_prog_data->base.base.dispatch_grf_start_reg,
 311
 312          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 313          /* This in the next dword on HSW. */
 314          .ControlDataFormat                     = gs_prog_data->control_data_format,
 315          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 316          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 317          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 318          .GSStatisticsEnable                    = true,
 319          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 320 #     if (ANV_IS_HASWELL)
 321          .ReorderMode                           = REORDER_TRAILING,
 322 #     else
 323          .ReorderEnable                         = true,
 324 #     endif
 325          .GSEnable                              = true);
 326    }
 327
 328    if (pipeline->ps_ksp0 == NO_KERNEL) {
 329       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
 330       anv_finishme("gen7 alternative to "
 331                    "3DSTATE_PS_EXTRA.PixelShaderValid = false");
 332    } else {
 333       const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 334       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 335           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 336          anv_finishme("two-sided color needs sbe swizzling setup");
 337       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 338          anv_finishme("primitive_id needs sbe swizzling setup");
 339
 340       /* FIXME: generated header doesn't emit attr swizzle fields */
 341       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 342                      .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 343                      .VertexURBEntryReadLength                 = urb_length,
 344                      .VertexURBEntryReadOffset                 = urb_offset,
 345                      .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 346
 347       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 348                      .KernelStartPointer0                      = pipeline->ps_ksp0,
 349                      .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 350                      .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 351
 352                      .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 353                      .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 354                      .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 355                      .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 356
 357                      .RenderTargetFastClearEnable              = false,
 358                      .DualSourceBlendEnable                    = false,
 359                      .RenderTargetResolveEnable                = false,
 360
 361                      .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 362                      POSOFFSET_SAMPLE : POSOFFSET_NONE,
 363
 364                      ._32PixelDispatchEnable                   = false,
 365                      ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 366                      ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 367
 368                      .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 369                      .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 370                      .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 371
 372 #if 0
 373                      /* Haswell requires the sample mask to be set in this packet as well as
 374                       * in 3DSTATE_SAMPLE_MASK; the values should match. */
 375                      /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 376 #endif
 377
 378                      .KernelStartPointer1                      = 0,
 379                      .KernelStartPointer2                      = pipeline->ps_ksp2);
 380
 381       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 382       anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 383                      .StatisticsEnable                         = true,
 384                      .ThreadDispatchEnable                     = true,
 385                      .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 386                      .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 387                      .EarlyDepthStencilControl                 = EDSC_NORMAL,
 388                      .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 389                      .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 390                      .PixelShaderUsesSourceDepth               = wm_prog_data->uses_src_depth,
 391                      .PixelShaderUsesSourceW                   = wm_prog_data->uses_src_w,
 392                      .PixelShaderUsesInputCoverageMask         = wm_prog_data->uses_sample_mask,
 393                      .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 394    }
 395
 396    *pPipeline = anv_pipeline_to_handle(pipeline);
 397
 398    return VK_SUCCESS;
 399 }