src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_vertex_input(struct anv_pipeline *pipeline,
  39                   const VkPipelineVertexInputStateCreateInfo *info,
  40                   const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    uint32_t elements;
  43    if (extra && extra->disable_vs) {
  44       /* If the VS is disabled, just assume the user knows what they're
  45        * doing and apply the layout blindly.  This can only come from
  46        * meta, so this *should* be safe.
  47        */
  48       elements = 0;
  49       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  50          elements |= (1 << info->pVertexAttributeDescriptions[i].location);
  51    } else {
  52       /* Pull inputs_read out of the VS prog data */
  53       uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
  54       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  55       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
  56    }
  57
  58    uint32_t vb_count = __builtin_popcount(elements);
  59
  60    if (pipeline->vs_prog_data.uses_vertexid ||
  61        pipeline->vs_prog_data.uses_instanceid)
  62       vb_count++;
  63
  64    if (vb_count == 0)
  65       return;
  66
  67    const uint32_t num_dwords = 1 + vb_count * 2;
  68
  69    uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
  70                                  GEN7_3DSTATE_VERTEX_ELEMENTS);
  71    memset(p + 1, 0, (num_dwords - 1) * 4);
  72
  73    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  74       const VkVertexInputAttributeDescription *desc =
  75          &info->pVertexAttributeDescriptions[i];
  76       enum isl_format format = anv_get_isl_format(desc->format,
  77                                                   VK_IMAGE_ASPECT_COLOR_BIT,
  78                                                   VK_IMAGE_TILING_LINEAR);
  79
  80       assert(desc->binding < 32);
  81
  82       if ((elements & (1 << desc->location)) == 0)
  83          continue; /* Binding unused */
  84
  85       uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
  86
  87       struct GEN7_VERTEX_ELEMENT_STATE element = {
  88          .VertexBufferIndex = desc->binding,
  89          .Valid = true,
  90          .SourceElementFormat = format,
  91          .EdgeFlagEnable = false,
  92          .SourceElementOffset = desc->offset,
  93          .Component0Control = vertex_element_comp_control(format, 0),
  94          .Component1Control = vertex_element_comp_control(format, 1),
  95          .Component2Control = vertex_element_comp_control(format, 2),
  96          .Component3Control = vertex_element_comp_control(format, 3),
  97       };
  98       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
  99    }
 100
 101    if (pipeline->vs_prog_data.uses_vertexid ||
 102        pipeline->vs_prog_data.uses_instanceid) {
 103       struct GEN7_VERTEX_ELEMENT_STATE element = {
 104          .Valid = true,
 105          /* FIXME: Do we need to provide the base vertex as component 0 here
 106           * to support the correct base vertex ID? */
 107          .Component0Control = VFCOMP_STORE_0,
 108          .Component1Control = VFCOMP_STORE_0,
 109          .Component2Control = VFCOMP_STORE_VID,
 110          .Component3Control = VFCOMP_STORE_IID
 111       };
 112       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
 113    }
 114 }
 115
 116 static void
 117 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 118                    const VkPipelineRasterizationStateCreateInfo *info,
 119                    const struct anv_graphics_pipeline_create_info *extra)
 120 {
 121    struct GEN7_3DSTATE_SF sf = {
 122       GEN7_3DSTATE_SF_header,
 123
 124       /* FIXME: Get this from pass info */
 125       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 126
 127       /* LegacyGlobalDepthBiasEnable */
 128
 129       .StatisticsEnable                         = true,
 130       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 131       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 132       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 133       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 134       /* bool                                         AntiAliasingEnable; */
 135
 136       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 137
 138       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 139       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 140
 141       /* uint32_t                                     MultisampleRasterizationMode; */
 142       /* bool                                         LastPixelEnable; */
 143
 144       .TriangleStripListProvokingVertexSelect   = 0,
 145       .LineStripListProvokingVertexSelect       = 0,
 146       .TriangleFanProvokingVertexSelect         = 0,
 147
 148       /* uint32_t                                     AALineDistanceMode; */
 149       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 150       .UsePointWidthState                       = !pipeline->writes_point_size,
 151       .PointWidth                               = 1.0,
 152    };
 153
 154    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 155 }
 156
 157 static void
 158 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 159                    const VkPipelineDepthStencilStateCreateInfo *info)
 160 {
 161    if (info == NULL) {
 162       /* We're going to OR this together with the dynamic state.  We need
 163        * to make sure it's initialized to something useful.
 164        */
 165       memset(pipeline->gen7.depth_stencil_state, 0,
 166              sizeof(pipeline->gen7.depth_stencil_state));
 167       return;
 168    }
 169
 170    struct GEN7_DEPTH_STENCIL_STATE state = {
 171       .DepthTestEnable = info->depthTestEnable,
 172       .DepthBufferWriteEnable = info->depthWriteEnable,
 173       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 174       .DoubleSidedStencilEnable = true,
 175
 176       .StencilTestEnable = info->stencilTestEnable,
 177       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 178       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 179       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 180       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 181
 182       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 183       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 184       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 185       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 186    };
 187
 188    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 189 }
 190
 191 static void
 192 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 193                    const VkPipelineColorBlendStateCreateInfo *info,
 194                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 195 {
 196    struct anv_device *device = pipeline->device;
 197
 198    if (info->pAttachments == NULL) {
 199       pipeline->blend_state =
 200          anv_state_pool_emit(&device->dynamic_state_pool,
 201             GEN7_BLEND_STATE, 64,
 202             .ColorBufferBlendEnable = false,
 203             .WriteDisableAlpha = false,
 204             .WriteDisableRed = false,
 205             .WriteDisableGreen = false,
 206             .WriteDisableBlue = false);
 207    } else {
 208       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 209        * can't implement this.
 210        */
 211       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 212       pipeline->blend_state =
 213          anv_state_pool_emit(&device->dynamic_state_pool,
 214             GEN7_BLEND_STATE, 64,
 215
 216             .ColorBufferBlendEnable = a->blendEnable,
 217             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 218             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 219
 220             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 221             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 222
 223             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 224             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 225             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 226             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 227
 228 #     if 0
 229             bool                                AlphaToOneEnable;
 230             bool                                AlphaToCoverageDitherEnable;
 231 #     endif
 232
 233             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 234             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 235             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 236             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 237
 238             .LogicOpEnable = info->logicOpEnable,
 239             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 240
 241 #     if 0
 242             bool                                AlphaTestEnable;
 243             uint32_t                            AlphaTestFunction;
 244             bool                                ColorDitherEnable;
 245             uint32_t                            XDitherOffset;
 246             uint32_t                            YDitherOffset;
 247             uint32_t                            ColorClampRange;
 248             bool                                PreBlendColorClampEnable;
 249             bool                                PostBlendColorClampEnable;
 250 #     endif
 251             );
 252     }
 253
 254    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 255                   .BlendStatePointer = pipeline->blend_state.offset);
 256 }
 257
 258 static inline uint32_t
 259 scratch_space(const struct brw_stage_prog_data *prog_data)
 260 {
 261    return ffs(prog_data->total_scratch / 1024);
 262 }
 263
 264 GENX_FUNC(GEN7, GEN75) VkResult
 265 genX(graphics_pipeline_create)(
 266     VkDevice                                    _device,
 267     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 268     const struct anv_graphics_pipeline_create_info *extra,
 269     const VkAllocationCallbacks*                pAllocator,
 270     VkPipeline*                                 pPipeline)
 271 {
 272    ANV_FROM_HANDLE(anv_device, device, _device);
 273    struct anv_pipeline *pipeline;
 274    VkResult result;
 275
 276    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 277
 278    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 279                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 280    if (pipeline == NULL)
 281       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 282
 283    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 284    if (result != VK_SUCCESS) {
 285       anv_free2(&device->alloc, pAllocator, pipeline);
 286       return result;
 287    }
 288
 289    assert(pCreateInfo->pVertexInputState);
 290    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 291
 292    assert(pCreateInfo->pRasterizationState);
 293    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 294
 295    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 296
 297    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 298                                 pCreateInfo->pMultisampleState);
 299
 300    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 301                    .StatisticsEnable = true);
 302    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 303    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 304    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 305    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 306
 307    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 308     *
 309     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 310     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 311     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 312     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 313     *    needs to be sent before any combination of VS associated 3DSTATE."
 314     */
 315    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 316                   .DepthStallEnable = true,
 317                   .PostSyncOperation = WriteImmediateData,
 318                   .Address = { &device->workaround_bo, 0 });
 319
 320    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 321                   .ConstantBufferOffset = 0,
 322                   .ConstantBufferSize = 4);
 323    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 324                   .ConstantBufferOffset = 4,
 325                   .ConstantBufferSize = 4);
 326    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 327                   .ConstantBufferOffset = 8,
 328                   .ConstantBufferSize = 4);
 329
 330    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 331
 332    const VkPipelineRasterizationStateCreateInfo *rs_info =
 333       pCreateInfo->pRasterizationState;
 334
 335    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 336       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 337       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 338       .ClipEnable                               = true,
 339       .APIMode                                  = APIMODE_OGL,
 340       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 341       .ClipMode                                 = CLIPMODE_NORMAL,
 342       .TriangleStripListProvokingVertexSelect   = 0,
 343       .LineStripListProvokingVertexSelect       = 0,
 344       .TriangleFanProvokingVertexSelect         = 0,
 345       .MinimumPointWidth                        = 0.125,
 346       .MaximumPointWidth                        = 255.875);
 347
 348    uint32_t samples = 1;
 349    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 350
 351    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 352       .PixelLocation                            = PIXLOC_CENTER,
 353       .NumberofMultisamples                     = log2_samples);
 354
 355    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 356       .SampleMask                               = 0xff);
 357
 358    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 359       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 360       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 361       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 362
 363    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 364       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 365       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 366       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 367
 368    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 369       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 370       .HSURBEntryAllocationSize                 = 0,
 371       .HSNumberofURBEntries                     = 0);
 372
 373    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 374       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 375       .DSURBEntryAllocationSize                 = 0,
 376       .DSNumberofURBEntries                     = 0);
 377
 378    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 379    /* The last geometry producing stage will set urb_offset and urb_length,
 380     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 381    uint32_t urb_offset = 1;
 382    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 383
 384 #if 0
 385    /* From gen7_vs_state.c */
 386
 387    /**
 388     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 389     * Geometry > Geometry Shader > State:
 390     *
 391     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 392     *     whole fixed function pipeline when the GS enable changes value in
 393     *     the 3DSTATE_GS."
 394     *
 395     * The hardware architects have clarified that in this context "flush the
 396     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 397     * Stall" bit set.
 398     */
 399    if (!brw->is_haswell && !brw->is_baytrail)
 400       gen7_emit_vs_workaround_flush(brw);
 401 #endif
 402
 403    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 404       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 405    else
 406       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 407          .KernelStartPointer                    = pipeline->vs_vec4,
 408          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 409          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 410
 411          .DispatchGRFStartRegisterforURBData    =
 412             vue_prog_data->base.dispatch_grf_start_reg,
 413          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 414          .VertexURBEntryReadOffset              = 0,
 415
 416          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 417          .StatisticsEnable                      = true,
 418          .VSFunctionEnable                      = true);
 419
 420    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 421
 422    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 423       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 424    } else {
 425       urb_offset = 1;
 426       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 427
 428       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 429          .KernelStartPointer                    = pipeline->gs_kernel,
 430          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 431          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 432
 433          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 434          .OutputTopology                        = gs_prog_data->output_topology,
 435          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 436          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 437          .DispatchGRFStartRegisterforURBData    =
 438             gs_prog_data->base.base.dispatch_grf_start_reg,
 439
 440          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 441          /* This in the next dword on HSW. */
 442          .ControlDataFormat                     = gs_prog_data->control_data_format,
 443          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 444          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 445          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 446          .GSStatisticsEnable                    = true,
 447          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 448 #     if (ANV_IS_HASWELL)
 449          .ReorderMode                           = REORDER_TRAILING,
 450 #     else
 451          .ReorderEnable                         = true,
 452 #     endif
 453          .GSEnable                              = true);
 454    }
 455
 456    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 457    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 458        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 459       anv_finishme("two-sided color needs sbe swizzling setup");
 460    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 461       anv_finishme("primitive_id needs sbe swizzling setup");
 462
 463    /* FIXME: generated header doesn't emit attr swizzle fields */
 464    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 465       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 466       .VertexURBEntryReadLength                 = urb_length,
 467       .VertexURBEntryReadOffset                 = urb_offset,
 468       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 469
 470    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 471       .KernelStartPointer0                      = pipeline->ps_ksp0,
 472       .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 473       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 474
 475       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 476       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 477       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 478       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 479
 480       .RenderTargetFastClearEnable              = false,
 481       .DualSourceBlendEnable                    = false,
 482       .RenderTargetResolveEnable                = false,
 483
 484       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 485          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 486
 487       ._32PixelDispatchEnable                   = false,
 488       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 489       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 490
 491       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 492       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 493       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 494
 495 #if 0
 496    /* Haswell requires the sample mask to be set in this packet as well as
 497     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 498    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 499 #endif
 500
 501       .KernelStartPointer1                      = 0,
 502       .KernelStartPointer2                      = pipeline->ps_ksp2);
 503
 504    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 505    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 506       .StatisticsEnable                         = true,
 507       .ThreadDispatchEnable                     = true,
 508       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 509       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 510       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 511       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 512       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 513       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 514
 515    *pPipeline = anv_pipeline_to_handle(pipeline);
 516
 517    return VK_SUCCESS;
 518 }
 519
 520 GENX_FUNC(GEN7, GEN75) VkResult
 521 genX(compute_pipeline_create)(
 522     VkDevice                                    _device,
 523     const VkComputePipelineCreateInfo*          pCreateInfo,
 524     const VkAllocationCallbacks*                pAllocator,
 525     VkPipeline*                                 pPipeline)
 526 {
 527    anv_finishme("primitive_id needs sbe swizzling setup");
 528    abort();
 529 }