src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 emit_vertex_input(struct anv_pipeline *pipeline,
  37                   const VkPipelineVertexInputStateCreateInfo *info,
  38                   const struct anv_graphics_pipeline_create_info *extra)
  39 {
  40
  41    uint32_t vb_used;
  42    if (extra && extra->disable_vs) {
  43       /* If the VS is disabled, just assume the user knows what they're
  44        * doing and apply the layout blindly.  This can only come from
  45        * meta, so this *should* be safe.
  46        */
  47       vb_used = 0;
  48       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  49          vb_used |= (1 << info->pVertexAttributeDescriptions[i].location);
  50    } else {
  51       /* Pull inputs_read out of the VS prog data */
  52       uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
  53       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  54       vb_used = inputs_read >> VERT_ATTRIB_GENERIC0;
  55    }
  56
  57    uint32_t vb_count = __builtin_popcount(vb_used);
  58
  59    if (pipeline->vs_prog_data.uses_vertexid ||
  60        pipeline->vs_prog_data.uses_instanceid)
  61       vb_count++;
  62
  63    if (vb_count == 0)
  64       return;
  65
  66    const uint32_t num_dwords = 1 + vb_count * 2;
  67
  68    uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
  69                                  GEN7_3DSTATE_VERTEX_ELEMENTS);
  70    memset(p + 1, 0, (num_dwords - 1) * 4);
  71
  72    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  73       const VkVertexInputAttributeDescription *desc =
  74          &info->pVertexAttributeDescriptions[i];
  75       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  76
  77       assert(desc->binding < 32);
  78
  79       if ((vb_used & (1 << desc->location)) == 0)
  80          continue; /* Binding unused */
  81
  82       uint32_t slot = __builtin_popcount(vb_used & ((1 << desc->location) - 1));
  83
  84       struct GEN7_VERTEX_ELEMENT_STATE element = {
  85          .VertexBufferIndex = desc->binding,
  86          .Valid = true,
  87          .SourceElementFormat = format->surface_format,
  88          .EdgeFlagEnable = false,
  89          .SourceElementOffset = desc->offset,
  90          .Component0Control = VFCOMP_STORE_SRC,
  91          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  92          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  93          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  94       };
  95       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
  96    }
  97
  98    if (pipeline->vs_prog_data.uses_vertexid ||
  99        pipeline->vs_prog_data.uses_instanceid) {
 100       struct GEN7_VERTEX_ELEMENT_STATE element = {
 101          .Valid = true,
 102          /* FIXME: Do we need to provide the base vertex as component 0 here
 103           * to support the correct base vertex ID? */
 104          .Component0Control = VFCOMP_STORE_0,
 105          .Component1Control = VFCOMP_STORE_0,
 106          .Component2Control = VFCOMP_STORE_VID,
 107          .Component3Control = VFCOMP_STORE_IID
 108       };
 109       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
 110    }
 111 }
 112
 113 static const uint32_t vk_to_gen_cullmode[] = {
 114    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
 115    [VK_CULL_MODE_FRONT_BIT]                     = CULLMODE_FRONT,
 116    [VK_CULL_MODE_BACK_BIT]                      = CULLMODE_BACK,
 117    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
 118 };
 119
 120 static const uint32_t vk_to_gen_fillmode[] = {
 121    [VK_POLYGON_MODE_FILL]                       = RASTER_SOLID,
 122    [VK_POLYGON_MODE_LINE]                       = RASTER_WIREFRAME,
 123    [VK_POLYGON_MODE_POINT]                      = RASTER_POINT,
 124 };
 125
 126 static const uint32_t vk_to_gen_front_face[] = {
 127    [VK_FRONT_FACE_COUNTER_CLOCKWISE]            = 1,
 128    [VK_FRONT_FACE_CLOCKWISE]                    = 0
 129 };
 130
 131 static void
 132 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 133                    const VkPipelineRasterizationStateCreateInfo *info,
 134                    const struct anv_graphics_pipeline_create_info *extra)
 135 {
 136    struct GEN7_3DSTATE_SF sf = {
 137       GEN7_3DSTATE_SF_header,
 138
 139       /* FIXME: Get this from pass info */
 140       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 141
 142       /* LegacyGlobalDepthBiasEnable */
 143
 144       .StatisticsEnable                         = true,
 145       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 146       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 147       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 148       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 149       /* bool                                         AntiAliasingEnable; */
 150
 151       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 152
 153       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 154       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 155
 156       /* uint32_t                                     MultisampleRasterizationMode; */
 157       /* bool                                         LastPixelEnable; */
 158
 159       .TriangleStripListProvokingVertexSelect   = 0,
 160       .LineStripListProvokingVertexSelect       = 0,
 161       .TriangleFanProvokingVertexSelect         = 0,
 162
 163       /* uint32_t                                     AALineDistanceMode; */
 164       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 165       .UsePointWidthState                       = !pipeline->writes_point_size,
 166       .PointWidth                               = 1.0,
 167    };
 168
 169    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 170 }
 171
 172 static const uint32_t vk_to_gen_compare_op[] = {
 173    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 174    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 175    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 176    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 177    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 178    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 179    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 180    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 181 };
 182
 183 static const uint32_t vk_to_gen_stencil_op[] = {
 184    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 185    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 186    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 187    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 188    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 189    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 190    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 191    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 192 };
 193
 194 static const uint32_t vk_to_gen_blend_op[] = {
 195    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 196    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 197    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 198    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 199    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 200 };
 201
 202 static const uint32_t vk_to_gen_logic_op[] = {
 203    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 204    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 205    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 206    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 207    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 208    [VK_LOGIC_OP_NO_OP]                          = LOGICOP_NOOP,
 209    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 210    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 211    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 212    [VK_LOGIC_OP_EQUIVALENT]                     = LOGICOP_EQUIV,
 213    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 214    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 215    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 216    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 217    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 218    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 219 };
 220
 221 static const uint32_t vk_to_gen_blend[] = {
 222    [VK_BLEND_FACTOR_ZERO]                       = BLENDFACTOR_ZERO,
 223    [VK_BLEND_FACTOR_ONE]                        = BLENDFACTOR_ONE,
 224    [VK_BLEND_FACTOR_SRC_COLOR]                  = BLENDFACTOR_SRC_COLOR,
 225    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]        = BLENDFACTOR_INV_SRC_COLOR,
 226    [VK_BLEND_FACTOR_DST_COLOR]                  = BLENDFACTOR_DST_COLOR,
 227    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]        = BLENDFACTOR_INV_DST_COLOR,
 228    [VK_BLEND_FACTOR_SRC_ALPHA]                  = BLENDFACTOR_SRC_ALPHA,
 229    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]        = BLENDFACTOR_INV_SRC_ALPHA,
 230    [VK_BLEND_FACTOR_DST_ALPHA]                  = BLENDFACTOR_DST_ALPHA,
 231    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]        = BLENDFACTOR_INV_DST_ALPHA,
 232    [VK_BLEND_FACTOR_CONSTANT_COLOR]             = BLENDFACTOR_CONST_COLOR,
 233    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]   = BLENDFACTOR_INV_CONST_COLOR,
 234    [VK_BLEND_FACTOR_CONSTANT_ALPHA]             = BLENDFACTOR_CONST_ALPHA,
 235    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]   = BLENDFACTOR_INV_CONST_ALPHA,
 236    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]         = BLENDFACTOR_SRC_ALPHA_SATURATE,
 237    [VK_BLEND_FACTOR_SRC1_COLOR]                 = BLENDFACTOR_SRC1_COLOR,
 238    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]       = BLENDFACTOR_INV_SRC1_COLOR,
 239    [VK_BLEND_FACTOR_SRC1_ALPHA]                 = BLENDFACTOR_SRC1_ALPHA,
 240    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]       = BLENDFACTOR_INV_SRC1_ALPHA,
 241 };
 242
 243 static void
 244 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 245                    const VkPipelineDepthStencilStateCreateInfo *info)
 246 {
 247    if (info == NULL) {
 248       /* We're going to OR this together with the dynamic state.  We need
 249        * to make sure it's initialized to something useful.
 250        */
 251       memset(pipeline->gen7.depth_stencil_state, 0,
 252              sizeof(pipeline->gen7.depth_stencil_state));
 253       return;
 254    }
 255
 256    struct GEN7_DEPTH_STENCIL_STATE state = {
 257       .DepthTestEnable = info->depthTestEnable,
 258       .DepthBufferWriteEnable = info->depthWriteEnable,
 259       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 260       .DoubleSidedStencilEnable = true,
 261
 262       .StencilTestEnable = info->stencilTestEnable,
 263       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 264       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 265       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 266       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 267
 268       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 269       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 270       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 271       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 272    };
 273
 274    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 275 }
 276
 277 static void
 278 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 279                    const VkPipelineColorBlendStateCreateInfo *info,
 280                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 281 {
 282    struct anv_device *device = pipeline->device;
 283
 284    if (info->pAttachments == NULL) {
 285       pipeline->blend_state =
 286          anv_state_pool_emit(&device->dynamic_state_pool,
 287             GEN7_BLEND_STATE, 64,
 288             .ColorBufferBlendEnable = false,
 289             .WriteDisableAlpha = false,
 290             .WriteDisableRed = false,
 291             .WriteDisableGreen = false,
 292             .WriteDisableBlue = false);
 293    } else {
 294       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 295        * can't implement this.
 296        */
 297       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 298       pipeline->blend_state =
 299          anv_state_pool_emit(&device->dynamic_state_pool,
 300             GEN7_BLEND_STATE, 64,
 301
 302             .ColorBufferBlendEnable = a->blendEnable,
 303             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 304             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 305
 306             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 307             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 308
 309             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 310             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 311             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 312             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 313
 314 #     if 0
 315             bool                                AlphaToOneEnable;
 316             bool                                AlphaToCoverageDitherEnable;
 317 #     endif
 318
 319             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 320             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 321             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 322             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 323
 324             .LogicOpEnable = info->logicOpEnable,
 325             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 326
 327 #     if 0
 328             bool                                AlphaTestEnable;
 329             uint32_t                            AlphaTestFunction;
 330             bool                                ColorDitherEnable;
 331             uint32_t                            XDitherOffset;
 332             uint32_t                            YDitherOffset;
 333             uint32_t                            ColorClampRange;
 334             bool                                PreBlendColorClampEnable;
 335             bool                                PostBlendColorClampEnable;
 336 #     endif
 337             );
 338     }
 339
 340    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 341                   .BlendStatePointer = pipeline->blend_state.offset);
 342 }
 343
 344 static inline uint32_t
 345 scratch_space(const struct brw_stage_prog_data *prog_data)
 346 {
 347    return ffs(prog_data->total_scratch / 1024);
 348 }
 349
 350 GENX_FUNC(GEN7, GEN75) VkResult
 351 genX(graphics_pipeline_create)(
 352     VkDevice                                    _device,
 353     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 354     const struct anv_graphics_pipeline_create_info *extra,
 355     const VkAllocationCallbacks*                pAllocator,
 356     VkPipeline*                                 pPipeline)
 357 {
 358    ANV_FROM_HANDLE(anv_device, device, _device);
 359    struct anv_pipeline *pipeline;
 360    VkResult result;
 361
 362    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 363
 364    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 365                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 366    if (pipeline == NULL)
 367       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 368
 369    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 370    if (result != VK_SUCCESS) {
 371       anv_free2(&device->alloc, pAllocator, pipeline);
 372       return result;
 373    }
 374
 375    assert(pCreateInfo->pVertexInputState);
 376    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 377
 378    assert(pCreateInfo->pRasterizationState);
 379    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 380
 381    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 382
 383    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 384                                 pCreateInfo->pMultisampleState);
 385
 386    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 387                    .StatisticsEnable = true);
 388    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 389    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 390    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 391    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 392
 393    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 394     *
 395     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 396     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 397     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 398     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 399     *    needs to be sent before any combination of VS associated 3DSTATE."
 400     */
 401    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 402                   .DepthStallEnable = true,
 403                   .PostSyncOperation = WriteImmediateData,
 404                   .Address = { &device->workaround_bo, 0 });
 405
 406    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 407                   .ConstantBufferOffset = 0,
 408                   .ConstantBufferSize = 4);
 409    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 410                   .ConstantBufferOffset = 4,
 411                   .ConstantBufferSize = 4);
 412    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 413                   .ConstantBufferOffset = 8,
 414                   .ConstantBufferSize = 4);
 415
 416    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 417
 418    const VkPipelineRasterizationStateCreateInfo *rs_info =
 419       pCreateInfo->pRasterizationState;
 420
 421    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 422       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 423       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 424       .ClipEnable                               = true,
 425       .APIMode                                  = APIMODE_OGL,
 426       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 427       .ClipMode                                 = CLIPMODE_NORMAL,
 428       .TriangleStripListProvokingVertexSelect   = 0,
 429       .LineStripListProvokingVertexSelect       = 0,
 430       .TriangleFanProvokingVertexSelect         = 0,
 431       .MinimumPointWidth                        = 0.125,
 432       .MaximumPointWidth                        = 255.875);
 433
 434    uint32_t samples = 1;
 435    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 436
 437    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 438       .PixelLocation                            = PIXLOC_CENTER,
 439       .NumberofMultisamples                     = log2_samples);
 440
 441    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 442       .SampleMask                               = 0xff);
 443
 444    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 445       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 446       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 447       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 448
 449    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 450       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 451       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 452       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 453
 454    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 455       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 456       .HSURBEntryAllocationSize                 = 0,
 457       .HSNumberofURBEntries                     = 0);
 458
 459    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 460       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 461       .DSURBEntryAllocationSize                 = 0,
 462       .DSNumberofURBEntries                     = 0);
 463
 464    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 465    /* The last geometry producing stage will set urb_offset and urb_length,
 466     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 467    uint32_t urb_offset = 1;
 468    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 469
 470 #if 0
 471    /* From gen7_vs_state.c */
 472
 473    /**
 474     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 475     * Geometry > Geometry Shader > State:
 476     *
 477     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 478     *     whole fixed function pipeline when the GS enable changes value in
 479     *     the 3DSTATE_GS."
 480     *
 481     * The hardware architects have clarified that in this context "flush the
 482     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 483     * Stall" bit set.
 484     */
 485    if (!brw->is_haswell && !brw->is_baytrail)
 486       gen7_emit_vs_workaround_flush(brw);
 487 #endif
 488
 489    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 490       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 491    else
 492       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 493          .KernelStartPointer                    = pipeline->vs_vec4,
 494          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 495          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 496
 497          .DispatchGRFStartRegisterforURBData    =
 498             vue_prog_data->base.dispatch_grf_start_reg,
 499          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 500          .VertexURBEntryReadOffset              = 0,
 501
 502          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 503          .StatisticsEnable                      = true,
 504          .VSFunctionEnable                      = true);
 505
 506    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 507
 508    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 509       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 510    } else {
 511       urb_offset = 1;
 512       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 513
 514       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 515          .KernelStartPointer                    = pipeline->gs_kernel,
 516          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 517          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 518
 519          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 520          .OutputTopology                        = gs_prog_data->output_topology,
 521          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 522          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 523          .DispatchGRFStartRegisterforURBData    =
 524             gs_prog_data->base.base.dispatch_grf_start_reg,
 525
 526          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 527          /* This in the next dword on HSW. */
 528          .ControlDataFormat                     = gs_prog_data->control_data_format,
 529          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 530          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 531          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 532          .GSStatisticsEnable                    = true,
 533          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 534 #     if (ANV_IS_HASWELL)
 535          .ReorderMode                           = REORDER_TRAILING,
 536 #     else
 537          .ReorderEnable                         = true,
 538 #     endif
 539          .GSEnable                              = true);
 540    }
 541
 542    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 543    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 544        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 545       anv_finishme("two-sided color needs sbe swizzling setup");
 546    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 547       anv_finishme("primitive_id needs sbe swizzling setup");
 548
 549    /* FIXME: generated header doesn't emit attr swizzle fields */
 550    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 551       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 552       .VertexURBEntryReadLength                 = urb_length,
 553       .VertexURBEntryReadOffset                 = urb_offset,
 554       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 555
 556    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 557       .KernelStartPointer0                      = pipeline->ps_ksp0,
 558       .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 559       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 560
 561       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 562       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 563       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 564       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 565
 566       .RenderTargetFastClearEnable              = false,
 567       .DualSourceBlendEnable                    = false,
 568       .RenderTargetResolveEnable                = false,
 569
 570       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 571          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 572
 573       ._32PixelDispatchEnable                   = false,
 574       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 575       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 576
 577       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 578       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 579       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 580
 581 #if 0
 582    /* Haswell requires the sample mask to be set in this packet as well as
 583     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 584    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 585 #endif
 586
 587       .KernelStartPointer1                      = 0,
 588       .KernelStartPointer2                      = pipeline->ps_ksp2);
 589
 590    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 591    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 592       .StatisticsEnable                         = true,
 593       .ThreadDispatchEnable                     = true,
 594       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 595       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 596       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 597       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 598       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 599       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 600
 601    *pPipeline = anv_pipeline_to_handle(pipeline);
 602
 603    return VK_SUCCESS;
 604 }
 605
 606 GENX_FUNC(GEN7, GEN75) VkResult
 607 genX(compute_pipeline_create)(
 608     VkDevice                                    _device,
 609     const VkComputePipelineCreateInfo*          pCreateInfo,
 610     const VkAllocationCallbacks*                pAllocator,
 611     VkPipeline*                                 pPipeline)
 612 {
 613    anv_finishme("primitive_id needs sbe swizzling setup");
 614    abort();
 615 }