2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "gen7_pack.h"
33 #include "gen75_pack.h"
35 #include "genX_pipeline_util.h"
38 emit_vertex_input(struct anv_pipeline
*pipeline
,
39 const VkPipelineVertexInputStateCreateInfo
*info
,
40 const struct anv_graphics_pipeline_create_info
*extra
)
43 if (extra
&& extra
->disable_vs
) {
44 /* If the VS is disabled, just assume the user knows what they're
45 * doing and apply the layout blindly. This can only come from
46 * meta, so this *should* be safe.
49 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++)
50 elements
|= (1 << info
->pVertexAttributeDescriptions
[i
].location
);
52 /* Pull inputs_read out of the VS prog data */
53 uint64_t inputs_read
= pipeline
->vs_prog_data
.inputs_read
;
54 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
55 elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
58 uint32_t vb_count
= __builtin_popcount(elements
);
60 if (pipeline
->vs_prog_data
.uses_vertexid
||
61 pipeline
->vs_prog_data
.uses_instanceid
)
67 const uint32_t num_dwords
= 1 + vb_count
* 2;
69 uint32_t *p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
70 GEN7_3DSTATE_VERTEX_ELEMENTS
);
71 memset(p
+ 1, 0, (num_dwords
- 1) * 4);
73 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
74 const VkVertexInputAttributeDescription
*desc
=
75 &info
->pVertexAttributeDescriptions
[i
];
76 enum isl_format format
= anv_get_isl_format(desc
->format
,
77 VK_IMAGE_ASPECT_COLOR_BIT
,
78 VK_IMAGE_TILING_LINEAR
);
80 assert(desc
->binding
< 32);
82 if ((elements
& (1 << desc
->location
)) == 0)
83 continue; /* Binding unused */
85 uint32_t slot
= __builtin_popcount(elements
& ((1 << desc
->location
) - 1));
87 struct GEN7_VERTEX_ELEMENT_STATE element
= {
88 .VertexBufferIndex
= desc
->binding
,
90 .SourceElementFormat
= format
,
91 .EdgeFlagEnable
= false,
92 .SourceElementOffset
= desc
->offset
,
93 .Component0Control
= vertex_element_comp_control(format
, 0),
94 .Component1Control
= vertex_element_comp_control(format
, 1),
95 .Component2Control
= vertex_element_comp_control(format
, 2),
96 .Component3Control
= vertex_element_comp_control(format
, 3),
98 GEN7_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + slot
* 2], &element
);
101 if (pipeline
->vs_prog_data
.uses_vertexid
||
102 pipeline
->vs_prog_data
.uses_instanceid
) {
103 struct GEN7_VERTEX_ELEMENT_STATE element
= {
105 /* FIXME: Do we need to provide the base vertex as component 0 here
106 * to support the correct base vertex ID? */
107 .Component0Control
= VFCOMP_STORE_0
,
108 .Component1Control
= VFCOMP_STORE_0
,
109 .Component2Control
= VFCOMP_STORE_VID
,
110 .Component3Control
= VFCOMP_STORE_IID
112 GEN7_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + (vb_count
- 1) * 2], &element
);
117 gen7_emit_rs_state(struct anv_pipeline
*pipeline
,
118 const VkPipelineRasterizationStateCreateInfo
*info
,
119 const struct anv_graphics_pipeline_create_info
*extra
)
121 struct GEN7_3DSTATE_SF sf
= {
122 GEN7_3DSTATE_SF_header
,
124 /* FIXME: Get this from pass info */
125 .DepthBufferSurfaceFormat
= D24_UNORM_X8_UINT
,
127 /* LegacyGlobalDepthBiasEnable */
129 .StatisticsEnable
= true,
130 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
131 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
132 .ViewTransformEnable
= !(extra
&& extra
->disable_viewport
),
133 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
134 /* bool AntiAliasingEnable; */
136 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
138 /* uint32_t LineEndCapAntialiasingRegionWidth; */
139 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
141 /* uint32_t MultisampleRasterizationMode; */
142 /* bool LastPixelEnable; */
144 .TriangleStripListProvokingVertexSelect
= 0,
145 .LineStripListProvokingVertexSelect
= 0,
146 .TriangleFanProvokingVertexSelect
= 0,
148 /* uint32_t AALineDistanceMode; */
149 /* uint32_t VertexSubPixelPrecisionSelect; */
150 .UsePointWidthState
= !pipeline
->writes_point_size
,
154 GEN7_3DSTATE_SF_pack(NULL
, &pipeline
->gen7
.sf
, &sf
);
158 gen7_emit_ds_state(struct anv_pipeline
*pipeline
,
159 const VkPipelineDepthStencilStateCreateInfo
*info
)
162 /* We're going to OR this together with the dynamic state. We need
163 * to make sure it's initialized to something useful.
165 memset(pipeline
->gen7
.depth_stencil_state
, 0,
166 sizeof(pipeline
->gen7
.depth_stencil_state
));
170 struct GEN7_DEPTH_STENCIL_STATE state
= {
171 .DepthTestEnable
= info
->depthTestEnable
,
172 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
173 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
174 .DoubleSidedStencilEnable
= true,
176 .StencilTestEnable
= info
->stencilTestEnable
,
177 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
178 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
179 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
180 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
182 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
183 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
184 .BackfaceStencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
185 .BackFaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
188 GEN7_DEPTH_STENCIL_STATE_pack(NULL
, &pipeline
->gen7
.depth_stencil_state
, &state
);
192 gen7_emit_cb_state(struct anv_pipeline
*pipeline
,
193 const VkPipelineColorBlendStateCreateInfo
*info
,
194 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
196 struct anv_device
*device
= pipeline
->device
;
198 if (info
->pAttachments
== NULL
) {
199 pipeline
->blend_state
=
200 anv_state_pool_emit(&device
->dynamic_state_pool
,
201 GEN7_BLEND_STATE
, 64,
202 .ColorBufferBlendEnable
= false,
203 .WriteDisableAlpha
= false,
204 .WriteDisableRed
= false,
205 .WriteDisableGreen
= false,
206 .WriteDisableBlue
= false);
208 /* FIXME-GEN7: All render targets share blend state settings on gen7, we
209 * can't implement this.
211 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[0];
212 pipeline
->blend_state
=
213 anv_state_pool_emit(&device
->dynamic_state_pool
,
214 GEN7_BLEND_STATE
, 64,
216 .ColorBufferBlendEnable
= a
->blendEnable
,
217 .IndependentAlphaBlendEnable
= true, /* FIXME: yes? */
218 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
220 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
221 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
223 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
224 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
225 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
226 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
229 bool AlphaToOneEnable
;
230 bool AlphaToCoverageDitherEnable
;
233 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
234 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
235 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
236 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
238 .LogicOpEnable
= info
->logicOpEnable
,
239 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
242 bool AlphaTestEnable
;
243 uint32_t AlphaTestFunction
;
244 bool ColorDitherEnable
;
245 uint32_t XDitherOffset
;
246 uint32_t YDitherOffset
;
247 uint32_t ColorClampRange
;
248 bool PreBlendColorClampEnable
;
249 bool PostBlendColorClampEnable
;
254 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_BLEND_STATE_POINTERS
,
255 .BlendStatePointer
= pipeline
->blend_state
.offset
);
258 static inline uint32_t
259 scratch_space(const struct brw_stage_prog_data
*prog_data
)
261 return ffs(prog_data
->total_scratch
/ 1024);
264 GENX_FUNC(GEN7
, GEN75
) VkResult
265 genX(graphics_pipeline_create
)(
267 struct anv_pipeline_cache
* cache
,
268 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
269 const struct anv_graphics_pipeline_create_info
*extra
,
270 const VkAllocationCallbacks
* pAllocator
,
271 VkPipeline
* pPipeline
)
273 ANV_FROM_HANDLE(anv_device
, device
, _device
);
274 struct anv_pipeline
*pipeline
;
277 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
279 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
280 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
281 if (pipeline
== NULL
)
282 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
284 result
= anv_pipeline_init(pipeline
, device
, cache
,
285 pCreateInfo
, extra
, pAllocator
);
286 if (result
!= VK_SUCCESS
) {
287 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
291 assert(pCreateInfo
->pVertexInputState
);
292 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
, extra
);
294 assert(pCreateInfo
->pRasterizationState
);
295 gen7_emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
, extra
);
297 gen7_emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
299 gen7_emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
300 pCreateInfo
->pMultisampleState
);
302 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_VF_STATISTICS
,
303 .StatisticsEnable
= true);
304 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_HS
, .Enable
= false);
305 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_TE
, .TEEnable
= false);
306 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_DS
, .DSFunctionEnable
= false);
307 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
309 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
311 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
312 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
313 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
314 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
315 * needs to be sent before any combination of VS associated 3DSTATE."
317 anv_batch_emit(&pipeline
->batch
, GEN7_PIPE_CONTROL
,
318 .DepthStallEnable
= true,
319 .PostSyncOperation
= WriteImmediateData
,
320 .Address
= { &device
->workaround_bo
, 0 });
322 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
323 .ConstantBufferOffset
= 0,
324 .ConstantBufferSize
= 4);
325 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
326 .ConstantBufferOffset
= 4,
327 .ConstantBufferSize
= 4);
328 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
329 .ConstantBufferOffset
= 8,
330 .ConstantBufferSize
= 4);
332 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_AA_LINE_PARAMETERS
);
334 const VkPipelineRasterizationStateCreateInfo
*rs_info
=
335 pCreateInfo
->pRasterizationState
;
337 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_CLIP
,
338 .FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
],
339 .CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
],
341 .APIMode
= APIMODE_OGL
,
342 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
343 .ClipMode
= CLIPMODE_NORMAL
,
344 .TriangleStripListProvokingVertexSelect
= 0,
345 .LineStripListProvokingVertexSelect
= 0,
346 .TriangleFanProvokingVertexSelect
= 0,
347 .MinimumPointWidth
= 0.125,
348 .MaximumPointWidth
= 255.875);
350 uint32_t samples
= 1;
351 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
353 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_MULTISAMPLE
,
354 .PixelLocation
= PIXLOC_CENTER
,
355 .NumberofMultisamples
= log2_samples
);
357 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_SAMPLE_MASK
,
360 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_VS
,
361 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
362 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
363 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
365 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_GS
,
366 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
367 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
368 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
370 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_HS
,
371 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
372 .HSURBEntryAllocationSize
= 0,
373 .HSNumberofURBEntries
= 0);
375 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_DS
,
376 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
377 .DSURBEntryAllocationSize
= 0,
378 .DSNumberofURBEntries
= 0);
380 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
381 /* The last geometry producing stage will set urb_offset and urb_length,
382 * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
383 uint32_t urb_offset
= 1;
384 uint32_t urb_length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_offset
;
387 /* From gen7_vs_state.c */
390 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
391 * Geometry > Geometry Shader > State:
393 * "Note: Because of corruption in IVB:GT2, software needs to flush the
394 * whole fixed function pipeline when the GS enable changes value in
397 * The hardware architects have clarified that in this context "flush the
398 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
401 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
402 gen7_emit_vs_workaround_flush(brw
);
405 if (pipeline
->vs_vec4
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
406 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), .VSFunctionEnable
= false);
408 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
409 .KernelStartPointer
= pipeline
->vs_vec4
,
410 .ScratchSpaceBaseOffset
= pipeline
->scratch_start
[MESA_SHADER_VERTEX
],
411 .PerThreadScratchSpace
= scratch_space(&vue_prog_data
->base
),
413 .DispatchGRFStartRegisterforURBData
=
414 vue_prog_data
->base
.dispatch_grf_start_reg
,
415 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
416 .VertexURBEntryReadOffset
= 0,
418 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
419 .StatisticsEnable
= true,
420 .VSFunctionEnable
= true);
422 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
424 if (pipeline
->gs_kernel
== NO_KERNEL
|| (extra
&& extra
->disable_vs
)) {
425 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), .GSEnable
= false);
428 urb_length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - urb_offset
;
430 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
),
431 .KernelStartPointer
= pipeline
->gs_kernel
,
432 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_GEOMETRY
],
433 .PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
),
435 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
436 .OutputTopology
= gs_prog_data
->output_topology
,
437 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
438 .IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
,
439 .DispatchGRFStartRegisterforURBData
=
440 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
442 .MaximumNumberofThreads
= device
->info
.max_gs_threads
- 1,
443 /* This in the next dword on HSW. */
444 .ControlDataFormat
= gs_prog_data
->control_data_format
,
445 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
446 .InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1,
447 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
448 .GSStatisticsEnable
= true,
449 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
450 # if (ANV_IS_HASWELL)
451 .ReorderMode
= REORDER_TRAILING
,
453 .ReorderEnable
= true,
458 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
459 if (wm_prog_data
->urb_setup
[VARYING_SLOT_BFC0
] != -1 ||
460 wm_prog_data
->urb_setup
[VARYING_SLOT_BFC1
] != -1)
461 anv_finishme("two-sided color needs sbe swizzling setup");
462 if (wm_prog_data
->urb_setup
[VARYING_SLOT_PRIMITIVE_ID
] != -1)
463 anv_finishme("primitive_id needs sbe swizzling setup");
465 /* FIXME: generated header doesn't emit attr swizzle fields */
466 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_SBE
,
467 .NumberofSFOutputAttributes
= pipeline
->wm_prog_data
.num_varying_inputs
,
468 .VertexURBEntryReadLength
= urb_length
,
469 .VertexURBEntryReadOffset
= urb_offset
,
470 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
);
472 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
473 .KernelStartPointer0
= pipeline
->ps_ksp0
,
474 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_FRAGMENT
],
475 .PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
),
477 .MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1,
478 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
479 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
480 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
482 .RenderTargetFastClearEnable
= false,
483 .DualSourceBlendEnable
= false,
484 .RenderTargetResolveEnable
= false,
486 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
487 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
489 ._32PixelDispatchEnable
= false,
490 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
491 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
493 .DispatchGRFStartRegisterforConstantSetupData0
= pipeline
->ps_grf_start0
,
494 .DispatchGRFStartRegisterforConstantSetupData1
= 0,
495 .DispatchGRFStartRegisterforConstantSetupData2
= pipeline
->ps_grf_start2
,
498 /* Haswell requires the sample mask to be set in this packet as well as
499 * in 3DSTATE_SAMPLE_MASK; the values should match. */
500 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
503 .KernelStartPointer1
= 0,
504 .KernelStartPointer2
= pipeline
->ps_ksp2
);
506 /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
507 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_WM
,
508 .StatisticsEnable
= true,
509 .ThreadDispatchEnable
= true,
510 .LineEndCapAntialiasingRegionWidth
= 0, /* 0.5 pixels */
511 .LineAntialiasingRegionWidth
= 1, /* 1.0 pixels */
512 .EarlyDepthStencilControl
= EDSC_NORMAL
,
513 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
514 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
515 .BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
);
517 *pPipeline
= anv_pipeline_to_handle(pipeline
);
522 GENX_FUNC(GEN7
, GEN75
) VkResult
523 genX(compute_pipeline_create
)(
525 struct anv_pipeline_cache
* cache
,
526 const VkComputePipelineCreateInfo
* pCreateInfo
,
527 const VkAllocationCallbacks
* pAllocator
,
528 VkPipeline
* pPipeline
)
530 anv_finishme("primitive_id needs sbe swizzling setup");