src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 gen7_emit_vertex_input(struct anv_pipeline *pipeline,
  37                        const VkPipelineVertexInputStateCreateInfo *info)
  38 {
  39    const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
  40       pipeline->vs_prog_data.uses_instanceid;
  41    const uint32_t element_count =
  42       info->vertexAttributeDescriptionCount + (sgvs ? 1 : 0);
  43    const uint32_t num_dwords = 1 + element_count * 2;
  44    uint32_t *p;
  45
  46    anv_finishme("gen7 vertex input needs to use inputs_read");
  47
  48    if (info->vertexAttributeDescriptionCount == 0 && !sgvs)
  49       return;
  50
  51    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  52                        GEN7_3DSTATE_VERTEX_ELEMENTS);
  53
  54    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  55       const VkVertexInputAttributeDescription *desc =
  56          &info->pVertexAttributeDescriptions[i];
  57       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  58
  59       struct GEN7_VERTEX_ELEMENT_STATE element = {
  60          .VertexBufferIndex = desc->binding,
  61          .Valid = true,
  62          .SourceElementFormat = format->surface_format,
  63          .EdgeFlagEnable = false,
  64          .SourceElementOffset = desc->offset,
  65          .Component0Control = VFCOMP_STORE_SRC,
  66          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  67          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  68          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  69       };
  70       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  71    }
  72
  73    if (sgvs) {
  74       struct GEN7_VERTEX_ELEMENT_STATE element = {
  75          .Valid = true,
  76          /* FIXME: Do we need to provide the base vertex as component 0 here
  77           * to support the correct base vertex ID? */
  78          .Component0Control = VFCOMP_STORE_0,
  79          .Component1Control = VFCOMP_STORE_0,
  80          .Component2Control = VFCOMP_STORE_VID,
  81          .Component3Control = VFCOMP_STORE_IID
  82       };
  83       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->vertexAttributeDescriptionCount * 2], &element);
  84    }
  85 }
  86
  87 static const uint32_t vk_to_gen_cullmode[] = {
  88    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
  89    [VK_CULL_MODE_FRONT_BIT]                     = CULLMODE_FRONT,
  90    [VK_CULL_MODE_BACK_BIT]                      = CULLMODE_BACK,
  91    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
  92 };
  93
  94 static const uint32_t vk_to_gen_fillmode[] = {
  95    [VK_POLYGON_MODE_FILL]                       = RASTER_SOLID,
  96    [VK_POLYGON_MODE_LINE]                       = RASTER_WIREFRAME,
  97    [VK_POLYGON_MODE_POINT]                      = RASTER_POINT,
  98 };
  99
 100 static const uint32_t vk_to_gen_front_face[] = {
 101    [VK_FRONT_FACE_COUNTER_CLOCKWISE]            = 1,
 102    [VK_FRONT_FACE_CLOCKWISE]                    = 0
 103 };
 104
 105 static void
 106 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 107                    const VkPipelineRasterizationStateCreateInfo *info,
 108                    const struct anv_graphics_pipeline_create_info *extra)
 109 {
 110    struct GEN7_3DSTATE_SF sf = {
 111       GEN7_3DSTATE_SF_header,
 112
 113       /* FIXME: Get this from pass info */
 114       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 115
 116       /* LegacyGlobalDepthBiasEnable */
 117
 118       .StatisticsEnable                         = true,
 119       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 120       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 121       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 122       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 123       /* bool                                         AntiAliasingEnable; */
 124
 125       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 126
 127       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 128       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 129
 130       /* uint32_t                                     MultisampleRasterizationMode; */
 131       /* bool                                         LastPixelEnable; */
 132
 133       .TriangleStripListProvokingVertexSelect   = 0,
 134       .LineStripListProvokingVertexSelect       = 0,
 135       .TriangleFanProvokingVertexSelect         = 0,
 136
 137       /* uint32_t                                     AALineDistanceMode; */
 138       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 139       .UsePointWidthState                       = !pipeline->writes_point_size,
 140       .PointWidth                               = 1.0,
 141    };
 142
 143    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 144 }
 145
 146 static const uint32_t vk_to_gen_compare_op[] = {
 147    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 148    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 149    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 150    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 151    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 152    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 153    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 154    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 155 };
 156
 157 static const uint32_t vk_to_gen_stencil_op[] = {
 158    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 159    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 160    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 161    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 162    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 163    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 164    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 165    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 166 };
 167
 168 static const uint32_t vk_to_gen_blend_op[] = {
 169    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 170    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 171    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 172    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 173    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 174 };
 175
 176 static const uint32_t vk_to_gen_logic_op[] = {
 177    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 178    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 179    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 180    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 181    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 182    [VK_LOGIC_OP_NO_OP]                          = LOGICOP_NOOP,
 183    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 184    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 185    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 186    [VK_LOGIC_OP_EQUIVALENT]                     = LOGICOP_EQUIV,
 187    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 188    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 189    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 190    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 191    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 192    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 193 };
 194
 195 static const uint32_t vk_to_gen_blend[] = {
 196    [VK_BLEND_FACTOR_ZERO]                       = BLENDFACTOR_ZERO,
 197    [VK_BLEND_FACTOR_ONE]                        = BLENDFACTOR_ONE,
 198    [VK_BLEND_FACTOR_SRC_COLOR]                  = BLENDFACTOR_SRC_COLOR,
 199    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]        = BLENDFACTOR_INV_SRC_COLOR,
 200    [VK_BLEND_FACTOR_DST_COLOR]                  = BLENDFACTOR_DST_COLOR,
 201    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]        = BLENDFACTOR_INV_DST_COLOR,
 202    [VK_BLEND_FACTOR_SRC_ALPHA]                  = BLENDFACTOR_SRC_ALPHA,
 203    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]        = BLENDFACTOR_INV_SRC_ALPHA,
 204    [VK_BLEND_FACTOR_DST_ALPHA]                  = BLENDFACTOR_DST_ALPHA,
 205    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]        = BLENDFACTOR_INV_DST_ALPHA,
 206    [VK_BLEND_FACTOR_CONSTANT_COLOR]             = BLENDFACTOR_CONST_COLOR,
 207    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]   = BLENDFACTOR_INV_CONST_COLOR,
 208    [VK_BLEND_FACTOR_CONSTANT_ALPHA]             = BLENDFACTOR_CONST_ALPHA,
 209    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]   = BLENDFACTOR_INV_CONST_ALPHA,
 210    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]         = BLENDFACTOR_SRC_ALPHA_SATURATE,
 211    [VK_BLEND_FACTOR_SRC1_COLOR]                 = BLENDFACTOR_SRC1_COLOR,
 212    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]       = BLENDFACTOR_INV_SRC1_COLOR,
 213    [VK_BLEND_FACTOR_SRC1_ALPHA]                 = BLENDFACTOR_SRC1_ALPHA,
 214    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]       = BLENDFACTOR_INV_SRC1_ALPHA,
 215 };
 216
 217 static void
 218 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 219                    const VkPipelineDepthStencilStateCreateInfo *info)
 220 {
 221    if (info == NULL) {
 222       /* We're going to OR this together with the dynamic state.  We need
 223        * to make sure it's initialized to something useful.
 224        */
 225       memset(pipeline->gen7.depth_stencil_state, 0,
 226              sizeof(pipeline->gen7.depth_stencil_state));
 227       return;
 228    }
 229
 230    struct GEN7_DEPTH_STENCIL_STATE state = {
 231       .DepthTestEnable = info->depthTestEnable,
 232       .DepthBufferWriteEnable = info->depthWriteEnable,
 233       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 234       .DoubleSidedStencilEnable = true,
 235
 236       .StencilTestEnable = info->stencilTestEnable,
 237       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 238       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 239       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 240       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 241
 242       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 243       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 244       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 245       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 246    };
 247
 248    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 249 }
 250
 251 static void
 252 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 253                    const VkPipelineColorBlendStateCreateInfo *info,
 254                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 255 {
 256    struct anv_device *device = pipeline->device;
 257
 258    if (info->pAttachments == NULL) {
 259       pipeline->blend_state =
 260          anv_state_pool_emit(&device->dynamic_state_pool,
 261             GEN7_BLEND_STATE, 64,
 262             .ColorBufferBlendEnable = false,
 263             .WriteDisableAlpha = false,
 264             .WriteDisableRed = false,
 265             .WriteDisableGreen = false,
 266             .WriteDisableBlue = false);
 267    } else {
 268       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 269        * can't implement this.
 270        */
 271       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 272       pipeline->blend_state =
 273          anv_state_pool_emit(&device->dynamic_state_pool,
 274             GEN7_BLEND_STATE, 64,
 275
 276             .ColorBufferBlendEnable = a->blendEnable,
 277             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 278             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 279
 280             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 281             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 282
 283             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 284             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 285             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 286             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 287
 288 #     if 0
 289             bool                                AlphaToOneEnable;
 290             bool                                AlphaToCoverageDitherEnable;
 291 #     endif
 292
 293             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 294             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 295             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 296             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 297
 298             .LogicOpEnable = info->logicOpEnable,
 299             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 300
 301 #     if 0
 302             bool                                AlphaTestEnable;
 303             uint32_t                            AlphaTestFunction;
 304             bool                                ColorDitherEnable;
 305             uint32_t                            XDitherOffset;
 306             uint32_t                            YDitherOffset;
 307             uint32_t                            ColorClampRange;
 308             bool                                PreBlendColorClampEnable;
 309             bool                                PostBlendColorClampEnable;
 310 #     endif
 311             );
 312     }
 313
 314    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 315                   .BlendStatePointer = pipeline->blend_state.offset);
 316 }
 317
 318 static inline uint32_t
 319 scratch_space(const struct brw_stage_prog_data *prog_data)
 320 {
 321    return ffs(prog_data->total_scratch / 1024);
 322 }
 323
 324 GENX_FUNC(GEN7, GEN75) VkResult
 325 genX(graphics_pipeline_create)(
 326     VkDevice                                    _device,
 327     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 328     const struct anv_graphics_pipeline_create_info *extra,
 329     const VkAllocationCallbacks*                pAllocator,
 330     VkPipeline*                                 pPipeline)
 331 {
 332    ANV_FROM_HANDLE(anv_device, device, _device);
 333    struct anv_pipeline *pipeline;
 334    VkResult result;
 335
 336    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 337
 338    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 339                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 340    if (pipeline == NULL)
 341       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 342
 343    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 344    if (result != VK_SUCCESS) {
 345       anv_free2(&device->alloc, pAllocator, pipeline);
 346       return result;
 347    }
 348
 349    assert(pCreateInfo->pVertexInputState);
 350    gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 351
 352    assert(pCreateInfo->pRasterizationState);
 353    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 354
 355    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 356
 357    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 358                                 pCreateInfo->pMultisampleState);
 359
 360    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 361                    .StatisticsEnable = true);
 362    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 363    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 364    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 365    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 366
 367    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 368     *
 369     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 370     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 371     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 372     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 373     *    needs to be sent before any combination of VS associated 3DSTATE."
 374     */
 375    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 376                   .DepthStallEnable = true,
 377                   .PostSyncOperation = WriteImmediateData,
 378                   .Address = { &device->workaround_bo, 0 });
 379
 380    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 381                   .ConstantBufferOffset = 0,
 382                   .ConstantBufferSize = 4);
 383    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 384                   .ConstantBufferOffset = 4,
 385                   .ConstantBufferSize = 4);
 386    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 387                   .ConstantBufferOffset = 8,
 388                   .ConstantBufferSize = 4);
 389
 390    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 391
 392    const VkPipelineRasterizationStateCreateInfo *rs_info =
 393       pCreateInfo->pRasterizationState;
 394
 395    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 396       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 397       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 398       .ClipEnable                               = true,
 399       .APIMode                                  = APIMODE_OGL,
 400       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 401       .ClipMode                                 = CLIPMODE_NORMAL,
 402       .TriangleStripListProvokingVertexSelect   = 0,
 403       .LineStripListProvokingVertexSelect       = 0,
 404       .TriangleFanProvokingVertexSelect         = 0,
 405       .MinimumPointWidth                        = 0.125,
 406       .MaximumPointWidth                        = 255.875);
 407
 408    uint32_t samples = 1;
 409    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 410
 411    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 412       .PixelLocation                            = PIXLOC_CENTER,
 413       .NumberofMultisamples                     = log2_samples);
 414
 415    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 416       .SampleMask                               = 0xff);
 417
 418    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 419       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 420       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 421       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 422
 423    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 424       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 425       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 426       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 427
 428    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 429       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 430       .HSURBEntryAllocationSize                 = 0,
 431       .HSNumberofURBEntries                     = 0);
 432
 433    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 434       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 435       .DSURBEntryAllocationSize                 = 0,
 436       .DSNumberofURBEntries                     = 0);
 437
 438    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 439    /* The last geometry producing stage will set urb_offset and urb_length,
 440     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 441    uint32_t urb_offset = 1;
 442    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 443
 444 #if 0
 445    /* From gen7_vs_state.c */
 446
 447    /**
 448     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 449     * Geometry > Geometry Shader > State:
 450     *
 451     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 452     *     whole fixed function pipeline when the GS enable changes value in
 453     *     the 3DSTATE_GS."
 454     *
 455     * The hardware architects have clarified that in this context "flush the
 456     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 457     * Stall" bit set.
 458     */
 459    if (!brw->is_haswell && !brw->is_baytrail)
 460       gen7_emit_vs_workaround_flush(brw);
 461 #endif
 462
 463    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 464       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 465    else
 466       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 467          .KernelStartPointer                    = pipeline->vs_vec4,
 468          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 469          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 470
 471          .DispatchGRFStartRegisterforURBData    =
 472             vue_prog_data->base.dispatch_grf_start_reg,
 473          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 474          .VertexURBEntryReadOffset              = 0,
 475
 476          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 477          .StatisticsEnable                      = true,
 478          .VSFunctionEnable                      = true);
 479
 480    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 481
 482    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 483       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 484    } else {
 485       urb_offset = 1;
 486       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 487
 488       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 489          .KernelStartPointer                    = pipeline->gs_kernel,
 490          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 491          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 492
 493          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 494          .OutputTopology                        = gs_prog_data->output_topology,
 495          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 496          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 497          .DispatchGRFStartRegisterforURBData    =
 498             gs_prog_data->base.base.dispatch_grf_start_reg,
 499
 500          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 501          /* This in the next dword on HSW. */
 502          .ControlDataFormat                     = gs_prog_data->control_data_format,
 503          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 504          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 505          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 506          .GSStatisticsEnable                    = true,
 507          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 508 #     if (ANV_IS_HASWELL)
 509          .ReorderMode                           = REORDER_TRAILING,
 510 #     else
 511          .ReorderEnable                         = true,
 512 #     endif
 513          .GSEnable                              = true);
 514    }
 515
 516    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 517    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 518        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 519       anv_finishme("two-sided color needs sbe swizzling setup");
 520    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 521       anv_finishme("primitive_id needs sbe swizzling setup");
 522
 523    /* FIXME: generated header doesn't emit attr swizzle fields */
 524    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 525       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 526       .VertexURBEntryReadLength                 = urb_length,
 527       .VertexURBEntryReadOffset                 = urb_offset,
 528       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 529
 530    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 531       .KernelStartPointer0                      = pipeline->ps_ksp0,
 532       .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 533       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 534
 535       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 536       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 537       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 538       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 539
 540       .RenderTargetFastClearEnable              = false,
 541       .DualSourceBlendEnable                    = false,
 542       .RenderTargetResolveEnable                = false,
 543
 544       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 545          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 546
 547       ._32PixelDispatchEnable                   = false,
 548       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 549       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 550
 551       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 552       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 553       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 554
 555 #if 0
 556    /* Haswell requires the sample mask to be set in this packet as well as
 557     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 558    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 559 #endif
 560
 561       .KernelStartPointer1                      = 0,
 562       .KernelStartPointer2                      = pipeline->ps_ksp2);
 563
 564    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 565    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 566       .StatisticsEnable                         = true,
 567       .ThreadDispatchEnable                     = true,
 568       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 569       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 570       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 571       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 572       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 573       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 574
 575    *pPipeline = anv_pipeline_to_handle(pipeline);
 576
 577    return VK_SUCCESS;
 578 }
 579
 580 GENX_FUNC(GEN7, GEN75) VkResult
 581 genX(compute_pipeline_create)(
 582     VkDevice                                    _device,
 583     const VkComputePipelineCreateInfo*          pCreateInfo,
 584     const VkAllocationCallbacks*                pAllocator,
 585     VkPipeline*                                 pPipeline)
 586 {
 587    anv_finishme("primitive_id needs sbe swizzling setup");
 588    abort();
 589 }