src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_vertex_input(struct anv_pipeline *pipeline,
  39                   const VkPipelineVertexInputStateCreateInfo *info,
  40                   const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    uint32_t elements;
  43    if (extra && extra->disable_vs) {
  44       /* If the VS is disabled, just assume the user knows what they're
  45        * doing and apply the layout blindly.  This can only come from
  46        * meta, so this *should* be safe.
  47        */
  48       elements = 0;
  49       for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
  50          elements |= (1 << info->pVertexAttributeDescriptions[i].location);
  51    } else {
  52       /* Pull inputs_read out of the VS prog data */
  53       uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
  54       assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
  55       elements = inputs_read >> VERT_ATTRIB_GENERIC0;
  56    }
  57
  58    uint32_t vb_count = __builtin_popcount(elements);
  59
  60    if (pipeline->vs_prog_data.uses_vertexid ||
  61        pipeline->vs_prog_data.uses_instanceid)
  62       vb_count++;
  63
  64    if (vb_count == 0)
  65       return;
  66
  67    const uint32_t num_dwords = 1 + vb_count * 2;
  68
  69    uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
  70                                  GEN7_3DSTATE_VERTEX_ELEMENTS);
  71    memset(p + 1, 0, (num_dwords - 1) * 4);
  72
  73    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  74       const VkVertexInputAttributeDescription *desc =
  75          &info->pVertexAttributeDescriptions[i];
  76       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  77
  78       assert(desc->binding < 32);
  79
  80       if ((elements & (1 << desc->location)) == 0)
  81          continue; /* Binding unused */
  82
  83       uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
  84
  85       struct GEN7_VERTEX_ELEMENT_STATE element = {
  86          .VertexBufferIndex = desc->binding,
  87          .Valid = true,
  88          .SourceElementFormat = format->surface_format,
  89          .EdgeFlagEnable = false,
  90          .SourceElementOffset = desc->offset,
  91          .Component0Control = VFCOMP_STORE_SRC,
  92          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  93          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  94          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  95       };
  96       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
  97    }
  98
  99    if (pipeline->vs_prog_data.uses_vertexid ||
 100        pipeline->vs_prog_data.uses_instanceid) {
 101       struct GEN7_VERTEX_ELEMENT_STATE element = {
 102          .Valid = true,
 103          /* FIXME: Do we need to provide the base vertex as component 0 here
 104           * to support the correct base vertex ID? */
 105          .Component0Control = VFCOMP_STORE_0,
 106          .Component1Control = VFCOMP_STORE_0,
 107          .Component2Control = VFCOMP_STORE_VID,
 108          .Component3Control = VFCOMP_STORE_IID
 109       };
 110       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
 111    }
 112 }
 113
 114 static void
 115 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 116                    const VkPipelineRasterizationStateCreateInfo *info,
 117                    const struct anv_graphics_pipeline_create_info *extra)
 118 {
 119    struct GEN7_3DSTATE_SF sf = {
 120       GEN7_3DSTATE_SF_header,
 121
 122       /* FIXME: Get this from pass info */
 123       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 124
 125       /* LegacyGlobalDepthBiasEnable */
 126
 127       .StatisticsEnable                         = true,
 128       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 129       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 130       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 131       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 132       /* bool                                         AntiAliasingEnable; */
 133
 134       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 135
 136       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 137       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 138
 139       /* uint32_t                                     MultisampleRasterizationMode; */
 140       /* bool                                         LastPixelEnable; */
 141
 142       .TriangleStripListProvokingVertexSelect   = 0,
 143       .LineStripListProvokingVertexSelect       = 0,
 144       .TriangleFanProvokingVertexSelect         = 0,
 145
 146       /* uint32_t                                     AALineDistanceMode; */
 147       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 148       .UsePointWidthState                       = !pipeline->writes_point_size,
 149       .PointWidth                               = 1.0,
 150    };
 151
 152    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 153 }
 154
 155 static void
 156 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 157                    const VkPipelineDepthStencilStateCreateInfo *info)
 158 {
 159    if (info == NULL) {
 160       /* We're going to OR this together with the dynamic state.  We need
 161        * to make sure it's initialized to something useful.
 162        */
 163       memset(pipeline->gen7.depth_stencil_state, 0,
 164              sizeof(pipeline->gen7.depth_stencil_state));
 165       return;
 166    }
 167
 168    struct GEN7_DEPTH_STENCIL_STATE state = {
 169       .DepthTestEnable = info->depthTestEnable,
 170       .DepthBufferWriteEnable = info->depthWriteEnable,
 171       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 172       .DoubleSidedStencilEnable = true,
 173
 174       .StencilTestEnable = info->stencilTestEnable,
 175       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 176       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 177       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 178       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 179
 180       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 181       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 182       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 183       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 184    };
 185
 186    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 187 }
 188
 189 static void
 190 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 191                    const VkPipelineColorBlendStateCreateInfo *info,
 192                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 193 {
 194    struct anv_device *device = pipeline->device;
 195
 196    if (info->pAttachments == NULL) {
 197       pipeline->blend_state =
 198          anv_state_pool_emit(&device->dynamic_state_pool,
 199             GEN7_BLEND_STATE, 64,
 200             .ColorBufferBlendEnable = false,
 201             .WriteDisableAlpha = false,
 202             .WriteDisableRed = false,
 203             .WriteDisableGreen = false,
 204             .WriteDisableBlue = false);
 205    } else {
 206       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 207        * can't implement this.
 208        */
 209       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 210       pipeline->blend_state =
 211          anv_state_pool_emit(&device->dynamic_state_pool,
 212             GEN7_BLEND_STATE, 64,
 213
 214             .ColorBufferBlendEnable = a->blendEnable,
 215             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 216             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 217
 218             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 219             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 220
 221             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 222             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 223             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 224             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 225
 226 #     if 0
 227             bool                                AlphaToOneEnable;
 228             bool                                AlphaToCoverageDitherEnable;
 229 #     endif
 230
 231             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 232             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 233             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 234             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 235
 236             .LogicOpEnable = info->logicOpEnable,
 237             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 238
 239 #     if 0
 240             bool                                AlphaTestEnable;
 241             uint32_t                            AlphaTestFunction;
 242             bool                                ColorDitherEnable;
 243             uint32_t                            XDitherOffset;
 244             uint32_t                            YDitherOffset;
 245             uint32_t                            ColorClampRange;
 246             bool                                PreBlendColorClampEnable;
 247             bool                                PostBlendColorClampEnable;
 248 #     endif
 249             );
 250     }
 251
 252    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 253                   .BlendStatePointer = pipeline->blend_state.offset);
 254 }
 255
 256 static inline uint32_t
 257 scratch_space(const struct brw_stage_prog_data *prog_data)
 258 {
 259    return ffs(prog_data->total_scratch / 1024);
 260 }
 261
 262 GENX_FUNC(GEN7, GEN75) VkResult
 263 genX(graphics_pipeline_create)(
 264     VkDevice                                    _device,
 265     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 266     const struct anv_graphics_pipeline_create_info *extra,
 267     const VkAllocationCallbacks*                pAllocator,
 268     VkPipeline*                                 pPipeline)
 269 {
 270    ANV_FROM_HANDLE(anv_device, device, _device);
 271    struct anv_pipeline *pipeline;
 272    VkResult result;
 273
 274    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 275
 276    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 277                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 278    if (pipeline == NULL)
 279       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 280
 281    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 282    if (result != VK_SUCCESS) {
 283       anv_free2(&device->alloc, pAllocator, pipeline);
 284       return result;
 285    }
 286
 287    assert(pCreateInfo->pVertexInputState);
 288    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 289
 290    assert(pCreateInfo->pRasterizationState);
 291    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 292
 293    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 294
 295    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 296                                 pCreateInfo->pMultisampleState);
 297
 298    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 299                    .StatisticsEnable = true);
 300    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 301    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 302    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 303    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 304
 305    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 306     *
 307     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 308     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 309     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 310     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 311     *    needs to be sent before any combination of VS associated 3DSTATE."
 312     */
 313    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 314                   .DepthStallEnable = true,
 315                   .PostSyncOperation = WriteImmediateData,
 316                   .Address = { &device->workaround_bo, 0 });
 317
 318    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 319                   .ConstantBufferOffset = 0,
 320                   .ConstantBufferSize = 4);
 321    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 322                   .ConstantBufferOffset = 4,
 323                   .ConstantBufferSize = 4);
 324    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 325                   .ConstantBufferOffset = 8,
 326                   .ConstantBufferSize = 4);
 327
 328    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 329
 330    const VkPipelineRasterizationStateCreateInfo *rs_info =
 331       pCreateInfo->pRasterizationState;
 332
 333    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 334       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 335       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 336       .ClipEnable                               = true,
 337       .APIMode                                  = APIMODE_OGL,
 338       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 339       .ClipMode                                 = CLIPMODE_NORMAL,
 340       .TriangleStripListProvokingVertexSelect   = 0,
 341       .LineStripListProvokingVertexSelect       = 0,
 342       .TriangleFanProvokingVertexSelect         = 0,
 343       .MinimumPointWidth                        = 0.125,
 344       .MaximumPointWidth                        = 255.875);
 345
 346    uint32_t samples = 1;
 347    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 348
 349    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 350       .PixelLocation                            = PIXLOC_CENTER,
 351       .NumberofMultisamples                     = log2_samples);
 352
 353    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 354       .SampleMask                               = 0xff);
 355
 356    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 357       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 358       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 359       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 360
 361    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 362       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 363       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 364       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 365
 366    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 367       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 368       .HSURBEntryAllocationSize                 = 0,
 369       .HSNumberofURBEntries                     = 0);
 370
 371    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 372       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 373       .DSURBEntryAllocationSize                 = 0,
 374       .DSNumberofURBEntries                     = 0);
 375
 376    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 377    /* The last geometry producing stage will set urb_offset and urb_length,
 378     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 379    uint32_t urb_offset = 1;
 380    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 381
 382 #if 0
 383    /* From gen7_vs_state.c */
 384
 385    /**
 386     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 387     * Geometry > Geometry Shader > State:
 388     *
 389     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 390     *     whole fixed function pipeline when the GS enable changes value in
 391     *     the 3DSTATE_GS."
 392     *
 393     * The hardware architects have clarified that in this context "flush the
 394     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 395     * Stall" bit set.
 396     */
 397    if (!brw->is_haswell && !brw->is_baytrail)
 398       gen7_emit_vs_workaround_flush(brw);
 399 #endif
 400
 401    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 402       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 403    else
 404       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 405          .KernelStartPointer                    = pipeline->vs_vec4,
 406          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 407          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 408
 409          .DispatchGRFStartRegisterforURBData    =
 410             vue_prog_data->base.dispatch_grf_start_reg,
 411          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 412          .VertexURBEntryReadOffset              = 0,
 413
 414          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 415          .StatisticsEnable                      = true,
 416          .VSFunctionEnable                      = true);
 417
 418    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 419
 420    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 421       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 422    } else {
 423       urb_offset = 1;
 424       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 425
 426       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 427          .KernelStartPointer                    = pipeline->gs_kernel,
 428          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 429          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 430
 431          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 432          .OutputTopology                        = gs_prog_data->output_topology,
 433          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 434          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 435          .DispatchGRFStartRegisterforURBData    =
 436             gs_prog_data->base.base.dispatch_grf_start_reg,
 437
 438          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 439          /* This in the next dword on HSW. */
 440          .ControlDataFormat                     = gs_prog_data->control_data_format,
 441          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 442          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 443          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 444          .GSStatisticsEnable                    = true,
 445          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 446 #     if (ANV_IS_HASWELL)
 447          .ReorderMode                           = REORDER_TRAILING,
 448 #     else
 449          .ReorderEnable                         = true,
 450 #     endif
 451          .GSEnable                              = true);
 452    }
 453
 454    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 455    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 456        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 457       anv_finishme("two-sided color needs sbe swizzling setup");
 458    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 459       anv_finishme("primitive_id needs sbe swizzling setup");
 460
 461    /* FIXME: generated header doesn't emit attr swizzle fields */
 462    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 463       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 464       .VertexURBEntryReadLength                 = urb_length,
 465       .VertexURBEntryReadOffset                 = urb_offset,
 466       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 467
 468    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 469       .KernelStartPointer0                      = pipeline->ps_ksp0,
 470       .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 471       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 472
 473       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 474       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 475       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 476       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 477
 478       .RenderTargetFastClearEnable              = false,
 479       .DualSourceBlendEnable                    = false,
 480       .RenderTargetResolveEnable                = false,
 481
 482       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 483          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 484
 485       ._32PixelDispatchEnable                   = false,
 486       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 487       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 488
 489       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 490       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 491       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 492
 493 #if 0
 494    /* Haswell requires the sample mask to be set in this packet as well as
 495     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 496    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 497 #endif
 498
 499       .KernelStartPointer1                      = 0,
 500       .KernelStartPointer2                      = pipeline->ps_ksp2);
 501
 502    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 503    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 504       .StatisticsEnable                         = true,
 505       .ThreadDispatchEnable                     = true,
 506       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 507       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 508       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 509       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 510       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 511       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 512
 513    *pPipeline = anv_pipeline_to_handle(pipeline);
 514
 515    return VK_SUCCESS;
 516 }
 517
 518 GENX_FUNC(GEN7, GEN75) VkResult
 519 genX(compute_pipeline_create)(
 520     VkDevice                                    _device,
 521     const VkComputePipelineCreateInfo*          pCreateInfo,
 522     const VkAllocationCallbacks*                pAllocator,
 523     VkPipeline*                                 pPipeline)
 524 {
 525    anv_finishme("primitive_id needs sbe swizzling setup");
 526    abort();
 527 }