src/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 static void
  36 gen7_emit_vertex_input(struct anv_pipeline *pipeline,
  37                        const VkPipelineVertexInputStateCreateInfo *info)
  38 {
  39    const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
  40       pipeline->vs_prog_data.uses_instanceid;
  41    const uint32_t element_count =
  42       info->vertexAttributeDescriptionCount + (sgvs ? 1 : 0);
  43    const uint32_t num_dwords = 1 + element_count * 2;
  44    uint32_t *p;
  45
  46    if (info->vertexAttributeDescriptionCount == 0 && !sgvs)
  47       return;
  48
  49    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  50                        GEN7_3DSTATE_VERTEX_ELEMENTS);
  51
  52    for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
  53       const VkVertexInputAttributeDescription *desc =
  54          &info->pVertexAttributeDescriptions[i];
  55       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  56
  57       struct GEN7_VERTEX_ELEMENT_STATE element = {
  58          .VertexBufferIndex = desc->binding,
  59          .Valid = true,
  60          .SourceElementFormat = format->surface_format,
  61          .EdgeFlagEnable = false,
  62          .SourceElementOffset = desc->offset,
  63          .Component0Control = VFCOMP_STORE_SRC,
  64          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  65          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  66          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  67       };
  68       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  69    }
  70
  71    if (sgvs) {
  72       struct GEN7_VERTEX_ELEMENT_STATE element = {
  73          .Valid = true,
  74          /* FIXME: Do we need to provide the base vertex as component 0 here
  75           * to support the correct base vertex ID? */
  76          .Component0Control = VFCOMP_STORE_0,
  77          .Component1Control = VFCOMP_STORE_0,
  78          .Component2Control = VFCOMP_STORE_VID,
  79          .Component3Control = VFCOMP_STORE_IID
  80       };
  81       GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->vertexAttributeDescriptionCount * 2], &element);
  82    }
  83 }
  84
  85 static const uint32_t vk_to_gen_cullmode[] = {
  86    [VK_CULL_MODE_NONE]                          = CULLMODE_NONE,
  87    [VK_CULL_MODE_FRONT_BIT]                     = CULLMODE_FRONT,
  88    [VK_CULL_MODE_BACK_BIT]                      = CULLMODE_BACK,
  89    [VK_CULL_MODE_FRONT_AND_BACK]                = CULLMODE_BOTH
  90 };
  91
  92 static const uint32_t vk_to_gen_fillmode[] = {
  93    [VK_POLYGON_MODE_FILL]                       = RASTER_SOLID,
  94    [VK_POLYGON_MODE_LINE]                       = RASTER_WIREFRAME,
  95    [VK_POLYGON_MODE_POINT]                      = RASTER_POINT,
  96 };
  97
  98 static const uint32_t vk_to_gen_front_face[] = {
  99    [VK_FRONT_FACE_COUNTER_CLOCKWISE]            = 1,
 100    [VK_FRONT_FACE_CLOCKWISE]                    = 0
 101 };
 102
 103 static void
 104 gen7_emit_rs_state(struct anv_pipeline *pipeline,
 105                    const VkPipelineRasterizationStateCreateInfo *info,
 106                    const struct anv_graphics_pipeline_create_info *extra)
 107 {
 108    struct GEN7_3DSTATE_SF sf = {
 109       GEN7_3DSTATE_SF_header,
 110
 111       /* FIXME: Get this from pass info */
 112       .DepthBufferSurfaceFormat                 = D24_UNORM_X8_UINT,
 113
 114       /* LegacyGlobalDepthBiasEnable */
 115
 116       .StatisticsEnable                         = true,
 117       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
 118       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
 119       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
 120       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
 121       /* bool                                         AntiAliasingEnable; */
 122
 123       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
 124
 125       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
 126       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
 127
 128       /* uint32_t                                     MultisampleRasterizationMode; */
 129       /* bool                                         LastPixelEnable; */
 130
 131       .TriangleStripListProvokingVertexSelect   = 0,
 132       .LineStripListProvokingVertexSelect       = 0,
 133       .TriangleFanProvokingVertexSelect         = 0,
 134
 135       /* uint32_t                                     AALineDistanceMode; */
 136       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
 137       .UsePointWidthState                       = !pipeline->writes_point_size,
 138       .PointWidth                               = 1.0,
 139    };
 140
 141    GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
 142 }
 143
 144 static const uint32_t vk_to_gen_compare_op[] = {
 145    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
 146    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
 147    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
 148    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
 149    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
 150    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
 151    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
 152    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
 153 };
 154
 155 static const uint32_t vk_to_gen_stencil_op[] = {
 156    [VK_STENCIL_OP_KEEP]                         = STENCILOP_KEEP,
 157    [VK_STENCIL_OP_ZERO]                         = STENCILOP_ZERO,
 158    [VK_STENCIL_OP_REPLACE]                      = STENCILOP_REPLACE,
 159    [VK_STENCIL_OP_INCREMENT_AND_CLAMP]          = STENCILOP_INCRSAT,
 160    [VK_STENCIL_OP_DECREMENT_AND_CLAMP]          = STENCILOP_DECRSAT,
 161    [VK_STENCIL_OP_INVERT]                       = STENCILOP_INVERT,
 162    [VK_STENCIL_OP_INCREMENT_AND_WRAP]           = STENCILOP_INCR,
 163    [VK_STENCIL_OP_DECREMENT_AND_WRAP]           = STENCILOP_DECR,
 164 };
 165
 166 static const uint32_t vk_to_gen_blend_op[] = {
 167    [VK_BLEND_OP_ADD]                            = BLENDFUNCTION_ADD,
 168    [VK_BLEND_OP_SUBTRACT]                       = BLENDFUNCTION_SUBTRACT,
 169    [VK_BLEND_OP_REVERSE_SUBTRACT]               = BLENDFUNCTION_REVERSE_SUBTRACT,
 170    [VK_BLEND_OP_MIN]                            = BLENDFUNCTION_MIN,
 171    [VK_BLEND_OP_MAX]                            = BLENDFUNCTION_MAX,
 172 };
 173
 174 static const uint32_t vk_to_gen_logic_op[] = {
 175    [VK_LOGIC_OP_COPY]                           = LOGICOP_COPY,
 176    [VK_LOGIC_OP_CLEAR]                          = LOGICOP_CLEAR,
 177    [VK_LOGIC_OP_AND]                            = LOGICOP_AND,
 178    [VK_LOGIC_OP_AND_REVERSE]                    = LOGICOP_AND_REVERSE,
 179    [VK_LOGIC_OP_AND_INVERTED]                   = LOGICOP_AND_INVERTED,
 180    [VK_LOGIC_OP_NO_OP]                          = LOGICOP_NOOP,
 181    [VK_LOGIC_OP_XOR]                            = LOGICOP_XOR,
 182    [VK_LOGIC_OP_OR]                             = LOGICOP_OR,
 183    [VK_LOGIC_OP_NOR]                            = LOGICOP_NOR,
 184    [VK_LOGIC_OP_EQUIVALENT]                     = LOGICOP_EQUIV,
 185    [VK_LOGIC_OP_INVERT]                         = LOGICOP_INVERT,
 186    [VK_LOGIC_OP_OR_REVERSE]                     = LOGICOP_OR_REVERSE,
 187    [VK_LOGIC_OP_COPY_INVERTED]                  = LOGICOP_COPY_INVERTED,
 188    [VK_LOGIC_OP_OR_INVERTED]                    = LOGICOP_OR_INVERTED,
 189    [VK_LOGIC_OP_NAND]                           = LOGICOP_NAND,
 190    [VK_LOGIC_OP_SET]                            = LOGICOP_SET,
 191 };
 192
 193 static const uint32_t vk_to_gen_blend[] = {
 194    [VK_BLEND_FACTOR_ZERO]                       = BLENDFACTOR_ZERO,
 195    [VK_BLEND_FACTOR_ONE]                        = BLENDFACTOR_ONE,
 196    [VK_BLEND_FACTOR_SRC_COLOR]                  = BLENDFACTOR_SRC_COLOR,
 197    [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR]        = BLENDFACTOR_INV_SRC_COLOR,
 198    [VK_BLEND_FACTOR_DST_COLOR]                  = BLENDFACTOR_DST_COLOR,
 199    [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR]        = BLENDFACTOR_INV_DST_COLOR,
 200    [VK_BLEND_FACTOR_SRC_ALPHA]                  = BLENDFACTOR_SRC_ALPHA,
 201    [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA]        = BLENDFACTOR_INV_SRC_ALPHA,
 202    [VK_BLEND_FACTOR_DST_ALPHA]                  = BLENDFACTOR_DST_ALPHA,
 203    [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA]        = BLENDFACTOR_INV_DST_ALPHA,
 204    [VK_BLEND_FACTOR_CONSTANT_COLOR]             = BLENDFACTOR_CONST_COLOR,
 205    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]   = BLENDFACTOR_INV_CONST_COLOR,
 206    [VK_BLEND_FACTOR_CONSTANT_ALPHA]             = BLENDFACTOR_CONST_ALPHA,
 207    [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]   = BLENDFACTOR_INV_CONST_ALPHA,
 208    [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE]         = BLENDFACTOR_SRC_ALPHA_SATURATE,
 209    [VK_BLEND_FACTOR_SRC1_COLOR]                 = BLENDFACTOR_SRC1_COLOR,
 210    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR]       = BLENDFACTOR_INV_SRC1_COLOR,
 211    [VK_BLEND_FACTOR_SRC1_ALPHA]                 = BLENDFACTOR_SRC1_ALPHA,
 212    [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA]       = BLENDFACTOR_INV_SRC1_ALPHA,
 213 };
 214
 215 static void
 216 gen7_emit_ds_state(struct anv_pipeline *pipeline,
 217                    const VkPipelineDepthStencilStateCreateInfo *info)
 218 {
 219    if (info == NULL) {
 220       /* We're going to OR this together with the dynamic state.  We need
 221        * to make sure it's initialized to something useful.
 222        */
 223       memset(pipeline->gen7.depth_stencil_state, 0,
 224              sizeof(pipeline->gen7.depth_stencil_state));
 225       return;
 226    }
 227
 228    struct GEN7_DEPTH_STENCIL_STATE state = {
 229       .DepthTestEnable = info->depthTestEnable,
 230       .DepthBufferWriteEnable = info->depthWriteEnable,
 231       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 232       .DoubleSidedStencilEnable = true,
 233
 234       .StencilTestEnable = info->stencilTestEnable,
 235       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 236       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 237       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 238       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 239
 240       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 241       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 242       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 243       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 244    };
 245
 246    GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
 247 }
 248
 249 static void
 250 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 251                    const VkPipelineColorBlendStateCreateInfo *info,
 252                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 253 {
 254    struct anv_device *device = pipeline->device;
 255
 256    if (info->pAttachments == NULL) {
 257       pipeline->blend_state =
 258          anv_state_pool_emit(&device->dynamic_state_pool,
 259             GEN7_BLEND_STATE, 64,
 260             .ColorBufferBlendEnable = false,
 261             .WriteDisableAlpha = false,
 262             .WriteDisableRed = false,
 263             .WriteDisableGreen = false,
 264             .WriteDisableBlue = false);
 265    } else {
 266       /* FIXME-GEN7: All render targets share blend state settings on gen7, we
 267        * can't implement this.
 268        */
 269       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 270       pipeline->blend_state =
 271          anv_state_pool_emit(&device->dynamic_state_pool,
 272             GEN7_BLEND_STATE, 64,
 273
 274             .ColorBufferBlendEnable = a->blendEnable,
 275             .IndependentAlphaBlendEnable = true, /* FIXME: yes? */
 276             .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 277
 278             .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 279             .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 280
 281             .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 282             .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 283             .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 284             .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 285
 286 #     if 0
 287             bool                                AlphaToOneEnable;
 288             bool                                AlphaToCoverageDitherEnable;
 289 #     endif
 290
 291             .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 292             .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 293             .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 294             .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 295
 296             .LogicOpEnable = info->logicOpEnable,
 297             .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 298
 299 #     if 0
 300             bool                                AlphaTestEnable;
 301             uint32_t                            AlphaTestFunction;
 302             bool                                ColorDitherEnable;
 303             uint32_t                            XDitherOffset;
 304             uint32_t                            YDitherOffset;
 305             uint32_t                            ColorClampRange;
 306             bool                                PreBlendColorClampEnable;
 307             bool                                PostBlendColorClampEnable;
 308 #     endif
 309             );
 310     }
 311
 312    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
 313                   .BlendStatePointer = pipeline->blend_state.offset);
 314 }
 315
 316 static inline uint32_t
 317 scratch_space(const struct brw_stage_prog_data *prog_data)
 318 {
 319    return ffs(prog_data->total_scratch / 1024);
 320 }
 321
 322 GENX_FUNC(GEN7, GEN75) VkResult
 323 genX(graphics_pipeline_create)(
 324     VkDevice                                    _device,
 325     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 326     const struct anv_graphics_pipeline_create_info *extra,
 327     const VkAllocationCallbacks*                pAllocator,
 328     VkPipeline*                                 pPipeline)
 329 {
 330    ANV_FROM_HANDLE(anv_device, device, _device);
 331    struct anv_pipeline *pipeline;
 332    VkResult result;
 333
 334    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 335
 336    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 337                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 338    if (pipeline == NULL)
 339       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 340
 341    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
 342    if (result != VK_SUCCESS) {
 343       anv_free2(&device->alloc, pAllocator, pipeline);
 344       return result;
 345    }
 346
 347    assert(pCreateInfo->pVertexInputState);
 348    gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 349
 350    assert(pCreateInfo->pRasterizationState);
 351    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 352
 353    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 354
 355    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 356                                 pCreateInfo->pMultisampleState);
 357
 358    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
 359                    .StatisticsEnable = true);
 360    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
 361    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
 362    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
 363    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 364
 365    /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
 366     *
 367     *    "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 368     *    needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 369     *    3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 370     *    3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 371     *    needs to be sent before any combination of VS associated 3DSTATE."
 372     */
 373    anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
 374                   .DepthStallEnable = true,
 375                   .PostSyncOperation = WriteImmediateData,
 376                   .Address = { &device->workaround_bo, 0 });
 377
 378    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 379                   .ConstantBufferOffset = 0,
 380                   .ConstantBufferSize = 4);
 381    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 382                   .ConstantBufferOffset = 4,
 383                   .ConstantBufferSize = 4);
 384    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 385                   .ConstantBufferOffset = 8,
 386                   .ConstantBufferSize = 4);
 387
 388    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
 389
 390    const VkPipelineRasterizationStateCreateInfo *rs_info =
 391       pCreateInfo->pRasterizationState;
 392
 393    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
 394       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 395       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 396       .ClipEnable                               = true,
 397       .APIMode                                  = APIMODE_OGL,
 398       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 399       .ClipMode                                 = CLIPMODE_NORMAL,
 400       .TriangleStripListProvokingVertexSelect   = 0,
 401       .LineStripListProvokingVertexSelect       = 0,
 402       .TriangleFanProvokingVertexSelect         = 0,
 403       .MinimumPointWidth                        = 0.125,
 404       .MaximumPointWidth                        = 255.875);
 405
 406    uint32_t samples = 1;
 407    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 408
 409    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
 410       .PixelLocation                            = PIXLOC_CENTER,
 411       .NumberofMultisamples                     = log2_samples);
 412
 413    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
 414       .SampleMask                               = 0xff);
 415
 416    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
 417       .VSURBStartingAddress                     = pipeline->urb.vs_start,
 418       .VSURBEntryAllocationSize                 = pipeline->urb.vs_size - 1,
 419       .VSNumberofURBEntries                     = pipeline->urb.nr_vs_entries);
 420
 421    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
 422       .GSURBStartingAddress                     = pipeline->urb.gs_start,
 423       .GSURBEntryAllocationSize                 = pipeline->urb.gs_size - 1,
 424       .GSNumberofURBEntries                     = pipeline->urb.nr_gs_entries);
 425
 426    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
 427       .HSURBStartingAddress                     = pipeline->urb.vs_start,
 428       .HSURBEntryAllocationSize                 = 0,
 429       .HSNumberofURBEntries                     = 0);
 430
 431    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
 432       .DSURBStartingAddress                     = pipeline->urb.vs_start,
 433       .DSURBEntryAllocationSize                 = 0,
 434       .DSNumberofURBEntries                     = 0);
 435
 436    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 437    /* The last geometry producing stage will set urb_offset and urb_length,
 438     * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
 439    uint32_t urb_offset = 1;
 440    uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
 441
 442 #if 0
 443    /* From gen7_vs_state.c */
 444
 445    /**
 446     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 447     * Geometry > Geometry Shader > State:
 448     *
 449     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 450     *     whole fixed function pipeline when the GS enable changes value in
 451     *     the 3DSTATE_GS."
 452     *
 453     * The hardware architects have clarified that in this context "flush the
 454     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 455     * Stall" bit set.
 456     */
 457    if (!brw->is_haswell && !brw->is_baytrail)
 458       gen7_emit_vs_workaround_flush(brw);
 459 #endif
 460
 461    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 462       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 463    else
 464       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 465          .KernelStartPointer                    = pipeline->vs_vec4,
 466          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 467          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 468
 469          .DispatchGRFStartRegisterforURBData    =
 470             vue_prog_data->base.dispatch_grf_start_reg,
 471          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 472          .VertexURBEntryReadOffset              = 0,
 473
 474          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 475          .StatisticsEnable                      = true,
 476          .VSFunctionEnable                      = true);
 477
 478    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 479
 480    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 481       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 482    } else {
 483       urb_offset = 1;
 484       urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
 485
 486       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 487          .KernelStartPointer                    = pipeline->gs_kernel,
 488          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 489          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 490
 491          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 492          .OutputTopology                        = gs_prog_data->output_topology,
 493          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 494          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 495          .DispatchGRFStartRegisterforURBData    =
 496             gs_prog_data->base.base.dispatch_grf_start_reg,
 497
 498          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 499          /* This in the next dword on HSW. */
 500          .ControlDataFormat                     = gs_prog_data->control_data_format,
 501          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 502          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 503          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 504          .GSStatisticsEnable                    = true,
 505          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 506 #     if (ANV_IS_HASWELL)
 507          .ReorderMode                           = REORDER_TRAILING,
 508 #     else
 509          .ReorderEnable                         = true,
 510 #     endif
 511          .GSEnable                              = true);
 512    }
 513
 514    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 515    if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 516        wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 517       anv_finishme("two-sided color needs sbe swizzling setup");
 518    if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 519       anv_finishme("primitive_id needs sbe swizzling setup");
 520
 521    /* FIXME: generated header doesn't emit attr swizzle fields */
 522    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
 523       .NumberofSFOutputAttributes               = pipeline->wm_prog_data.num_varying_inputs,
 524       .VertexURBEntryReadLength                 = urb_length,
 525       .VertexURBEntryReadOffset                 = urb_offset,
 526       .PointSpriteTextureCoordinateOrigin       = UPPERLEFT);
 527
 528    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 529       .KernelStartPointer0                      = pipeline->ps_ksp0,
 530       .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 531       .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 532
 533       .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 534       .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 535       .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 536       .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 537
 538       .RenderTargetFastClearEnable              = false,
 539       .DualSourceBlendEnable                    = false,
 540       .RenderTargetResolveEnable                = false,
 541
 542       .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 543          POSOFFSET_SAMPLE : POSOFFSET_NONE,
 544
 545       ._32PixelDispatchEnable                   = false,
 546       ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 547       ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 548
 549       .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 550       .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 551       .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 552
 553 #if 0
 554    /* Haswell requires the sample mask to be set in this packet as well as
 555     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 556    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 557 #endif
 558
 559       .KernelStartPointer1                      = 0,
 560       .KernelStartPointer2                      = pipeline->ps_ksp2);
 561
 562    /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 563    anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
 564       .StatisticsEnable                         = true,
 565       .ThreadDispatchEnable                     = true,
 566       .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 567       .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 568       .EarlyDepthStencilControl                 = EDSC_NORMAL,
 569       .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 570       .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 571       .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 572
 573    *pPipeline = anv_pipeline_to_handle(pipeline);
 574
 575    return VK_SUCCESS;
 576 }
 577
 578 GENX_FUNC(GEN7, GEN75) VkResult
 579 genX(compute_pipeline_create)(
 580     VkDevice                                    _device,
 581     const VkComputePipelineCreateInfo*          pCreateInfo,
 582     const VkAllocationCallbacks*                pAllocator,
 583     VkPipeline*                                 pPipeline)
 584 {
 585    anv_finishme("primitive_id needs sbe swizzling setup");
 586    abort();
 587 }