2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "gen7_pack.h"
33 #include "gen75_pack.h"
36 gen7_emit_vertex_input(struct anv_pipeline
*pipeline
,
37 const VkPipelineVertexInputStateCreateInfo
*info
)
39 const bool sgvs
= pipeline
->vs_prog_data
.uses_vertexid
||
40 pipeline
->vs_prog_data
.uses_instanceid
;
41 const uint32_t element_count
=
42 info
->vertexAttributeDescriptionCount
+ (sgvs
? 1 : 0);
43 const uint32_t num_dwords
= 1 + element_count
* 2;
46 if (info
->vertexAttributeDescriptionCount
== 0 && !sgvs
)
49 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
50 GEN7_3DSTATE_VERTEX_ELEMENTS
);
52 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
53 const VkVertexInputAttributeDescription
*desc
=
54 &info
->pVertexAttributeDescriptions
[i
];
55 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
57 struct GEN7_VERTEX_ELEMENT_STATE element
= {
58 .VertexBufferIndex
= desc
->binding
,
60 .SourceElementFormat
= format
->surface_format
,
61 .EdgeFlagEnable
= false,
62 .SourceElementOffset
= desc
->offset
,
63 .Component0Control
= VFCOMP_STORE_SRC
,
64 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
65 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
66 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
68 GEN7_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
72 struct GEN7_VERTEX_ELEMENT_STATE element
= {
74 /* FIXME: Do we need to provide the base vertex as component 0 here
75 * to support the correct base vertex ID? */
76 .Component0Control
= VFCOMP_STORE_0
,
77 .Component1Control
= VFCOMP_STORE_0
,
78 .Component2Control
= VFCOMP_STORE_VID
,
79 .Component3Control
= VFCOMP_STORE_IID
81 GEN7_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + info
->vertexAttributeDescriptionCount
* 2], &element
);
85 static const uint32_t vk_to_gen_cullmode
[] = {
86 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
87 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
88 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
89 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
92 static const uint32_t vk_to_gen_fillmode
[] = {
93 [VK_POLYGON_MODE_FILL
] = RASTER_SOLID
,
94 [VK_POLYGON_MODE_LINE
] = RASTER_WIREFRAME
,
95 [VK_POLYGON_MODE_POINT
] = RASTER_POINT
,
98 static const uint32_t vk_to_gen_front_face
[] = {
99 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
100 [VK_FRONT_FACE_CLOCKWISE
] = 0
104 gen7_emit_rs_state(struct anv_pipeline
*pipeline
,
105 const VkPipelineRasterizationStateCreateInfo
*info
,
106 const struct anv_graphics_pipeline_create_info
*extra
)
108 struct GEN7_3DSTATE_SF sf
= {
109 GEN7_3DSTATE_SF_header
,
111 /* FIXME: Get this from pass info */
112 .DepthBufferSurfaceFormat
= D24_UNORM_X8_UINT
,
114 /* LegacyGlobalDepthBiasEnable */
116 .StatisticsEnable
= true,
117 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
118 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
119 .ViewTransformEnable
= !(extra
&& extra
->disable_viewport
),
120 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
121 /* bool AntiAliasingEnable; */
123 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
125 /* uint32_t LineEndCapAntialiasingRegionWidth; */
126 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
128 /* uint32_t MultisampleRasterizationMode; */
129 /* bool LastPixelEnable; */
131 .TriangleStripListProvokingVertexSelect
= 0,
132 .LineStripListProvokingVertexSelect
= 0,
133 .TriangleFanProvokingVertexSelect
= 0,
135 /* uint32_t AALineDistanceMode; */
136 /* uint32_t VertexSubPixelPrecisionSelect; */
137 .UsePointWidthState
= !pipeline
->writes_point_size
,
141 GEN7_3DSTATE_SF_pack(NULL
, &pipeline
->gen7
.sf
, &sf
);
144 static const uint32_t vk_to_gen_compare_op
[] = {
145 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
146 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
147 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
148 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
149 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
150 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
151 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
152 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
155 static const uint32_t vk_to_gen_stencil_op
[] = {
156 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
157 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
158 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
159 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
160 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
161 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
162 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
163 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
166 static const uint32_t vk_to_gen_blend_op
[] = {
167 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
168 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
169 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
170 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
171 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
174 static const uint32_t vk_to_gen_logic_op
[] = {
175 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
176 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
177 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
178 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
179 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
180 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
181 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
182 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
183 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
184 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
185 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
186 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
187 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
188 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
189 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
190 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
193 static const uint32_t vk_to_gen_blend
[] = {
194 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
195 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
196 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
197 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
198 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
199 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
200 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
201 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
202 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
203 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
204 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
205 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
206 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
207 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
208 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
209 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
210 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
211 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
212 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
216 gen7_emit_ds_state(struct anv_pipeline
*pipeline
,
217 const VkPipelineDepthStencilStateCreateInfo
*info
)
220 /* We're going to OR this together with the dynamic state. We need
221 * to make sure it's initialized to something useful.
223 memset(pipeline
->gen7
.depth_stencil_state
, 0,
224 sizeof(pipeline
->gen7
.depth_stencil_state
));
228 struct GEN7_DEPTH_STENCIL_STATE state
= {
229 .DepthTestEnable
= info
->depthTestEnable
,
230 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
231 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
232 .DoubleSidedStencilEnable
= true,
234 .StencilTestEnable
= info
->stencilTestEnable
,
235 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
236 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
237 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
238 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
240 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
241 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
242 .BackfaceStencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
243 .BackFaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
246 GEN7_DEPTH_STENCIL_STATE_pack(NULL
, &pipeline
->gen7
.depth_stencil_state
, &state
);
250 gen7_emit_cb_state(struct anv_pipeline
*pipeline
,
251 const VkPipelineColorBlendStateCreateInfo
*info
,
252 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
254 struct anv_device
*device
= pipeline
->device
;
256 uint32_t num_dwords
= GEN7_BLEND_STATE_length
;
257 pipeline
->blend_state
=
258 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
260 if (info
->pAttachments
== NULL
) {
261 struct GEN7_BLEND_STATE blend_state
= {
262 .ColorBufferBlendEnable
= false,
263 .WriteDisableAlpha
= false,
264 .WriteDisableRed
= false,
265 .WriteDisableGreen
= false,
266 .WriteDisableBlue
= false,
269 GEN7_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
271 /* FIXME-GEN7: All render targets share blend state settings on gen7, we
272 * can't implement this.
274 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[0];
276 struct GEN7_BLEND_STATE blend_state
= {
277 .ColorBufferBlendEnable
= a
->blendEnable
,
278 .IndependentAlphaBlendEnable
= true, /* FIXME: yes? */
279 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
281 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
282 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
284 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
285 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
286 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
287 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
290 bool AlphaToOneEnable
;
291 bool AlphaToCoverageDitherEnable
;
294 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
295 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
296 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
297 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
299 .LogicOpEnable
= info
->logicOpEnable
,
300 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
303 bool AlphaTestEnable
;
304 uint32_t AlphaTestFunction
;
305 bool ColorDitherEnable
;
306 uint32_t XDitherOffset
;
307 uint32_t YDitherOffset
;
308 uint32_t ColorClampRange
;
309 bool PreBlendColorClampEnable
;
310 bool PostBlendColorClampEnable
;
314 GEN7_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
317 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_BLEND_STATE_POINTERS
,
318 .BlendStatePointer
= pipeline
->blend_state
.offset
);
321 static inline uint32_t
322 scratch_space(const struct brw_stage_prog_data
*prog_data
)
324 return ffs(prog_data
->total_scratch
/ 1024);
327 GENX_FUNC(GEN7
, GEN75
) VkResult
328 genX(graphics_pipeline_create
)(
330 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
331 const struct anv_graphics_pipeline_create_info
*extra
,
332 const VkAllocationCallbacks
* pAllocator
,
333 VkPipeline
* pPipeline
)
335 ANV_FROM_HANDLE(anv_device
, device
, _device
);
336 struct anv_pipeline
*pipeline
;
339 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
341 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
343 if (pipeline
== NULL
)
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
346 result
= anv_pipeline_init(pipeline
, device
, pCreateInfo
, extra
, pAllocator
);
347 if (result
!= VK_SUCCESS
) {
348 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
352 assert(pCreateInfo
->pVertexInputState
);
353 gen7_emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
355 assert(pCreateInfo
->pRasterizationState
);
356 gen7_emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
, extra
);
358 gen7_emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
360 gen7_emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
361 pCreateInfo
->pMultisampleState
);
363 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_VF_STATISTICS
,
364 .StatisticsEnable
= true);
365 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_HS
, .Enable
= false);
366 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_TE
, .TEEnable
= false);
367 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_DS
, .DSFunctionEnable
= false);
368 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
370 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
372 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
373 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
374 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
375 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
376 * needs to be sent before any combination of VS associated 3DSTATE."
378 anv_batch_emit(&pipeline
->batch
, GEN7_PIPE_CONTROL
,
379 .DepthStallEnable
= true,
380 .PostSyncOperation
= WriteImmediateData
,
381 .Address
= { &device
->workaround_bo
, 0 });
383 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
384 .ConstantBufferOffset
= 0,
385 .ConstantBufferSize
= 4);
386 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
387 .ConstantBufferOffset
= 4,
388 .ConstantBufferSize
= 4);
389 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
390 .ConstantBufferOffset
= 8,
391 .ConstantBufferSize
= 4);
393 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_AA_LINE_PARAMETERS
);
395 const VkPipelineRasterizationStateCreateInfo
*rs_info
=
396 pCreateInfo
->pRasterizationState
;
398 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_CLIP
,
399 .FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
],
400 .CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
],
402 .APIMode
= APIMODE_OGL
,
403 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
404 .ClipMode
= CLIPMODE_NORMAL
,
405 .TriangleStripListProvokingVertexSelect
= 0,
406 .LineStripListProvokingVertexSelect
= 0,
407 .TriangleFanProvokingVertexSelect
= 0,
408 .MinimumPointWidth
= 0.125,
409 .MaximumPointWidth
= 255.875);
411 uint32_t samples
= 1;
412 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
414 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_MULTISAMPLE
,
415 .PixelLocation
= PIXLOC_CENTER
,
416 .NumberofMultisamples
= log2_samples
);
418 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_SAMPLE_MASK
,
421 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_VS
,
422 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
423 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
424 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
426 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_GS
,
427 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
428 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
429 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
431 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_HS
,
432 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
433 .HSURBEntryAllocationSize
= 0,
434 .HSNumberofURBEntries
= 0);
436 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_URB_DS
,
437 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
438 .DSURBEntryAllocationSize
= 0,
439 .DSNumberofURBEntries
= 0);
441 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
442 /* The last geometry producing stage will set urb_offset and urb_length,
443 * which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
444 uint32_t urb_offset
= 1;
445 uint32_t urb_length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_offset
;
448 /* From gen7_vs_state.c */
451 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
452 * Geometry > Geometry Shader > State:
454 * "Note: Because of corruption in IVB:GT2, software needs to flush the
455 * whole fixed function pipeline when the GS enable changes value in
458 * The hardware architects have clarified that in this context "flush the
459 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
462 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
463 gen7_emit_vs_workaround_flush(brw
);
466 if (pipeline
->vs_vec4
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
467 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), .VSFunctionEnable
= false);
469 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
470 .KernelStartPointer
= pipeline
->vs_vec4
,
471 .ScratchSpaceBaseOffset
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
472 .PerThreadScratchSpace
= scratch_space(&vue_prog_data
->base
),
474 .DispatchGRFStartRegisterforURBData
=
475 vue_prog_data
->base
.dispatch_grf_start_reg
,
476 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
477 .VertexURBEntryReadOffset
= 0,
479 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
480 .StatisticsEnable
= true,
481 .VSFunctionEnable
= true);
483 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
485 if (pipeline
->gs_vec4
== NO_KERNEL
|| (extra
&& extra
->disable_vs
)) {
486 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), .GSEnable
= false);
489 urb_length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - urb_offset
;
491 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
),
492 .KernelStartPointer
= pipeline
->gs_vec4
,
493 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
494 .PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
),
496 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
497 .OutputTopology
= gs_prog_data
->output_topology
,
498 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
499 .DispatchGRFStartRegisterforURBData
=
500 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
502 .MaximumNumberofThreads
= device
->info
.max_gs_threads
- 1,
503 /* This in the next dword on HSW. */
504 .ControlDataFormat
= gs_prog_data
->control_data_format
,
505 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
506 .InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1,
507 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
508 .GSStatisticsEnable
= true,
509 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
510 # if (ANV_IS_HASWELL)
511 .ReorderMode
= REORDER_TRAILING
,
513 .ReorderEnable
= true,
518 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
519 if (wm_prog_data
->urb_setup
[VARYING_SLOT_BFC0
] != -1 ||
520 wm_prog_data
->urb_setup
[VARYING_SLOT_BFC1
] != -1)
521 anv_finishme("two-sided color needs sbe swizzling setup");
522 if (wm_prog_data
->urb_setup
[VARYING_SLOT_PRIMITIVE_ID
] != -1)
523 anv_finishme("primitive_id needs sbe swizzling setup");
525 /* FIXME: generated header doesn't emit attr swizzle fields */
526 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_SBE
,
527 .NumberofSFOutputAttributes
= pipeline
->wm_prog_data
.num_varying_inputs
,
528 .VertexURBEntryReadLength
= urb_length
,
529 .VertexURBEntryReadOffset
= urb_offset
,
530 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
);
532 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
533 .KernelStartPointer0
= pipeline
->ps_ksp0
,
534 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
535 .PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
),
537 .MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1,
538 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
539 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
540 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
542 .RenderTargetFastClearEnable
= false,
543 .DualSourceBlendEnable
= false,
544 .RenderTargetResolveEnable
= false,
546 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
547 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
549 ._32PixelDispatchEnable
= false,
550 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
551 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
553 .DispatchGRFStartRegisterforConstantSetupData0
= pipeline
->ps_grf_start0
,
554 .DispatchGRFStartRegisterforConstantSetupData1
= 0,
555 .DispatchGRFStartRegisterforConstantSetupData2
= pipeline
->ps_grf_start2
,
558 /* Haswell requires the sample mask to be set in this packet as well as
559 * in 3DSTATE_SAMPLE_MASK; the values should match. */
560 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
563 .KernelStartPointer1
= 0,
564 .KernelStartPointer2
= pipeline
->ps_ksp2
);
566 /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
567 anv_batch_emit(&pipeline
->batch
, GEN7_3DSTATE_WM
,
568 .StatisticsEnable
= true,
569 .ThreadDispatchEnable
= true,
570 .LineEndCapAntialiasingRegionWidth
= 0, /* 0.5 pixels */
571 .LineAntialiasingRegionWidth
= 1, /* 1.0 pixels */
572 .EarlyDepthStencilControl
= EDSC_NORMAL
,
573 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
574 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
575 .BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
);
577 *pPipeline
= anv_pipeline_to_handle(pipeline
);
582 GENX_FUNC(GEN7
, GEN75
) VkResult
583 genX(compute_pipeline_create
)(
585 const VkComputePipelineCreateInfo
* pCreateInfo
,
586 const VkAllocationCallbacks
* pAllocator
,
587 VkPipeline
* pPipeline
)
589 anv_finishme("primitive_id needs sbe swizzling setup");