src/vulkan/gen7_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 GENX_FUNC(GEN7, GEN75) void
  36 genX(fill_buffer_surface_state)(void *state, const struct anv_format *format,
  37                                 uint32_t offset, uint32_t range,
  38                                 uint32_t stride)
  39 {
  40    uint32_t num_elements = range / stride;
  41
  42    struct GENX(RENDER_SURFACE_STATE) surface_state = {
  43       .SurfaceType                              = SURFTYPE_BUFFER,
  44       .SurfaceFormat                            = format->surface_format,
  45       .SurfaceVerticalAlignment                 = VALIGN_4,
  46       .SurfaceHorizontalAlignment               = HALIGN_4,
  47       .TiledSurface                             = false,
  48       .RenderCacheReadWriteMode                 = false,
  49       .SurfaceObjectControlState                = GENX(MOCS),
  50       .Height                                   = (num_elements >> 7) & 0x3fff,
  51       .Width                                    = num_elements & 0x7f,
  52       .Depth                                    = (num_elements >> 21) & 0x3f,
  53       .SurfacePitch                             = stride - 1,
  54 #  if (ANV_IS_HASWELL)
  55       .ShaderChannelSelectR                     = SCS_RED,
  56       .ShaderChannelSelectG                     = SCS_GREEN,
  57       .ShaderChannelSelectB                     = SCS_BLUE,
  58       .ShaderChannelSelectA                     = SCS_ALPHA,
  59 #  endif
  60       .SurfaceBaseAddress                       = { NULL, offset },
  61    };
  62
  63    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
  64 }
  65
  66 static const uint32_t vk_to_gen_tex_filter[] = {
  67    [VK_TEX_FILTER_NEAREST]                      = MAPFILTER_NEAREST,
  68    [VK_TEX_FILTER_LINEAR]                       = MAPFILTER_LINEAR
  69 };
  70
  71 static const uint32_t vk_to_gen_mipmap_mode[] = {
  72    [VK_TEX_MIPMAP_MODE_BASE]                    = MIPFILTER_NONE,
  73    [VK_TEX_MIPMAP_MODE_NEAREST]                 = MIPFILTER_NEAREST,
  74    [VK_TEX_MIPMAP_MODE_LINEAR]                  = MIPFILTER_LINEAR
  75 };
  76
  77 static const uint32_t vk_to_gen_tex_address[] = {
  78    [VK_TEX_ADDRESS_MODE_WRAP]                   = TCM_WRAP,
  79    [VK_TEX_ADDRESS_MODE_MIRROR]                 = TCM_MIRROR,
  80    [VK_TEX_ADDRESS_MODE_CLAMP]                  = TCM_CLAMP,
  81    [VK_TEX_ADDRESS_MODE_MIRROR_ONCE]            = TCM_MIRROR_ONCE,
  82    [VK_TEX_ADDRESS_MODE_CLAMP_BORDER]           = TCM_CLAMP_BORDER,
  83 };
  84
  85 static const uint32_t vk_to_gen_compare_op[] = {
  86    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
  87    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
  88    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
  89    [VK_COMPARE_OP_LESS_EQUAL]                   = PREFILTEROPLEQUAL,
  90    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
  91    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
  92    [VK_COMPARE_OP_GREATER_EQUAL]                = PREFILTEROPGEQUAL,
  93    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
  94 };
  95
  96 static struct anv_state
  97 alloc_surface_state(struct anv_device *device,
  98                     struct anv_cmd_buffer *cmd_buffer)
  99 {
 100       if (cmd_buffer) {
 101          return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
 102       } else {
 103          return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
 104       }
 105 }
 106
 107 VkResult genX(CreateSampler)(
 108     VkDevice                                    _device,
 109     const VkSamplerCreateInfo*                  pCreateInfo,
 110     VkSampler*                                  pSampler)
 111 {
 112    ANV_FROM_HANDLE(anv_device, device, _device);
 113    struct anv_sampler *sampler;
 114    uint32_t mag_filter, min_filter, max_anisotropy;
 115
 116    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 117
 118    sampler = anv_device_alloc(device, sizeof(*sampler), 8,
 119                               VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 120    if (!sampler)
 121       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 122
 123    if (pCreateInfo->maxAnisotropy > 1) {
 124       mag_filter = MAPFILTER_ANISOTROPIC;
 125       min_filter = MAPFILTER_ANISOTROPIC;
 126       max_anisotropy = (pCreateInfo->maxAnisotropy - 2) / 2;
 127    } else {
 128       mag_filter = vk_to_gen_tex_filter[pCreateInfo->magFilter];
 129       min_filter = vk_to_gen_tex_filter[pCreateInfo->minFilter];
 130       max_anisotropy = RATIO21;
 131    }
 132
 133    struct GEN7_SAMPLER_STATE sampler_state = {
 134       .SamplerDisable = false,
 135       .TextureBorderColorMode = DX10OGL,
 136       .BaseMipLevel = 0.0,
 137       .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipMode],
 138       .MagModeFilter = mag_filter,
 139       .MinModeFilter = min_filter,
 140       .TextureLODBias = pCreateInfo->mipLodBias * 256,
 141       .AnisotropicAlgorithm = EWAApproximation,
 142       .MinLOD = pCreateInfo->minLod,
 143       .MaxLOD = pCreateInfo->maxLod,
 144       .ChromaKeyEnable = 0,
 145       .ChromaKeyIndex = 0,
 146       .ChromaKeyMode = 0,
 147       .ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
 148       .CubeSurfaceControlMode = 0,
 149
 150       .BorderColorPointer =
 151          device->border_colors.offset +
 152          pCreateInfo->borderColor * sizeof(float) * 4,
 153
 154       .MaximumAnisotropy = max_anisotropy,
 155       .RAddressMinFilterRoundingEnable = 0,
 156       .RAddressMagFilterRoundingEnable = 0,
 157       .VAddressMinFilterRoundingEnable = 0,
 158       .VAddressMagFilterRoundingEnable = 0,
 159       .UAddressMinFilterRoundingEnable = 0,
 160       .UAddressMagFilterRoundingEnable = 0,
 161       .TrilinearFilterQuality = 0,
 162       .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 163       .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 164       .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 165       .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 166    };
 167
 168    GEN7_SAMPLER_STATE_pack(NULL, sampler->state, &sampler_state);
 169
 170    *pSampler = anv_sampler_to_handle(sampler);
 171
 172    return VK_SUCCESS;
 173 }
 174
 175 static const uint8_t anv_halign[] = {
 176     [4] = HALIGN_4,
 177     [8] = HALIGN_8,
 178 };
 179
 180 static const uint8_t anv_valign[] = {
 181     [2] = VALIGN_2,
 182     [4] = VALIGN_4,
 183 };
 184
 185 static const uint32_t vk_to_gen_swizzle[] = {
 186    [VK_CHANNEL_SWIZZLE_ZERO]                 = SCS_ZERO,
 187    [VK_CHANNEL_SWIZZLE_ONE]                  = SCS_ONE,
 188    [VK_CHANNEL_SWIZZLE_R]                    = SCS_RED,
 189    [VK_CHANNEL_SWIZZLE_G]                    = SCS_GREEN,
 190    [VK_CHANNEL_SWIZZLE_B]                    = SCS_BLUE,
 191    [VK_CHANNEL_SWIZZLE_A]                    = SCS_ALPHA
 192 };
 193
 194 GENX_FUNC(GEN7, GEN75) void
 195 genX(image_view_init)(struct anv_image_view *iview,
 196                       struct anv_device *device,
 197                       const VkImageViewCreateInfo* pCreateInfo,
 198                       struct anv_cmd_buffer *cmd_buffer)
 199 {
 200    ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
 201
 202    const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
 203
 204    struct anv_surface *surface =
 205       anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
 206
 207    const struct anv_format *format =
 208       anv_format_for_vk_format(pCreateInfo->format);
 209
 210    if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
 211       anv_finishme("non-2D image views");
 212
 213    iview->image = image;
 214    iview->bo = image->bo;
 215    iview->offset = image->offset + surface->offset;
 216    iview->format = anv_format_for_vk_format(pCreateInfo->format);
 217
 218    iview->extent = (VkExtent3D) {
 219       .width = anv_minify(image->extent.width, range->baseMipLevel),
 220       .height = anv_minify(image->extent.height, range->baseMipLevel),
 221       .depth = anv_minify(image->extent.depth, range->baseMipLevel),
 222    };
 223
 224    uint32_t depth = 1;
 225    if (range->arraySize > 1) {
 226       depth = range->arraySize;
 227    } else if (image->extent.depth > 1) {
 228       depth = image->extent.depth;
 229    }
 230
 231    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 232       .SurfaceType = image->surface_type,
 233       .SurfaceArray = image->array_size > 1,
 234       .SurfaceFormat = format->surface_format,
 235       .SurfaceVerticalAlignment = anv_valign[surface->v_align],
 236       .SurfaceHorizontalAlignment = anv_halign[surface->h_align],
 237
 238       /* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
 239        * Tiled Surface is False."
 240        */
 241       .TiledSurface = surface->tiling != ISL_TILING_LINEAR,
 242       .TileWalk = surface->tiling == ISL_TILING_Y ?
 243                   TILEWALK_YMAJOR : TILEWALK_XMAJOR,
 244
 245       .VerticalLineStride = 0,
 246       .VerticalLineStrideOffset = 0,
 247
 248       .RenderCacheReadWriteMode = 0, /* TEMPLATE */
 249
 250       .Height = image->extent.height - 1,
 251       .Width = image->extent.width - 1,
 252       .Depth = depth - 1,
 253       .SurfacePitch = surface->stride - 1,
 254       .MinimumArrayElement = range->baseArrayLayer,
 255       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 256       .XOffset = 0,
 257       .YOffset = 0,
 258
 259       .SurfaceObjectControlState = GENX(MOCS),
 260
 261       .MIPCountLOD = 0, /* TEMPLATE */
 262       .SurfaceMinLOD = 0, /* TEMPLATE */
 263
 264       .MCSEnable = false,
 265 #  if (ANV_IS_HASWELL)
 266       .ShaderChannelSelectR = vk_to_gen_swizzle[pCreateInfo->channels.r],
 267       .ShaderChannelSelectG = vk_to_gen_swizzle[pCreateInfo->channels.g],
 268       .ShaderChannelSelectB = vk_to_gen_swizzle[pCreateInfo->channels.b],
 269       .ShaderChannelSelectA = vk_to_gen_swizzle[pCreateInfo->channels.a],
 270 #  else /* XXX: Seriously? */
 271       .RedClearColor = 0,
 272       .GreenClearColor = 0,
 273       .BlueClearColor = 0,
 274       .AlphaClearColor = 0,
 275 #  endif
 276       .ResourceMinLOD = 0.0,
 277       .SurfaceBaseAddress = { NULL, iview->offset },
 278    };
 279
 280    if (image->needs_nonrt_surface_state) {
 281       iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer);
 282
 283       surface_state.RenderCacheReadWriteMode = false;
 284
 285       /* For non render target surfaces, the hardware interprets field
 286        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 287        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 288        */
 289       surface_state.SurfaceMinLOD = range->baseMipLevel;
 290       surface_state.MIPCountLOD = range->mipLevels - 1;
 291
 292       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
 293                                       &surface_state);
 294    }
 295
 296    if (image->needs_color_rt_surface_state) {
 297       iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
 298
 299       surface_state.RenderCacheReadWriteMode = 0; /* Write only */
 300
 301       /* For render target surfaces, the hardware interprets field MIPCount/LOD as
 302        * LOD. The Broadwell PRM says:
 303        *
 304        *    MIPCountLOD defines the LOD that will be rendered into.
 305        *    SurfaceMinLOD is ignored.
 306        */
 307       surface_state.MIPCountLOD = range->baseMipLevel;
 308       surface_state.SurfaceMinLOD = 0;
 309
 310       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
 311                                       &surface_state);
 312    }
 313 }