src/vulkan/gen7_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 void
  33 gen7_fill_buffer_surface_state(void *state, const struct anv_format *format,
  34                                uint32_t offset, uint32_t range, uint32_t stride)
  35 {
  36    uint32_t num_elements = range / stride;
  37
  38    struct GEN7_RENDER_SURFACE_STATE surface_state = {
  39       .SurfaceType                              = SURFTYPE_BUFFER,
  40       .SurfaceFormat                            = format->surface_format,
  41       .SurfaceVerticalAlignment                 = VALIGN_4,
  42       .SurfaceHorizontalAlignment               = HALIGN_4,
  43       .TiledSurface                             = false,
  44       .RenderCacheReadWriteMode                 = false,
  45       .SurfaceObjectControlState                = GEN7_MOCS,
  46       .Height                                   = (num_elements >> 7) & 0x3fff,
  47       .Width                                    = num_elements & 0x7f,
  48       .Depth                                    = (num_elements >> 21) & 0x3f,
  49       .SurfacePitch                             = stride - 1,
  50       .SurfaceBaseAddress                       = { NULL, offset },
  51    };
  52
  53    GEN7_RENDER_SURFACE_STATE_pack(NULL, state, &surface_state);
  54 }
  55
  56 static const uint32_t vk_to_gen_tex_filter[] = {
  57    [VK_TEX_FILTER_NEAREST]                      = MAPFILTER_NEAREST,
  58    [VK_TEX_FILTER_LINEAR]                       = MAPFILTER_LINEAR
  59 };
  60
  61 static const uint32_t vk_to_gen_mipmap_mode[] = {
  62    [VK_TEX_MIPMAP_MODE_BASE]                    = MIPFILTER_NONE,
  63    [VK_TEX_MIPMAP_MODE_NEAREST]                 = MIPFILTER_NEAREST,
  64    [VK_TEX_MIPMAP_MODE_LINEAR]                  = MIPFILTER_LINEAR
  65 };
  66
  67 static const uint32_t vk_to_gen_tex_address[] = {
  68    [VK_TEX_ADDRESS_MODE_WRAP]                   = TCM_WRAP,
  69    [VK_TEX_ADDRESS_MODE_MIRROR]                 = TCM_MIRROR,
  70    [VK_TEX_ADDRESS_MODE_CLAMP]                  = TCM_CLAMP,
  71    [VK_TEX_ADDRESS_MODE_MIRROR_ONCE]            = TCM_MIRROR_ONCE,
  72    [VK_TEX_ADDRESS_MODE_CLAMP_BORDER]           = TCM_CLAMP_BORDER,
  73 };
  74
  75 static const uint32_t vk_to_gen_compare_op[] = {
  76    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
  77    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
  78    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
  79    [VK_COMPARE_OP_LESS_EQUAL]                   = PREFILTEROPLEQUAL,
  80    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
  81    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
  82    [VK_COMPARE_OP_GREATER_EQUAL]                = PREFILTEROPGEQUAL,
  83    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
  84 };
  85
  86 static struct anv_state
  87 gen7_alloc_surface_state(struct anv_device *device,
  88                          struct anv_cmd_buffer *cmd_buffer)
  89 {
  90       if (cmd_buffer) {
  91          return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
  92       } else {
  93          return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
  94       }
  95 }
  96
  97 VkResult gen7_CreateSampler(
  98     VkDevice                                    _device,
  99     const VkSamplerCreateInfo*                  pCreateInfo,
 100     VkSampler*                                  pSampler)
 101 {
 102    ANV_FROM_HANDLE(anv_device, device, _device);
 103    struct anv_sampler *sampler;
 104    uint32_t mag_filter, min_filter, max_anisotropy;
 105
 106    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 107
 108    sampler = anv_device_alloc(device, sizeof(*sampler), 8,
 109                               VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 110    if (!sampler)
 111       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 112
 113    if (pCreateInfo->maxAnisotropy > 1) {
 114       mag_filter = MAPFILTER_ANISOTROPIC;
 115       min_filter = MAPFILTER_ANISOTROPIC;
 116       max_anisotropy = (pCreateInfo->maxAnisotropy - 2) / 2;
 117    } else {
 118       mag_filter = vk_to_gen_tex_filter[pCreateInfo->magFilter];
 119       min_filter = vk_to_gen_tex_filter[pCreateInfo->minFilter];
 120       max_anisotropy = RATIO21;
 121    }
 122
 123    struct GEN7_SAMPLER_STATE sampler_state = {
 124       .SamplerDisable = false,
 125       .TextureBorderColorMode = DX10OGL,
 126       .BaseMipLevel = 0.0,
 127       .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipMode],
 128       .MagModeFilter = mag_filter,
 129       .MinModeFilter = min_filter,
 130       .TextureLODBias = pCreateInfo->mipLodBias * 256,
 131       .AnisotropicAlgorithm = EWAApproximation,
 132       .MinLOD = pCreateInfo->minLod,
 133       .MaxLOD = pCreateInfo->maxLod,
 134       .ChromaKeyEnable = 0,
 135       .ChromaKeyIndex = 0,
 136       .ChromaKeyMode = 0,
 137       .ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
 138       .CubeSurfaceControlMode = 0,
 139
 140       .BorderColorPointer =
 141          device->border_colors.offset +
 142          pCreateInfo->borderColor * sizeof(float) * 4,
 143
 144       .MaximumAnisotropy = max_anisotropy,
 145       .RAddressMinFilterRoundingEnable = 0,
 146       .RAddressMagFilterRoundingEnable = 0,
 147       .VAddressMinFilterRoundingEnable = 0,
 148       .VAddressMagFilterRoundingEnable = 0,
 149       .UAddressMinFilterRoundingEnable = 0,
 150       .UAddressMagFilterRoundingEnable = 0,
 151       .TrilinearFilterQuality = 0,
 152       .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 153       .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 154       .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 155       .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 156    };
 157
 158    GEN7_SAMPLER_STATE_pack(NULL, sampler->state, &sampler_state);
 159
 160    *pSampler = anv_sampler_to_handle(sampler);
 161
 162    return VK_SUCCESS;
 163 }
 164
 165 static const uint8_t anv_halign[] = {
 166     [4] = HALIGN_4,
 167     [8] = HALIGN_8,
 168 };
 169
 170 static const uint8_t anv_valign[] = {
 171     [2] = VALIGN_2,
 172     [4] = VALIGN_4,
 173 };
 174
 175 void
 176 gen7_image_view_init(struct anv_image_view *iview,
 177                      struct anv_device *device,
 178                      const VkImageViewCreateInfo* pCreateInfo,
 179                      struct anv_cmd_buffer *cmd_buffer)
 180 {
 181    ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
 182
 183    const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
 184
 185    struct anv_surface *surface =
 186       anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
 187
 188    const struct anv_format *format =
 189       anv_format_for_vk_format(pCreateInfo->format);
 190
 191    if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
 192       anv_finishme("non-2D image views");
 193
 194    iview->image = image;
 195    iview->bo = image->bo;
 196    iview->offset = image->offset + surface->offset;
 197    iview->format = anv_format_for_vk_format(pCreateInfo->format);
 198
 199    iview->extent = (VkExtent3D) {
 200       .width = anv_minify(image->extent.width, range->baseMipLevel),
 201       .height = anv_minify(image->extent.height, range->baseMipLevel),
 202       .depth = anv_minify(image->extent.depth, range->baseMipLevel),
 203    };
 204
 205    uint32_t depth = 1;
 206    if (range->arraySize > 1) {
 207       depth = range->arraySize;
 208    } else if (image->extent.depth > 1) {
 209       depth = image->extent.depth;
 210    }
 211
 212    struct GEN7_RENDER_SURFACE_STATE surface_state = {
 213       .SurfaceType = image->surface_type,
 214       .SurfaceArray = image->array_size > 1,
 215       .SurfaceFormat = format->surface_format,
 216       .SurfaceVerticalAlignment = anv_valign[surface->v_align],
 217       .SurfaceHorizontalAlignment = anv_halign[surface->h_align],
 218
 219       /* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
 220        * Tiled Surface is False."
 221        */
 222       .TiledSurface = surface->tiling != ISL_TILING_LINEAR,
 223       .TileWalk = surface->tiling == ISL_TILING_Y ?
 224                   TILEWALK_YMAJOR : TILEWALK_XMAJOR,
 225
 226       .VerticalLineStride = 0,
 227       .VerticalLineStrideOffset = 0,
 228
 229       .RenderCacheReadWriteMode = 0, /* TEMPLATE */
 230
 231       .Height = image->extent.height - 1,
 232       .Width = image->extent.width - 1,
 233       .Depth = depth - 1,
 234       .SurfacePitch = surface->stride - 1,
 235       .MinimumArrayElement = range->baseArrayLayer,
 236       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 237       .XOffset = 0,
 238       .YOffset = 0,
 239
 240       .SurfaceObjectControlState = GEN7_MOCS,
 241
 242       .MIPCountLOD = 0, /* TEMPLATE */
 243       .SurfaceMinLOD = 0, /* TEMPLATE */
 244
 245       .MCSEnable = false,
 246       .RedClearColor = 0,
 247       .GreenClearColor = 0,
 248       .BlueClearColor = 0,
 249       .AlphaClearColor = 0,
 250       .ResourceMinLOD = 0.0,
 251       .SurfaceBaseAddress = { NULL, iview->offset },
 252    };
 253
 254    if (image->needs_nonrt_surface_state) {
 255       iview->nonrt_surface_state =
 256          gen7_alloc_surface_state(device, cmd_buffer);
 257
 258       surface_state.RenderCacheReadWriteMode = false;
 259
 260       /* For non render target surfaces, the hardware interprets field
 261        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 262        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 263        */
 264       surface_state.SurfaceMinLOD = range->baseMipLevel;
 265       surface_state.MIPCountLOD = range->mipLevels - 1;
 266
 267       GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->nonrt_surface_state.map,
 268                                      &surface_state);
 269    }
 270
 271    if (image->needs_color_rt_surface_state) {
 272       iview->color_rt_surface_state =
 273          gen7_alloc_surface_state(device, cmd_buffer);
 274
 275       surface_state.RenderCacheReadWriteMode = WriteOnlyCache;
 276
 277       /* For render target surfaces, the hardware interprets field MIPCount/LOD as
 278        * LOD. The Broadwell PRM says:
 279        *
 280        *    MIPCountLOD defines the LOD that will be rendered into.
 281        *    SurfaceMinLOD is ignored.
 282        */
 283       surface_state.MIPCountLOD = range->baseMipLevel;
 284       surface_state.SurfaceMinLOD = 0;
 285
 286       GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->color_rt_surface_state.map,
 287                                      &surface_state);
 288    }
 289 }