src/vulkan/gen7_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen7_pack.h"
  33 #include "gen75_pack.h"
  34
  35 GENX_FUNC(GEN7, GEN75) void
  36 genX(fill_buffer_surface_state)(void *state, const struct anv_format *format,
  37                                 uint32_t offset, uint32_t range,
  38                                 uint32_t stride)
  39 {
  40    uint32_t num_elements = range / stride;
  41
  42    struct GENX(RENDER_SURFACE_STATE) surface_state = {
  43       .SurfaceType                              = SURFTYPE_BUFFER,
  44       .SurfaceFormat                            = format->surface_format,
  45       .SurfaceVerticalAlignment                 = VALIGN_4,
  46       .SurfaceHorizontalAlignment               = HALIGN_4,
  47       .TiledSurface                             = false,
  48       .RenderCacheReadWriteMode                 = false,
  49       .SurfaceObjectControlState                = GENX(MOCS),
  50       .Height                                   = (num_elements >> 7) & 0x3fff,
  51       .Width                                    = num_elements & 0x7f,
  52       .Depth                                    = (num_elements >> 21) & 0x3f,
  53       .SurfacePitch                             = stride - 1,
  54 #  if (ANV_IS_HASWELL)
  55       .ShaderChannelSelectR                     = SCS_RED,
  56       .ShaderChannelSelectG                     = SCS_GREEN,
  57       .ShaderChannelSelectB                     = SCS_BLUE,
  58       .ShaderChannelSelectA                     = SCS_ALPHA,
  59 #  endif
  60       .SurfaceBaseAddress                       = { NULL, offset },
  61    };
  62
  63    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
  64 }
  65
  66 static const uint32_t vk_to_gen_tex_filter[] = {
  67    [VK_FILTER_NEAREST]                          = MAPFILTER_NEAREST,
  68    [VK_FILTER_LINEAR]                           = MAPFILTER_LINEAR
  69 };
  70
  71 static const uint32_t vk_to_gen_mipmap_mode[] = {
  72    [VK_SAMPLER_MIPMAP_MODE_BASE]                = MIPFILTER_NONE,
  73    [VK_SAMPLER_MIPMAP_MODE_NEAREST]             = MIPFILTER_NEAREST,
  74    [VK_SAMPLER_MIPMAP_MODE_LINEAR]              = MIPFILTER_LINEAR
  75 };
  76
  77 static const uint32_t vk_to_gen_tex_address[] = {
  78    [VK_SAMPLER_ADDRESS_MODE_REPEAT]             = TCM_WRAP,
  79    [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT]    = TCM_MIRROR,
  80    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE]      = TCM_CLAMP,
  81    [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
  82    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER]    = TCM_CLAMP_BORDER,
  83 };
  84
  85 static const uint32_t vk_to_gen_compare_op[] = {
  86    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPNEVER,
  87    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLESS,
  88    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPEQUAL,
  89    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLEQUAL,
  90    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGREATER,
  91    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPNOTEQUAL,
  92    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGEQUAL,
  93    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPALWAYS,
  94 };
  95
  96 static struct anv_state
  97 alloc_surface_state(struct anv_device *device,
  98                     struct anv_cmd_buffer *cmd_buffer)
  99 {
 100       if (cmd_buffer) {
 101          return anv_cmd_buffer_alloc_surface_state(cmd_buffer);
 102       } else {
 103          return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
 104       }
 105 }
 106
 107 VkResult genX(CreateSampler)(
 108     VkDevice                                    _device,
 109     const VkSamplerCreateInfo*                  pCreateInfo,
 110     const VkAllocationCallbacks*                pAllocator,
 111     VkSampler*                                  pSampler)
 112 {
 113    ANV_FROM_HANDLE(anv_device, device, _device);
 114    struct anv_sampler *sampler;
 115    uint32_t mag_filter, min_filter, max_anisotropy;
 116
 117    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 118
 119    sampler = anv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
 120                         VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 121    if (!sampler)
 122       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 123
 124    if (pCreateInfo->maxAnisotropy > 1) {
 125       mag_filter = MAPFILTER_ANISOTROPIC;
 126       min_filter = MAPFILTER_ANISOTROPIC;
 127       max_anisotropy = (pCreateInfo->maxAnisotropy - 2) / 2;
 128    } else {
 129       mag_filter = vk_to_gen_tex_filter[pCreateInfo->magFilter];
 130       min_filter = vk_to_gen_tex_filter[pCreateInfo->minFilter];
 131       max_anisotropy = RATIO21;
 132    }
 133
 134    struct GEN7_SAMPLER_STATE sampler_state = {
 135       .SamplerDisable = false,
 136       .TextureBorderColorMode = DX10OGL,
 137       .BaseMipLevel = 0.0,
 138       .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
 139       .MagModeFilter = mag_filter,
 140       .MinModeFilter = min_filter,
 141       .TextureLODBias = pCreateInfo->mipLodBias * 256,
 142       .AnisotropicAlgorithm = EWAApproximation,
 143       .MinLOD = pCreateInfo->minLod,
 144       .MaxLOD = pCreateInfo->maxLod,
 145       .ChromaKeyEnable = 0,
 146       .ChromaKeyIndex = 0,
 147       .ChromaKeyMode = 0,
 148       .ShadowFunction = vk_to_gen_compare_op[pCreateInfo->compareOp],
 149       .CubeSurfaceControlMode = 0,
 150
 151       .BorderColorPointer =
 152          device->border_colors.offset +
 153          pCreateInfo->borderColor * sizeof(float) * 4,
 154
 155       .MaximumAnisotropy = max_anisotropy,
 156       .RAddressMinFilterRoundingEnable = 0,
 157       .RAddressMagFilterRoundingEnable = 0,
 158       .VAddressMinFilterRoundingEnable = 0,
 159       .VAddressMagFilterRoundingEnable = 0,
 160       .UAddressMinFilterRoundingEnable = 0,
 161       .UAddressMagFilterRoundingEnable = 0,
 162       .TrilinearFilterQuality = 0,
 163       .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 164       .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 165       .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 166       .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 167    };
 168
 169    GEN7_SAMPLER_STATE_pack(NULL, sampler->state, &sampler_state);
 170
 171    *pSampler = anv_sampler_to_handle(sampler);
 172
 173    return VK_SUCCESS;
 174 }
 175
 176 static const uint8_t anv_halign[] = {
 177     [4] = HALIGN_4,
 178     [8] = HALIGN_8,
 179 };
 180
 181 static const uint8_t anv_valign[] = {
 182     [2] = VALIGN_2,
 183     [4] = VALIGN_4,
 184 };
 185
 186 static const uint32_t vk_to_gen_swizzle_map[] = {
 187    [VK_COMPONENT_SWIZZLE_ZERO]                 = SCS_ZERO,
 188    [VK_COMPONENT_SWIZZLE_ONE]                  = SCS_ONE,
 189    [VK_COMPONENT_SWIZZLE_R]                    = SCS_RED,
 190    [VK_COMPONENT_SWIZZLE_G]                    = SCS_GREEN,
 191    [VK_COMPONENT_SWIZZLE_B]                    = SCS_BLUE,
 192    [VK_COMPONENT_SWIZZLE_A]                    = SCS_ALPHA
 193 };
 194
 195 static inline uint32_t
 196 vk_to_gen_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component)
 197 {
 198    if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
 199       return vk_to_gen_swizzle_map[component];
 200    else
 201       return vk_to_gen_swizzle_map[swizzle];
 202 }
 203
 204 GENX_FUNC(GEN7, GEN75) void
 205 genX(image_view_init)(struct anv_image_view *iview,
 206                       struct anv_device *device,
 207                       const VkImageViewCreateInfo* pCreateInfo,
 208                       struct anv_cmd_buffer *cmd_buffer)
 209 {
 210    ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
 211
 212    const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
 213
 214    struct anv_surface *surface =
 215       anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
 216
 217    const struct anv_format *format =
 218       anv_format_for_vk_format(pCreateInfo->format);
 219
 220    if (pCreateInfo->viewType != VK_IMAGE_VIEW_TYPE_2D)
 221       anv_finishme("non-2D image views");
 222
 223    iview->image = image;
 224    iview->bo = image->bo;
 225    iview->offset = image->offset + surface->offset;
 226    iview->format = anv_format_for_vk_format(pCreateInfo->format);
 227
 228    iview->extent = (VkExtent3D) {
 229       .width = anv_minify(image->extent.width, range->baseMipLevel),
 230       .height = anv_minify(image->extent.height, range->baseMipLevel),
 231       .depth = anv_minify(image->extent.depth, range->baseMipLevel),
 232    };
 233
 234    uint32_t depth = 1;
 235    if (range->layerCount > 1) {
 236       depth = range->layerCount;
 237    } else if (image->extent.depth > 1) {
 238       depth = image->extent.depth;
 239    }
 240
 241    const struct isl_extent3d lod_align_sa =
 242       isl_surf_get_lod_alignment_sa(&surface->isl);
 243
 244    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 245       .SurfaceType = image->surface_type,
 246       .SurfaceArray = image->array_size > 1,
 247       .SurfaceFormat = format->surface_format,
 248       .SurfaceVerticalAlignment = anv_valign[lod_align_sa.height],
 249       .SurfaceHorizontalAlignment = anv_halign[lod_align_sa.width],
 250
 251       /* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
 252        * Tiled Surface is False."
 253        */
 254       .TiledSurface = surface->isl.tiling != ISL_TILING_LINEAR,
 255       .TileWalk = surface->isl.tiling == ISL_TILING_Y0 ?
 256                   TILEWALK_YMAJOR : TILEWALK_XMAJOR,
 257
 258       .VerticalLineStride = 0,
 259       .VerticalLineStrideOffset = 0,
 260
 261       .RenderCacheReadWriteMode = 0, /* TEMPLATE */
 262
 263       .Height = image->extent.height - 1,
 264       .Width = image->extent.width - 1,
 265       .Depth = depth - 1,
 266       .SurfacePitch = surface->isl.row_pitch - 1,
 267       .MinimumArrayElement = range->baseArrayLayer,
 268       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 269       .XOffset = 0,
 270       .YOffset = 0,
 271
 272       .SurfaceObjectControlState = GENX(MOCS),
 273
 274       .MIPCountLOD = 0, /* TEMPLATE */
 275       .SurfaceMinLOD = 0, /* TEMPLATE */
 276
 277       .MCSEnable = false,
 278 #  if (ANV_IS_HASWELL)
 279       .ShaderChannelSelectR = vk_to_gen_swizzle(pCreateInfo->components.r,
 280                                                 VK_COMPONENT_SWIZZLE_R),
 281       .ShaderChannelSelectG = vk_to_gen_swizzle(pCreateInfo->components.g,
 282                                                 VK_COMPONENT_SWIZZLE_G),
 283       .ShaderChannelSelectB = vk_to_gen_swizzle(pCreateInfo->components.b,
 284                                                 VK_COMPONENT_SWIZZLE_B),
 285       .ShaderChannelSelectA = vk_to_gen_swizzle(pCreateInfo->components.a,
 286                                                 VK_COMPONENT_SWIZZLE_A),
 287 #  else /* XXX: Seriously? */
 288       .RedClearColor = 0,
 289       .GreenClearColor = 0,
 290       .BlueClearColor = 0,
 291       .AlphaClearColor = 0,
 292 #  endif
 293       .ResourceMinLOD = 0.0,
 294       .SurfaceBaseAddress = { NULL, iview->offset },
 295    };
 296
 297    if (image->needs_nonrt_surface_state) {
 298       iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer);
 299
 300       surface_state.RenderCacheReadWriteMode = false;
 301
 302       /* For non render target surfaces, the hardware interprets field
 303        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 304        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 305        */
 306       surface_state.SurfaceMinLOD = range->baseMipLevel;
 307       surface_state.MIPCountLOD = range->levelCount - 1;
 308
 309       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
 310                                       &surface_state);
 311
 312       if (!device->info.has_llc)
 313          anv_state_clflush(iview->nonrt_surface_state);
 314    }
 315
 316    if (image->needs_color_rt_surface_state) {
 317       iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
 318
 319       surface_state.RenderCacheReadWriteMode = 0; /* Write only */
 320
 321       /* For render target surfaces, the hardware interprets field MIPCount/LOD as
 322        * LOD. The Broadwell PRM says:
 323        *
 324        *    MIPCountLOD defines the LOD that will be rendered into.
 325        *    SurfaceMinLOD is ignored.
 326        */
 327       surface_state.MIPCountLOD = range->baseMipLevel;
 328       surface_state.SurfaceMinLOD = 0;
 329
 330       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
 331                                       &surface_state);
 332       if (!device->info.has_llc)
 333          anv_state_clflush(iview->color_rt_surface_state);
 334    }
 335
 336    if (image->needs_storage_surface_state) {
 337       iview->storage_surface_state = alloc_surface_state(device, cmd_buffer);
 338
 339       surface_state.SurfaceFormat =
 340          isl_lower_storage_image_format(&device->isl_dev,
 341                                         format->surface_format);
 342
 343       surface_state.SurfaceMinLOD = range->baseMipLevel;
 344       surface_state.MIPCountLOD = range->levelCount - 1;
 345
 346       GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->storage_surface_state.map,
 347                                       &surface_state);
 348    }
 349 }