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vk: Fix 3DSTATE_WM_DEPTH_STENCIL for gen8
[mesa.git] / src / vulkan / gen8_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
34
35 static void
36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
37 {
38 static const uint32_t push_constant_opcodes[] = {
39 [VK_SHADER_STAGE_VERTEX] = 21,
40 [VK_SHADER_STAGE_TESS_CONTROL] = 25, /* HS */
41 [VK_SHADER_STAGE_TESS_EVALUATION] = 26, /* DS */
42 [VK_SHADER_STAGE_GEOMETRY] = 22,
43 [VK_SHADER_STAGE_FRAGMENT] = 23,
44 [VK_SHADER_STAGE_COMPUTE] = 0,
45 };
46
47 VkShaderStage stage;
48 VkShaderStageFlags flushed = 0;
49
50 for_each_bit(stage, cmd_buffer->state.push_constants_dirty) {
51 struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
52
53 if (state.offset == 0)
54 continue;
55
56 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
57 ._3DCommandSubOpcode = push_constant_opcodes[stage],
58 .ConstantBody = {
59 .PointerToConstantBuffer0 = { .offset = state.offset },
60 .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
61 });
62
63 flushed |= 1 << stage;
64 }
65
66 cmd_buffer->state.push_constants_dirty &= ~flushed;
67 }
68
69 #if ANV_GEN == 8
70 static void
71 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
72 uint32_t count, const VkViewport *viewports)
73 {
74 struct anv_state sf_clip_state =
75 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
76 struct anv_state cc_state =
77 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
78
79 for (uint32_t i = 0; i < count; i++) {
80 const VkViewport *vp = &viewports[i];
81
82 /* The gen7 state struct has just the matrix and guardband fields, the
83 * gen8 struct adds the min/max viewport fields. */
84 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
85 .ViewportMatrixElementm00 = vp->width / 2,
86 .ViewportMatrixElementm11 = vp->height / 2,
87 .ViewportMatrixElementm22 = (vp->maxDepth - vp->minDepth) / 2,
88 .ViewportMatrixElementm30 = vp->originX + vp->width / 2,
89 .ViewportMatrixElementm31 = vp->originY + vp->height / 2,
90 .ViewportMatrixElementm32 = (vp->maxDepth + vp->minDepth) / 2,
91 .XMinClipGuardband = -1.0f,
92 .XMaxClipGuardband = 1.0f,
93 .YMinClipGuardband = -1.0f,
94 .YMaxClipGuardband = 1.0f,
95 .XMinViewPort = vp->originX,
96 .XMaxViewPort = vp->originX + vp->width - 1,
97 .YMinViewPort = vp->originY,
98 .YMaxViewPort = vp->originY + vp->height - 1,
99 };
100
101 struct GENX(CC_VIEWPORT) cc_viewport = {
102 .MinimumDepth = vp->minDepth,
103 .MaximumDepth = vp->maxDepth
104 };
105
106 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
107 &sf_clip_viewport);
108 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 32, &cc_viewport);
109 }
110
111 anv_batch_emit(&cmd_buffer->batch,
112 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
113 .CCViewportPointer = cc_state.offset);
114 anv_batch_emit(&cmd_buffer->batch,
115 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
116 .SFClipViewportPointer = sf_clip_state.offset);
117 }
118
119 void
120 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
121 {
122 if (cmd_buffer->state.dynamic.viewport.count > 0) {
123 emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
124 cmd_buffer->state.dynamic.viewport.viewports);
125 } else {
126 /* If viewport count is 0, this is taken to mean "use the default" */
127 emit_viewport_state(cmd_buffer, 1,
128 &(VkViewport) {
129 .originX = 0.0f,
130 .originY = 0.0f,
131 .width = cmd_buffer->state.framebuffer->width,
132 .height = cmd_buffer->state.framebuffer->height,
133 .minDepth = 0.0f,
134 .maxDepth = 1.0f,
135 });
136 }
137 }
138 #endif
139
140 static void
141 cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
142 {
143 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
144 uint32_t *p;
145
146 uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
147
148 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
149
150 if (cmd_buffer->state.current_pipeline != _3D) {
151 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
152 #if ANV_GEN >= 9
153 .MaskBits = 3,
154 #endif
155 .PipelineSelection = _3D);
156 cmd_buffer->state.current_pipeline = _3D;
157 }
158
159 if (vb_emit) {
160 const uint32_t num_buffers = __builtin_popcount(vb_emit);
161 const uint32_t num_dwords = 1 + num_buffers * 4;
162
163 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
164 GENX(3DSTATE_VERTEX_BUFFERS));
165 uint32_t vb, i = 0;
166 for_each_bit(vb, vb_emit) {
167 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
168 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
169
170 struct GENX(VERTEX_BUFFER_STATE) state = {
171 .VertexBufferIndex = vb,
172 .MemoryObjectControlState = GENX(MOCS),
173 .AddressModifyEnable = true,
174 .BufferPitch = pipeline->binding_stride[vb],
175 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
176 .BufferSize = buffer->size - offset
177 };
178
179 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
180 i++;
181 }
182 }
183
184 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
185 /* If somebody compiled a pipeline after starting a command buffer the
186 * scratch bo may have grown since we started this cmd buffer (and
187 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
188 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
189 if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
190 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
191
192 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
193 }
194
195 #if ANV_GEN >= 9
196 /* On SKL+ the new constants don't take effect until the next corresponding
197 * 3DSTATE_BINDING_TABLE_POINTER_* command is parsed so we need to ensure
198 * that is sent. As it is, we re-emit binding tables but we could hold on
199 * to the offset of the most recent binding table and only re-emit the
200 * 3DSTATE_BINDING_TABLE_POINTER_* command.
201 */
202 cmd_buffer->state.descriptors_dirty |=
203 cmd_buffer->state.push_constants_dirty &
204 cmd_buffer->state.pipeline->active_stages;
205 #endif
206
207 if (cmd_buffer->state.push_constants_dirty)
208 cmd_buffer_flush_push_constants(cmd_buffer);
209
210 if (cmd_buffer->state.descriptors_dirty)
211 gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
212
213 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
214 gen8_cmd_buffer_emit_viewport(cmd_buffer);
215
216 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
217 gen7_cmd_buffer_emit_scissor(cmd_buffer);
218
219 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
220 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
221 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
222 struct GENX(3DSTATE_SF) sf = {
223 GENX(3DSTATE_SF_header),
224 .LineWidth = cmd_buffer->state.dynamic.line_width,
225 };
226 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
227 /* FIXME: gen9.fs */
228 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
229 }
230
231 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
232 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
233 bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
234 cmd_buffer->state.dynamic.depth_bias.slope_scaled != 0.0f;
235
236 uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
237 struct GENX(3DSTATE_RASTER) raster = {
238 GENX(3DSTATE_RASTER_header),
239 .GlobalDepthOffsetEnableSolid = enable_bias,
240 .GlobalDepthOffsetEnableWireframe = enable_bias,
241 .GlobalDepthOffsetEnablePoint = enable_bias,
242 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
243 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope_scaled,
244 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
245 };
246 GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
247 anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
248 pipeline->gen8.raster);
249 }
250
251 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
252 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
253 * across different state packets for gen8 and gen9. We handle that by
254 * using a big old #if switch here.
255 */
256 #if ANV_GEN == 8
257 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
258 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
259 struct anv_state cc_state =
260 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
261 GEN8_COLOR_CALC_STATE_length, 64);
262 struct GEN8_COLOR_CALC_STATE cc = {
263 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
264 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
265 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
266 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
267 .StencilReferenceValue =
268 cmd_buffer->state.dynamic.stencil_reference.front,
269 .BackFaceStencilReferenceValue =
270 cmd_buffer->state.dynamic.stencil_reference.back,
271 };
272 GEN8_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
273
274 anv_batch_emit(&cmd_buffer->batch,
275 GEN8_3DSTATE_CC_STATE_POINTERS,
276 .ColorCalcStatePointer = cc_state.offset,
277 .ColorCalcStatePointerValid = true);
278 }
279
280 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
281 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
282 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
283 uint32_t wm_depth_stencil_dw[GEN8_3DSTATE_WM_DEPTH_STENCIL_length];
284
285 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
286 GEN8_3DSTATE_WM_DEPTH_STENCIL_header,
287
288 /* Is this what we need to do? */
289 .StencilBufferWriteEnable =
290 cmd_buffer->state.dynamic.stencil_write_mask.front != 0,
291
292 .StencilTestMask =
293 cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
294 .StencilWriteMask =
295 cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
296
297 .BackfaceStencilTestMask =
298 cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
299 .BackfaceStencilWriteMask =
300 cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
301 };
302 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, wm_depth_stencil_dw,
303 &wm_depth_stencil);
304
305 anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
306 pipeline->gen8.wm_depth_stencil);
307 }
308 #else
309 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
310 struct anv_state cc_state =
311 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
312 GEN9_COLOR_CALC_STATE_length, 64);
313 struct GEN9_COLOR_CALC_STATE cc = {
314 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
315 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
316 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
317 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
318 };
319 GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
320
321 anv_batch_emit(&cmd_buffer->batch,
322 GEN9_3DSTATE_CC_STATE_POINTERS,
323 .ColorCalcStatePointer = cc_state.offset,
324 .ColorCalcStatePointerValid = true);
325 }
326
327 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
328 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
329 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
330 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
331 uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
332 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
333 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
334 GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
335
336 .StencilBufferWriteEnable = d->stencil_write_mask.front != 0,
337
338 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
339 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
340
341 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
342 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
343
344 .StencilReferenceValue = d->stencil_reference.front,
345 .BackfaceStencilReferenceValue = d->stencil_reference.back
346 };
347 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
348
349 anv_batch_emit_merge(&cmd_buffer->batch, dwords,
350 pipeline->gen9.wm_depth_stencil);
351 }
352 #endif
353
354 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
355 ANV_CMD_DIRTY_INDEX_BUFFER)) {
356 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
357 .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
358 .CutIndex = cmd_buffer->state.restart_index,
359 );
360 }
361
362 cmd_buffer->state.vb_dirty &= ~vb_emit;
363 cmd_buffer->state.dirty = 0;
364 }
365
366 void genX(CmdDraw)(
367 VkCmdBuffer cmdBuffer,
368 uint32_t vertexCount,
369 uint32_t instanceCount,
370 uint32_t firstVertex,
371 uint32_t firstInstance)
372 {
373 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
374
375 cmd_buffer_flush_state(cmd_buffer);
376
377 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
378 .VertexAccessType = SEQUENTIAL,
379 .VertexCountPerInstance = vertexCount,
380 .StartVertexLocation = firstVertex,
381 .InstanceCount = instanceCount,
382 .StartInstanceLocation = firstInstance,
383 .BaseVertexLocation = 0);
384 }
385
386 void genX(CmdDrawIndexed)(
387 VkCmdBuffer cmdBuffer,
388 uint32_t indexCount,
389 uint32_t instanceCount,
390 uint32_t firstIndex,
391 int32_t vertexOffset,
392 uint32_t firstInstance)
393 {
394 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
395
396 cmd_buffer_flush_state(cmd_buffer);
397
398 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
399 .VertexAccessType = RANDOM,
400 .VertexCountPerInstance = indexCount,
401 .StartVertexLocation = firstIndex,
402 .InstanceCount = instanceCount,
403 .StartInstanceLocation = firstInstance,
404 .BaseVertexLocation = vertexOffset);
405 }
406
407 static void
408 emit_lrm(struct anv_batch *batch,
409 uint32_t reg, struct anv_bo *bo, uint32_t offset)
410 {
411 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
412 .RegisterAddress = reg,
413 .MemoryAddress = { bo, offset });
414 }
415
416 static void
417 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
418 {
419 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
420 .RegisterOffset = reg,
421 .DataDWord = imm);
422 }
423
424 /* Auto-Draw / Indirect Registers */
425 #define GEN7_3DPRIM_END_OFFSET 0x2420
426 #define GEN7_3DPRIM_START_VERTEX 0x2430
427 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
428 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
429 #define GEN7_3DPRIM_START_INSTANCE 0x243C
430 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
431
432 void genX(CmdDrawIndirect)(
433 VkCmdBuffer cmdBuffer,
434 VkBuffer _buffer,
435 VkDeviceSize offset,
436 uint32_t count,
437 uint32_t stride)
438 {
439 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
440 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
441 struct anv_bo *bo = buffer->bo;
442 uint32_t bo_offset = buffer->offset + offset;
443
444 cmd_buffer_flush_state(cmd_buffer);
445
446 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
447 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
448 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
449 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
450 emit_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
451
452 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
453 .IndirectParameterEnable = true,
454 .VertexAccessType = SEQUENTIAL);
455 }
456
457 void genX(CmdBindIndexBuffer)(
458 VkCmdBuffer cmdBuffer,
459 VkBuffer _buffer,
460 VkDeviceSize offset,
461 VkIndexType indexType)
462 {
463 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
464 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
465
466 static const uint32_t vk_to_gen_index_type[] = {
467 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
468 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
469 };
470
471 static const uint32_t restart_index_for_type[] = {
472 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
473 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
474 };
475
476 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
477
478 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
479 .IndexFormat = vk_to_gen_index_type[indexType],
480 .MemoryObjectControlState = GENX(MOCS),
481 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
482 .BufferSize = buffer->size - offset);
483
484 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
485 }
486
487 static VkResult
488 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
489 {
490 struct anv_device *device = cmd_buffer->device;
491 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
492 struct anv_state surfaces = { 0, }, samplers = { 0, };
493 VkResult result;
494
495 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
496 VK_SHADER_STAGE_COMPUTE, &samplers);
497 if (result != VK_SUCCESS)
498 return result;
499 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
500 VK_SHADER_STAGE_COMPUTE, &surfaces);
501 if (result != VK_SUCCESS)
502 return result;
503
504 struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
505 .KernelStartPointer = pipeline->cs_simd,
506 .KernelStartPointerHigh = 0,
507 .BindingTablePointer = surfaces.offset,
508 .BindingTableEntryCount = 0,
509 .SamplerStatePointer = samplers.offset,
510 .SamplerCount = 0,
511 .NumberofThreadsinGPGPUThreadGroup = 0 /* FIXME: Really? */
512 };
513
514 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
515 struct anv_state state =
516 anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
517
518 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(NULL, state.map, &desc);
519
520 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
521 .InterfaceDescriptorTotalLength = size,
522 .InterfaceDescriptorDataStartAddress = state.offset);
523
524 return VK_SUCCESS;
525 }
526
527 static void
528 cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
529 {
530 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
531 VkResult result;
532
533 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
534
535 if (cmd_buffer->state.current_pipeline != GPGPU) {
536 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
537 #if ANV_GEN >= 9
538 .MaskBits = 3,
539 #endif
540 .PipelineSelection = GPGPU);
541 cmd_buffer->state.current_pipeline = GPGPU;
542 }
543
544 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
545 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
546
547 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
548 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
549 result = flush_compute_descriptor_set(cmd_buffer);
550 assert(result == VK_SUCCESS);
551 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE;
552 }
553
554 cmd_buffer->state.compute_dirty = 0;
555 }
556
557 void genX(CmdDrawIndexedIndirect)(
558 VkCmdBuffer cmdBuffer,
559 VkBuffer _buffer,
560 VkDeviceSize offset,
561 uint32_t count,
562 uint32_t stride)
563 {
564 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
565 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
566 struct anv_bo *bo = buffer->bo;
567 uint32_t bo_offset = buffer->offset + offset;
568
569 cmd_buffer_flush_state(cmd_buffer);
570
571 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
572 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
573 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
574 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
575 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
576
577 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
578 .IndirectParameterEnable = true,
579 .VertexAccessType = RANDOM);
580 }
581
582 void genX(CmdDispatch)(
583 VkCmdBuffer cmdBuffer,
584 uint32_t x,
585 uint32_t y,
586 uint32_t z)
587 {
588 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
589 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
590 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
591
592 cmd_buffer_flush_compute_state(cmd_buffer);
593
594 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
595 .SIMDSize = prog_data->simd_size / 16,
596 .ThreadDepthCounterMaximum = 0,
597 .ThreadHeightCounterMaximum = 0,
598 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
599 .ThreadGroupIDXDimension = x,
600 .ThreadGroupIDYDimension = y,
601 .ThreadGroupIDZDimension = z,
602 .RightExecutionMask = pipeline->cs_right_mask,
603 .BottomExecutionMask = 0xffffffff);
604
605 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
606 }
607
608 #define GPGPU_DISPATCHDIMX 0x2500
609 #define GPGPU_DISPATCHDIMY 0x2504
610 #define GPGPU_DISPATCHDIMZ 0x2508
611
612 void genX(CmdDispatchIndirect)(
613 VkCmdBuffer cmdBuffer,
614 VkBuffer _buffer,
615 VkDeviceSize offset)
616 {
617 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
618 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
619 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
620 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
621 struct anv_bo *bo = buffer->bo;
622 uint32_t bo_offset = buffer->offset + offset;
623
624 cmd_buffer_flush_compute_state(cmd_buffer);
625
626 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
627 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
628 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
629
630 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
631 .IndirectParameterEnable = true,
632 .SIMDSize = prog_data->simd_size / 16,
633 .ThreadDepthCounterMaximum = 0,
634 .ThreadHeightCounterMaximum = 0,
635 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
636 .RightExecutionMask = pipeline->cs_right_mask,
637 .BottomExecutionMask = 0xffffffff);
638
639 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
640 }
641
642 static void
643 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
644 {
645 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
646 const struct anv_image_view *iview =
647 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
648 const struct anv_image *image = iview ? iview->image : NULL;
649 const bool has_depth = iview && iview->format->depth_format;
650 const bool has_stencil = iview && iview->format->has_stencil;
651
652 /* FIXME: Implement the PMA stall W/A */
653 /* FIXME: Width and Height are wrong */
654
655 /* Emit 3DSTATE_DEPTH_BUFFER */
656 if (has_depth) {
657 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
658 .SurfaceType = SURFTYPE_2D,
659 .DepthWriteEnable = iview->format->depth_format,
660 .StencilWriteEnable = has_stencil,
661 .HierarchicalDepthBufferEnable = false,
662 .SurfaceFormat = iview->format->depth_format,
663 .SurfacePitch = image->depth_surface.stride - 1,
664 .SurfaceBaseAddress = {
665 .bo = image->bo,
666 .offset = image->depth_surface.offset,
667 },
668 .Height = fb->height - 1,
669 .Width = fb->width - 1,
670 .LOD = 0,
671 .Depth = 1 - 1,
672 .MinimumArrayElement = 0,
673 .DepthBufferObjectControlState = GENX(MOCS),
674 .RenderTargetViewExtent = 1 - 1,
675 .SurfaceQPitch = image->depth_surface.qpitch >> 2);
676 } else {
677 /* Even when no depth buffer is present, the hardware requires that
678 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
679 *
680 * If a null depth buffer is bound, the driver must instead bind depth as:
681 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
682 * 3DSTATE_DEPTH.Width = 1
683 * 3DSTATE_DEPTH.Height = 1
684 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
685 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
686 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
687 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
688 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
689 *
690 * The PRM is wrong, though. The width and height must be programmed to
691 * actual framebuffer's width and height, even when neither depth buffer
692 * nor stencil buffer is present.
693 */
694 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
695 .SurfaceType = SURFTYPE_2D,
696 .SurfaceFormat = D16_UNORM,
697 .Width = fb->width - 1,
698 .Height = fb->height - 1,
699 .StencilWriteEnable = has_stencil);
700 }
701
702 /* Emit 3DSTATE_STENCIL_BUFFER */
703 if (has_stencil) {
704 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
705 .StencilBufferEnable = true,
706 .StencilBufferObjectControlState = GENX(MOCS),
707
708 /* Stencil buffers have strange pitch. The PRM says:
709 *
710 * The pitch must be set to 2x the value computed based on width,
711 * as the stencil buffer is stored with two rows interleaved.
712 */
713 .SurfacePitch = 2 * image->stencil_surface.stride - 1,
714
715 .SurfaceBaseAddress = {
716 .bo = image->bo,
717 .offset = image->offset + image->stencil_surface.offset,
718 },
719 .SurfaceQPitch = image->stencil_surface.stride >> 2);
720 } else {
721 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
722 }
723
724 /* Disable hierarchial depth buffers. */
725 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
726
727 /* Clear the clear params. */
728 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
729 }
730
731 void
732 genX(cmd_buffer_begin_subpass)(struct anv_cmd_buffer *cmd_buffer,
733 struct anv_subpass *subpass)
734 {
735 cmd_buffer->state.subpass = subpass;
736
737 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
738
739 cmd_buffer_emit_depth_stencil(cmd_buffer);
740 }
741
742 void genX(CmdBeginRenderPass)(
743 VkCmdBuffer cmdBuffer,
744 const VkRenderPassBeginInfo* pRenderPassBegin,
745 VkRenderPassContents contents)
746 {
747 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
748 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
749 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
750
751 cmd_buffer->state.framebuffer = framebuffer;
752 cmd_buffer->state.pass = pass;
753
754 const VkRect2D *render_area = &pRenderPassBegin->renderArea;
755
756 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
757 .ClippedDrawingRectangleYMin = render_area->offset.y,
758 .ClippedDrawingRectangleXMin = render_area->offset.x,
759 .ClippedDrawingRectangleYMax =
760 render_area->offset.y + render_area->extent.height - 1,
761 .ClippedDrawingRectangleXMax =
762 render_area->offset.x + render_area->extent.width - 1,
763 .DrawingRectangleOriginY = 0,
764 .DrawingRectangleOriginX = 0);
765
766 anv_cmd_buffer_clear_attachments(cmd_buffer, pass,
767 pRenderPassBegin->pClearValues);
768
769 genX(cmd_buffer_begin_subpass)(cmd_buffer, pass->subpasses);
770 }
771
772 void genX(CmdNextSubpass)(
773 VkCmdBuffer cmdBuffer,
774 VkRenderPassContents contents)
775 {
776 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
777
778 assert(cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
779
780 genX(cmd_buffer_begin_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
781 }
782
783 void genX(CmdEndRenderPass)(
784 VkCmdBuffer cmdBuffer)
785 {
786 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
787
788 /* Emit a flushing pipe control at the end of a pass. This is kind of a
789 * hack but it ensures that render targets always actually get written.
790 * Eventually, we should do flushing based on image format transitions
791 * or something of that nature.
792 */
793 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
794 .PostSyncOperation = NoWrite,
795 .RenderTargetCacheFlushEnable = true,
796 .InstructionCacheInvalidateEnable = true,
797 .DepthCacheFlushEnable = true,
798 .VFCacheInvalidationEnable = true,
799 .TextureCacheInvalidationEnable = true,
800 .CommandStreamerStallEnable = true);
801 }
802
803 static void
804 emit_ps_depth_count(struct anv_batch *batch,
805 struct anv_bo *bo, uint32_t offset)
806 {
807 anv_batch_emit(batch, GENX(PIPE_CONTROL),
808 .DestinationAddressType = DAT_PPGTT,
809 .PostSyncOperation = WritePSDepthCount,
810 .Address = { bo, offset }); /* FIXME: This is only lower 32 bits */
811 }
812
813 void genX(CmdBeginQuery)(
814 VkCmdBuffer cmdBuffer,
815 VkQueryPool queryPool,
816 uint32_t slot,
817 VkQueryControlFlags flags)
818 {
819 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
820 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
821
822 switch (pool->type) {
823 case VK_QUERY_TYPE_OCCLUSION:
824 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
825 slot * sizeof(struct anv_query_pool_slot));
826 break;
827
828 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
829 default:
830 unreachable("");
831 }
832 }
833
834 void genX(CmdEndQuery)(
835 VkCmdBuffer cmdBuffer,
836 VkQueryPool queryPool,
837 uint32_t slot)
838 {
839 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
840 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
841
842 switch (pool->type) {
843 case VK_QUERY_TYPE_OCCLUSION:
844 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
845 slot * sizeof(struct anv_query_pool_slot) + 8);
846 break;
847
848 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
849 default:
850 unreachable("");
851 }
852 }
853
854 #define TIMESTAMP 0x2358
855
856 void genX(CmdWriteTimestamp)(
857 VkCmdBuffer cmdBuffer,
858 VkTimestampType timestampType,
859 VkBuffer destBuffer,
860 VkDeviceSize destOffset)
861 {
862 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
863 ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
864 struct anv_bo *bo = buffer->bo;
865
866 switch (timestampType) {
867 case VK_TIMESTAMP_TYPE_TOP:
868 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
869 .RegisterAddress = TIMESTAMP,
870 .MemoryAddress = { bo, buffer->offset + destOffset });
871 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
872 .RegisterAddress = TIMESTAMP + 4,
873 .MemoryAddress = { bo, buffer->offset + destOffset + 4 });
874 break;
875
876 case VK_TIMESTAMP_TYPE_BOTTOM:
877 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
878 .DestinationAddressType = DAT_PPGTT,
879 .PostSyncOperation = WriteTimestamp,
880 .Address = /* FIXME: This is only lower 32 bits */
881 { bo, buffer->offset + destOffset });
882 break;
883
884 default:
885 break;
886 }
887 }
888
889 #define alu_opcode(v) __gen_field((v), 20, 31)
890 #define alu_operand1(v) __gen_field((v), 10, 19)
891 #define alu_operand2(v) __gen_field((v), 0, 9)
892 #define alu(opcode, operand1, operand2) \
893 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
894
895 #define OPCODE_NOOP 0x000
896 #define OPCODE_LOAD 0x080
897 #define OPCODE_LOADINV 0x480
898 #define OPCODE_LOAD0 0x081
899 #define OPCODE_LOAD1 0x481
900 #define OPCODE_ADD 0x100
901 #define OPCODE_SUB 0x101
902 #define OPCODE_AND 0x102
903 #define OPCODE_OR 0x103
904 #define OPCODE_XOR 0x104
905 #define OPCODE_STORE 0x180
906 #define OPCODE_STOREINV 0x580
907
908 #define OPERAND_R0 0x00
909 #define OPERAND_R1 0x01
910 #define OPERAND_R2 0x02
911 #define OPERAND_R3 0x03
912 #define OPERAND_R4 0x04
913 #define OPERAND_SRCA 0x20
914 #define OPERAND_SRCB 0x21
915 #define OPERAND_ACCU 0x31
916 #define OPERAND_ZF 0x32
917 #define OPERAND_CF 0x33
918
919 #define CS_GPR(n) (0x2600 + (n) * 8)
920
921 static void
922 emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
923 struct anv_bo *bo, uint32_t offset)
924 {
925 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
926 .RegisterAddress = reg,
927 .MemoryAddress = { bo, offset });
928 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
929 .RegisterAddress = reg + 4,
930 .MemoryAddress = { bo, offset + 4 });
931 }
932
933 void genX(CmdCopyQueryPoolResults)(
934 VkCmdBuffer cmdBuffer,
935 VkQueryPool queryPool,
936 uint32_t startQuery,
937 uint32_t queryCount,
938 VkBuffer destBuffer,
939 VkDeviceSize destOffset,
940 VkDeviceSize destStride,
941 VkQueryResultFlags flags)
942 {
943 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
944 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
945 ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
946 uint32_t slot_offset, dst_offset;
947
948 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
949 /* Where is the availabilty info supposed to go? */
950 anv_finishme("VK_QUERY_RESULT_WITH_AVAILABILITY_BIT");
951 return;
952 }
953
954 assert(pool->type == VK_QUERY_TYPE_OCCLUSION);
955
956 /* FIXME: If we're not waiting, should we just do this on the CPU? */
957 if (flags & VK_QUERY_RESULT_WAIT_BIT)
958 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
959 .CommandStreamerStallEnable = true,
960 .StallAtPixelScoreboard = true);
961
962 dst_offset = buffer->offset + destOffset;
963 for (uint32_t i = 0; i < queryCount; i++) {
964
965 slot_offset = (startQuery + i) * sizeof(struct anv_query_pool_slot);
966
967 emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0), &pool->bo, slot_offset);
968 emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(1), &pool->bo, slot_offset + 8);
969
970 /* FIXME: We need to clamp the result for 32 bit. */
971
972 uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(MI_MATH));
973 dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
974 dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
975 dw[3] = alu(OPCODE_SUB, 0, 0);
976 dw[4] = alu(OPCODE_STORE, OPERAND_R2, OPERAND_ACCU);
977
978 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
979 .RegisterAddress = CS_GPR(2),
980 /* FIXME: This is only lower 32 bits */
981 .MemoryAddress = { buffer->bo, dst_offset });
982
983 if (flags & VK_QUERY_RESULT_64_BIT)
984 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
985 .RegisterAddress = CS_GPR(2) + 4,
986 /* FIXME: This is only lower 32 bits */
987 .MemoryAddress = { buffer->bo, dst_offset + 4 });
988
989 dst_offset += destStride;
990 }
991 }