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anv/gen8: Set SLM size in interface descriptor
[mesa.git] / src / vulkan / gen8_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
34
35 static uint32_t
36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
37 {
38 static const uint32_t push_constant_opcodes[] = {
39 [MESA_SHADER_VERTEX] = 21,
40 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
41 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
42 [MESA_SHADER_GEOMETRY] = 22,
43 [MESA_SHADER_FRAGMENT] = 23,
44 [MESA_SHADER_COMPUTE] = 0,
45 };
46
47 VkShaderStageFlags flushed = 0;
48
49 anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
50 if (stage == MESA_SHADER_COMPUTE)
51 continue;
52
53 struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
54
55 if (state.offset == 0)
56 continue;
57
58 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
59 ._3DCommandSubOpcode = push_constant_opcodes[stage],
60 .ConstantBody = {
61 .PointerToConstantBuffer0 = { .offset = state.offset },
62 .ConstantBuffer0ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
63 });
64
65 flushed |= mesa_to_vk_shader_stage(stage);
66 }
67
68 cmd_buffer->state.push_constants_dirty &= ~flushed;
69
70 return flushed;
71 }
72
73 #if ANV_GEN == 8
74 static void
75 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
76 uint32_t count, const VkViewport *viewports)
77 {
78 struct anv_state sf_clip_state =
79 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
80 struct anv_state cc_state =
81 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
82
83 for (uint32_t i = 0; i < count; i++) {
84 const VkViewport *vp = &viewports[i];
85
86 /* The gen7 state struct has just the matrix and guardband fields, the
87 * gen8 struct adds the min/max viewport fields. */
88 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
89 .ViewportMatrixElementm00 = vp->width / 2,
90 .ViewportMatrixElementm11 = vp->height / 2,
91 .ViewportMatrixElementm22 = 1.0,
92 .ViewportMatrixElementm30 = vp->x + vp->width / 2,
93 .ViewportMatrixElementm31 = vp->y + vp->height / 2,
94 .ViewportMatrixElementm32 = 0.0,
95 .XMinClipGuardband = -1.0f,
96 .XMaxClipGuardband = 1.0f,
97 .YMinClipGuardband = -1.0f,
98 .YMaxClipGuardband = 1.0f,
99 .XMinViewPort = vp->x,
100 .XMaxViewPort = vp->x + vp->width - 1,
101 .YMinViewPort = vp->y,
102 .YMaxViewPort = vp->y + vp->height - 1,
103 };
104
105 struct GENX(CC_VIEWPORT) cc_viewport = {
106 .MinimumDepth = vp->minDepth,
107 .MaximumDepth = vp->maxDepth
108 };
109
110 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
111 &sf_clip_viewport);
112 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
113 }
114
115 if (!cmd_buffer->device->info.has_llc) {
116 anv_state_clflush(sf_clip_state);
117 anv_state_clflush(cc_state);
118 }
119
120 anv_batch_emit(&cmd_buffer->batch,
121 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
122 .CCViewportPointer = cc_state.offset);
123 anv_batch_emit(&cmd_buffer->batch,
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
125 .SFClipViewportPointer = sf_clip_state.offset);
126 }
127
128 void
129 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
130 {
131 if (cmd_buffer->state.dynamic.viewport.count > 0) {
132 emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
133 cmd_buffer->state.dynamic.viewport.viewports);
134 } else {
135 /* If viewport count is 0, this is taken to mean "use the default" */
136 emit_viewport_state(cmd_buffer, 1,
137 &(VkViewport) {
138 .x = 0.0f,
139 .y = 0.0f,
140 .width = cmd_buffer->state.framebuffer->width,
141 .height = cmd_buffer->state.framebuffer->height,
142 .minDepth = 0.0f,
143 .maxDepth = 1.0f,
144 });
145 }
146 }
147 #endif
148
149 static void
150 emit_lrm(struct anv_batch *batch,
151 uint32_t reg, struct anv_bo *bo, uint32_t offset)
152 {
153 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
154 .RegisterAddress = reg,
155 .MemoryAddress = { bo, offset });
156 }
157
158 static void
159 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
160 {
161 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
162 .RegisterOffset = reg,
163 .DataDWord = imm);
164 }
165
166 #define GEN8_L3CNTLREG 0x7034
167
168 static void
169 config_l3(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
170 {
171 /* References for GL state:
172 *
173 * - commits e307cfa..228d5a3
174 * - src/mesa/drivers/dri/i965/gen7_l3_state.c
175 */
176
177 uint32_t val = enable_slm ?
178 /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */
179 0x60000021 :
180 /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */
181 0x60000060;
182 bool changed = cmd_buffer->state.current_l3_config != val;
183
184 if (changed) {
185 /* According to the hardware docs, the L3 partitioning can only be changed
186 * while the pipeline is completely drained and the caches are flushed,
187 * which involves a first PIPE_CONTROL flush which stalls the pipeline and
188 * initiates invalidation of the relevant caches...
189 */
190 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
191 .TextureCacheInvalidationEnable = true,
192 .ConstantCacheInvalidationEnable = true,
193 .InstructionCacheInvalidateEnable = true,
194 .DCFlushEnable = true,
195 .PostSyncOperation = NoWrite,
196 .CommandStreamerStallEnable = true);
197
198 /* ...followed by a second stalling flush which guarantees that
199 * invalidation is complete when the L3 configuration registers are
200 * modified.
201 */
202 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
203 .DCFlushEnable = true,
204 .PostSyncOperation = NoWrite,
205 .CommandStreamerStallEnable = true);
206
207 emit_lri(&cmd_buffer->batch, GEN8_L3CNTLREG, val);
208 cmd_buffer->state.current_l3_config = val;
209 }
210 }
211
212 static void
213 flush_pipeline_select_3d(struct anv_cmd_buffer *cmd_buffer)
214 {
215 config_l3(cmd_buffer, false);
216
217 if (cmd_buffer->state.current_pipeline != _3D) {
218 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
219 #if ANV_GEN >= 9
220 .MaskBits = 3,
221 #endif
222 .PipelineSelection = _3D);
223 cmd_buffer->state.current_pipeline = _3D;
224 }
225 }
226
227 static void
228 cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
229 {
230 struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
231 uint32_t *p;
232
233 uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
234
235 assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
236
237 flush_pipeline_select_3d(cmd_buffer);
238
239 if (vb_emit) {
240 const uint32_t num_buffers = __builtin_popcount(vb_emit);
241 const uint32_t num_dwords = 1 + num_buffers * 4;
242
243 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
244 GENX(3DSTATE_VERTEX_BUFFERS));
245 uint32_t vb, i = 0;
246 for_each_bit(vb, vb_emit) {
247 struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
248 uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
249
250 struct GENX(VERTEX_BUFFER_STATE) state = {
251 .VertexBufferIndex = vb,
252 .MemoryObjectControlState = GENX(MOCS),
253 .AddressModifyEnable = true,
254 .BufferPitch = pipeline->binding_stride[vb],
255 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
256 .BufferSize = buffer->size - offset
257 };
258
259 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
260 i++;
261 }
262 }
263
264 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
265 /* If somebody compiled a pipeline after starting a command buffer the
266 * scratch bo may have grown since we started this cmd buffer (and
267 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
268 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
269 if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
270 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
271
272 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
273 }
274
275 /* We emit the binding tables and sampler tables first, then emit push
276 * constants and then finally emit binding table and sampler table
277 * pointers. It has to happen in this order, since emitting the binding
278 * tables may change the push constants (in case of storage images). After
279 * emitting push constants, on SKL+ we have to emit the corresponding
280 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
281 */
282 uint32_t dirty = 0;
283 if (cmd_buffer->state.descriptors_dirty)
284 dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
285
286 if (cmd_buffer->state.push_constants_dirty)
287 dirty |= cmd_buffer_flush_push_constants(cmd_buffer);
288
289 if (dirty)
290 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
291
292 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
293 gen8_cmd_buffer_emit_viewport(cmd_buffer);
294
295 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
296 gen7_cmd_buffer_emit_scissor(cmd_buffer);
297
298 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
299 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
300 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
301 struct GENX(3DSTATE_SF) sf = {
302 GENX(3DSTATE_SF_header),
303 .LineWidth = cmd_buffer->state.dynamic.line_width,
304 };
305 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
306 /* FIXME: gen9.fs */
307 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
308 }
309
310 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
311 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
312 bool enable_bias = cmd_buffer->state.dynamic.depth_bias.bias != 0.0f ||
313 cmd_buffer->state.dynamic.depth_bias.slope != 0.0f;
314
315 uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
316 struct GENX(3DSTATE_RASTER) raster = {
317 GENX(3DSTATE_RASTER_header),
318 .GlobalDepthOffsetEnableSolid = enable_bias,
319 .GlobalDepthOffsetEnableWireframe = enable_bias,
320 .GlobalDepthOffsetEnablePoint = enable_bias,
321 .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
322 .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
323 .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
324 };
325 GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
326 anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
327 pipeline->gen8.raster);
328 }
329
330 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
331 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
332 * across different state packets for gen8 and gen9. We handle that by
333 * using a big old #if switch here.
334 */
335 #if ANV_GEN == 8
336 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
337 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
338 struct anv_state cc_state =
339 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
340 GEN8_COLOR_CALC_STATE_length * 4,
341 64);
342 struct GEN8_COLOR_CALC_STATE cc = {
343 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
344 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
345 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
346 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
347 .StencilReferenceValue =
348 cmd_buffer->state.dynamic.stencil_reference.front,
349 .BackFaceStencilReferenceValue =
350 cmd_buffer->state.dynamic.stencil_reference.back,
351 };
352 GEN8_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
353
354 if (!cmd_buffer->device->info.has_llc)
355 anv_state_clflush(cc_state);
356
357 anv_batch_emit(&cmd_buffer->batch,
358 GEN8_3DSTATE_CC_STATE_POINTERS,
359 .ColorCalcStatePointer = cc_state.offset,
360 .ColorCalcStatePointerValid = true);
361 }
362
363 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
364 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
365 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
366 uint32_t wm_depth_stencil_dw[GEN8_3DSTATE_WM_DEPTH_STENCIL_length];
367
368 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
369 GEN8_3DSTATE_WM_DEPTH_STENCIL_header,
370
371 /* Is this what we need to do? */
372 .StencilBufferWriteEnable =
373 cmd_buffer->state.dynamic.stencil_write_mask.front != 0,
374
375 .StencilTestMask =
376 cmd_buffer->state.dynamic.stencil_compare_mask.front & 0xff,
377 .StencilWriteMask =
378 cmd_buffer->state.dynamic.stencil_write_mask.front & 0xff,
379
380 .BackfaceStencilTestMask =
381 cmd_buffer->state.dynamic.stencil_compare_mask.back & 0xff,
382 .BackfaceStencilWriteMask =
383 cmd_buffer->state.dynamic.stencil_write_mask.back & 0xff,
384 };
385 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, wm_depth_stencil_dw,
386 &wm_depth_stencil);
387
388 anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
389 pipeline->gen8.wm_depth_stencil);
390 }
391 #else
392 if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
393 struct anv_state cc_state =
394 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
395 GEN9_COLOR_CALC_STATE_length * 4,
396 64);
397 struct GEN9_COLOR_CALC_STATE cc = {
398 .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
399 .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
400 .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
401 .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
402 };
403 GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
404
405 if (!cmd_buffer->device->info.has_llc)
406 anv_state_clflush(cc_state);
407
408 anv_batch_emit(&cmd_buffer->batch,
409 GEN9_3DSTATE_CC_STATE_POINTERS,
410 .ColorCalcStatePointer = cc_state.offset,
411 .ColorCalcStatePointerValid = true);
412 }
413
414 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
415 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
416 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
417 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
418 uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
419 struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
420 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
421 GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
422
423 .StencilBufferWriteEnable = d->stencil_write_mask.front != 0,
424
425 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
426 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
427
428 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
429 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
430
431 .StencilReferenceValue = d->stencil_reference.front,
432 .BackfaceStencilReferenceValue = d->stencil_reference.back
433 };
434 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
435
436 anv_batch_emit_merge(&cmd_buffer->batch, dwords,
437 pipeline->gen9.wm_depth_stencil);
438 }
439 #endif
440
441 if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
442 ANV_CMD_DIRTY_INDEX_BUFFER)) {
443 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
444 .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
445 .CutIndex = cmd_buffer->state.restart_index,
446 );
447 }
448
449 cmd_buffer->state.vb_dirty &= ~vb_emit;
450 cmd_buffer->state.dirty = 0;
451 }
452
453 void genX(CmdDraw)(
454 VkCommandBuffer commandBuffer,
455 uint32_t vertexCount,
456 uint32_t instanceCount,
457 uint32_t firstVertex,
458 uint32_t firstInstance)
459 {
460 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
461
462 cmd_buffer_flush_state(cmd_buffer);
463
464 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
465 .VertexAccessType = SEQUENTIAL,
466 .VertexCountPerInstance = vertexCount,
467 .StartVertexLocation = firstVertex,
468 .InstanceCount = instanceCount,
469 .StartInstanceLocation = firstInstance,
470 .BaseVertexLocation = 0);
471 }
472
473 void genX(CmdDrawIndexed)(
474 VkCommandBuffer commandBuffer,
475 uint32_t indexCount,
476 uint32_t instanceCount,
477 uint32_t firstIndex,
478 int32_t vertexOffset,
479 uint32_t firstInstance)
480 {
481 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
482
483 cmd_buffer_flush_state(cmd_buffer);
484
485 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
486 .VertexAccessType = RANDOM,
487 .VertexCountPerInstance = indexCount,
488 .StartVertexLocation = firstIndex,
489 .InstanceCount = instanceCount,
490 .StartInstanceLocation = firstInstance,
491 .BaseVertexLocation = vertexOffset);
492 }
493
494 /* Auto-Draw / Indirect Registers */
495 #define GEN7_3DPRIM_END_OFFSET 0x2420
496 #define GEN7_3DPRIM_START_VERTEX 0x2430
497 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
498 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
499 #define GEN7_3DPRIM_START_INSTANCE 0x243C
500 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
501
502 void genX(CmdDrawIndirect)(
503 VkCommandBuffer commandBuffer,
504 VkBuffer _buffer,
505 VkDeviceSize offset,
506 uint32_t drawCount,
507 uint32_t stride)
508 {
509 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
510 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
511 struct anv_bo *bo = buffer->bo;
512 uint32_t bo_offset = buffer->offset + offset;
513
514 cmd_buffer_flush_state(cmd_buffer);
515
516 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
517 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
518 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
519 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
520 emit_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
521
522 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
523 .IndirectParameterEnable = true,
524 .VertexAccessType = SEQUENTIAL);
525 }
526
527 void genX(CmdBindIndexBuffer)(
528 VkCommandBuffer commandBuffer,
529 VkBuffer _buffer,
530 VkDeviceSize offset,
531 VkIndexType indexType)
532 {
533 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
534 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
535
536 static const uint32_t vk_to_gen_index_type[] = {
537 [VK_INDEX_TYPE_UINT16] = INDEX_WORD,
538 [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
539 };
540
541 static const uint32_t restart_index_for_type[] = {
542 [VK_INDEX_TYPE_UINT16] = UINT16_MAX,
543 [VK_INDEX_TYPE_UINT32] = UINT32_MAX,
544 };
545
546 cmd_buffer->state.restart_index = restart_index_for_type[indexType];
547
548 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
549 .IndexFormat = vk_to_gen_index_type[indexType],
550 .MemoryObjectControlState = GENX(MOCS),
551 .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
552 .BufferSize = buffer->size - offset);
553
554 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
555 }
556
557 static VkResult
558 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
559 {
560 struct anv_device *device = cmd_buffer->device;
561 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
562 struct anv_state surfaces = { 0, }, samplers = { 0, };
563 VkResult result;
564
565 result = anv_cmd_buffer_emit_samplers(cmd_buffer,
566 MESA_SHADER_COMPUTE, &samplers);
567 if (result != VK_SUCCESS)
568 return result;
569 result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
570 MESA_SHADER_COMPUTE, &surfaces);
571 if (result != VK_SUCCESS)
572 return result;
573
574 struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
575
576 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
577 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
578
579 unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
580 unsigned push_constant_data_size =
581 (prog_data->nr_params + local_id_dwords) * 4;
582 unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
583 unsigned push_constant_regs = reg_aligned_constant_size / 32;
584
585 if (push_state.alloc_size) {
586 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
587 .CURBETotalDataLength = push_state.alloc_size,
588 .CURBEDataStartAddress = push_state.offset);
589 }
590
591 assert(prog_data->total_shared <= 64 * 1024);
592 uint32_t slm_size = 0;
593 if (prog_data->total_shared > 0) {
594 /* slm_size is in 4k increments, but must be a power of 2. */
595 slm_size = 4 * 1024;
596 while (slm_size < prog_data->total_shared)
597 slm_size <<= 1;
598 slm_size /= 4 * 1024;
599 }
600
601 struct anv_state state =
602 anv_state_pool_emit(&device->dynamic_state_pool,
603 GENX(INTERFACE_DESCRIPTOR_DATA), 64,
604 .KernelStartPointer = pipeline->cs_simd,
605 .KernelStartPointerHigh = 0,
606 .BindingTablePointer = surfaces.offset,
607 .BindingTableEntryCount = 0,
608 .SamplerStatePointer = samplers.offset,
609 .SamplerCount = 0,
610 .ConstantIndirectURBEntryReadLength = push_constant_regs,
611 .ConstantURBEntryReadOffset = 0,
612 .BarrierEnable = cs_prog_data->uses_barrier,
613 .SharedLocalMemorySize = slm_size,
614 .NumberofThreadsinGPGPUThreadGroup =
615 pipeline->cs_thread_width_max);
616
617 uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
618 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
619 .InterfaceDescriptorTotalLength = size,
620 .InterfaceDescriptorDataStartAddress = state.offset);
621
622 return VK_SUCCESS;
623 }
624
625 static void
626 cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
627 {
628 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
629 VkResult result;
630
631 assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
632
633 bool needs_slm = pipeline->cs_prog_data.base.total_shared > 0;
634 config_l3(cmd_buffer, needs_slm);
635
636 if (cmd_buffer->state.current_pipeline != GPGPU) {
637 #if ANV_GEN < 10
638 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
639 *
640 * Software must clear the COLOR_CALC_STATE Valid field in
641 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
642 * with Pipeline Select set to GPGPU.
643 *
644 * The internal hardware docs recommend the same workaround for Gen9
645 * hardware too.
646 */
647 anv_batch_emit(&cmd_buffer->batch,
648 GENX(3DSTATE_CC_STATE_POINTERS));
649 #endif
650
651 anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
652 #if ANV_GEN >= 9
653 .MaskBits = 3,
654 #endif
655 .PipelineSelection = GPGPU);
656 cmd_buffer->state.current_pipeline = GPGPU;
657 }
658
659 if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
660 anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
661
662 if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
663 (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
664 result = flush_compute_descriptor_set(cmd_buffer);
665 assert(result == VK_SUCCESS);
666 cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
667 }
668
669 cmd_buffer->state.compute_dirty = 0;
670 }
671
672 void genX(CmdDrawIndexedIndirect)(
673 VkCommandBuffer commandBuffer,
674 VkBuffer _buffer,
675 VkDeviceSize offset,
676 uint32_t drawCount,
677 uint32_t stride)
678 {
679 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
680 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
681 struct anv_bo *bo = buffer->bo;
682 uint32_t bo_offset = buffer->offset + offset;
683
684 cmd_buffer_flush_state(cmd_buffer);
685
686 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
687 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
688 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
689 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
690 emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
691
692 anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE),
693 .IndirectParameterEnable = true,
694 .VertexAccessType = RANDOM);
695 }
696
697 void genX(CmdDispatch)(
698 VkCommandBuffer commandBuffer,
699 uint32_t x,
700 uint32_t y,
701 uint32_t z)
702 {
703 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
704 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
705 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
706
707 if (prog_data->uses_num_work_groups) {
708 struct anv_state state =
709 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 12, 4);
710 uint32_t *sizes = state.map;
711 sizes[0] = x;
712 sizes[1] = y;
713 sizes[2] = z;
714 if (!cmd_buffer->device->info.has_llc)
715 anv_state_clflush(state);
716 cmd_buffer->state.num_workgroups_offset = state.offset;
717 cmd_buffer->state.num_workgroups_bo =
718 &cmd_buffer->device->dynamic_state_block_pool.bo;
719 }
720
721 cmd_buffer_flush_compute_state(cmd_buffer);
722
723 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
724 .SIMDSize = prog_data->simd_size / 16,
725 .ThreadDepthCounterMaximum = 0,
726 .ThreadHeightCounterMaximum = 0,
727 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
728 .ThreadGroupIDXDimension = x,
729 .ThreadGroupIDYDimension = y,
730 .ThreadGroupIDZDimension = z,
731 .RightExecutionMask = pipeline->cs_right_mask,
732 .BottomExecutionMask = 0xffffffff);
733
734 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
735 }
736
737 #define GPGPU_DISPATCHDIMX 0x2500
738 #define GPGPU_DISPATCHDIMY 0x2504
739 #define GPGPU_DISPATCHDIMZ 0x2508
740
741 void genX(CmdDispatchIndirect)(
742 VkCommandBuffer commandBuffer,
743 VkBuffer _buffer,
744 VkDeviceSize offset)
745 {
746 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
747 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
748 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
749 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
750 struct anv_bo *bo = buffer->bo;
751 uint32_t bo_offset = buffer->offset + offset;
752
753 if (prog_data->uses_num_work_groups) {
754 cmd_buffer->state.num_workgroups_offset = bo_offset;
755 cmd_buffer->state.num_workgroups_bo = bo;
756 }
757
758 cmd_buffer_flush_compute_state(cmd_buffer);
759
760 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
761 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
762 emit_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
763
764 anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER),
765 .IndirectParameterEnable = true,
766 .SIMDSize = prog_data->simd_size / 16,
767 .ThreadDepthCounterMaximum = 0,
768 .ThreadHeightCounterMaximum = 0,
769 .ThreadWidthCounterMaximum = pipeline->cs_thread_width_max - 1,
770 .RightExecutionMask = pipeline->cs_right_mask,
771 .BottomExecutionMask = 0xffffffff);
772
773 anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_STATE_FLUSH));
774 }
775
776 static void
777 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
778 {
779 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
780 const struct anv_image_view *iview =
781 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
782 const struct anv_image *image = iview ? iview->image : NULL;
783
784 /* XXX: isl needs to grow depth format support */
785 const struct anv_format *anv_format =
786 iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
787
788 const bool has_depth = iview && anv_format->depth_format;
789 const bool has_stencil = iview && anv_format->has_stencil;
790
791 /* FIXME: Implement the PMA stall W/A */
792 /* FIXME: Width and Height are wrong */
793
794 /* Emit 3DSTATE_DEPTH_BUFFER */
795 if (has_depth) {
796 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
797 .SurfaceType = SURFTYPE_2D,
798 .DepthWriteEnable = anv_format->depth_format,
799 .StencilWriteEnable = has_stencil,
800 .HierarchicalDepthBufferEnable = false,
801 .SurfaceFormat = anv_format->depth_format,
802 .SurfacePitch = image->depth_surface.isl.row_pitch - 1,
803 .SurfaceBaseAddress = {
804 .bo = image->bo,
805 .offset = image->depth_surface.offset,
806 },
807 .Height = fb->height - 1,
808 .Width = fb->width - 1,
809 .LOD = 0,
810 .Depth = 1 - 1,
811 .MinimumArrayElement = 0,
812 .DepthBufferObjectControlState = GENX(MOCS),
813 .RenderTargetViewExtent = 1 - 1,
814 .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2);
815 } else {
816 /* Even when no depth buffer is present, the hardware requires that
817 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
818 *
819 * If a null depth buffer is bound, the driver must instead bind depth as:
820 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
821 * 3DSTATE_DEPTH.Width = 1
822 * 3DSTATE_DEPTH.Height = 1
823 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
824 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
825 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
826 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
827 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
828 *
829 * The PRM is wrong, though. The width and height must be programmed to
830 * actual framebuffer's width and height, even when neither depth buffer
831 * nor stencil buffer is present.
832 */
833 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER),
834 .SurfaceType = SURFTYPE_2D,
835 .SurfaceFormat = D16_UNORM,
836 .Width = fb->width - 1,
837 .Height = fb->height - 1,
838 .StencilWriteEnable = has_stencil);
839 }
840
841 /* Emit 3DSTATE_STENCIL_BUFFER */
842 if (has_stencil) {
843 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER),
844 .StencilBufferEnable = true,
845 .StencilBufferObjectControlState = GENX(MOCS),
846
847 /* Stencil buffers have strange pitch. The PRM says:
848 *
849 * The pitch must be set to 2x the value computed based on width,
850 * as the stencil buffer is stored with two rows interleaved.
851 */
852 .SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
853
854 .SurfaceBaseAddress = {
855 .bo = image->bo,
856 .offset = image->offset + image->stencil_surface.offset,
857 },
858 .SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2);
859 } else {
860 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
861 }
862
863 /* Disable hierarchial depth buffers. */
864 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HIER_DEPTH_BUFFER));
865
866 /* Clear the clear params. */
867 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS));
868 }
869
870 /**
871 * @see anv_cmd_buffer_set_subpass()
872 */
873 void
874 genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
875 struct anv_subpass *subpass)
876 {
877 cmd_buffer->state.subpass = subpass;
878
879 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
880
881 cmd_buffer_emit_depth_stencil(cmd_buffer);
882 }
883
884 void genX(CmdBeginRenderPass)(
885 VkCommandBuffer commandBuffer,
886 const VkRenderPassBeginInfo* pRenderPassBegin,
887 VkSubpassContents contents)
888 {
889 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
890 ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
891 ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
892
893 cmd_buffer->state.framebuffer = framebuffer;
894 cmd_buffer->state.pass = pass;
895 anv_cmd_state_setup_attachments(cmd_buffer, pRenderPassBegin);
896
897 flush_pipeline_select_3d(cmd_buffer);
898
899 const VkRect2D *render_area = &pRenderPassBegin->renderArea;
900
901 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DRAWING_RECTANGLE),
902 .ClippedDrawingRectangleYMin = render_area->offset.y,
903 .ClippedDrawingRectangleXMin = render_area->offset.x,
904 .ClippedDrawingRectangleYMax =
905 render_area->offset.y + render_area->extent.height - 1,
906 .ClippedDrawingRectangleXMax =
907 render_area->offset.x + render_area->extent.width - 1,
908 .DrawingRectangleOriginY = 0,
909 .DrawingRectangleOriginX = 0);
910
911 genX(cmd_buffer_set_subpass)(cmd_buffer, pass->subpasses);
912 anv_cmd_buffer_clear_subpass(cmd_buffer);
913 }
914
915 void genX(CmdNextSubpass)(
916 VkCommandBuffer commandBuffer,
917 VkSubpassContents contents)
918 {
919 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
920
921 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
922
923 genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
924 anv_cmd_buffer_clear_subpass(cmd_buffer);
925 }
926
927 void genX(CmdEndRenderPass)(
928 VkCommandBuffer commandBuffer)
929 {
930 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
931
932 /* Emit a flushing pipe control at the end of a pass. This is kind of a
933 * hack but it ensures that render targets always actually get written.
934 * Eventually, we should do flushing based on image format transitions
935 * or something of that nature.
936 */
937 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
938 .PostSyncOperation = NoWrite,
939 .RenderTargetCacheFlushEnable = true,
940 .InstructionCacheInvalidateEnable = true,
941 .DepthCacheFlushEnable = true,
942 .VFCacheInvalidationEnable = true,
943 .TextureCacheInvalidationEnable = true,
944 .CommandStreamerStallEnable = true);
945 }
946
947 static void
948 emit_ps_depth_count(struct anv_batch *batch,
949 struct anv_bo *bo, uint32_t offset)
950 {
951 anv_batch_emit(batch, GENX(PIPE_CONTROL),
952 .DestinationAddressType = DAT_PPGTT,
953 .PostSyncOperation = WritePSDepthCount,
954 .DepthStallEnable = true,
955 .Address = { bo, offset });
956 }
957
958 static void
959 emit_query_availability(struct anv_batch *batch,
960 struct anv_bo *bo, uint32_t offset)
961 {
962 anv_batch_emit(batch, GENX(PIPE_CONTROL),
963 .DestinationAddressType = DAT_PPGTT,
964 .PostSyncOperation = WriteImmediateData,
965 .Address = { bo, offset },
966 .ImmediateData = 1);
967 }
968
969 void genX(CmdBeginQuery)(
970 VkCommandBuffer commandBuffer,
971 VkQueryPool queryPool,
972 uint32_t query,
973 VkQueryControlFlags flags)
974 {
975 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
976 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
977
978 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
979 * that the pipelining of the depth write breaks. What we see is that
980 * samples from the render pass clear leaks into the first query
981 * immediately after the clear. Doing a pipecontrol with a post-sync
982 * operation and DepthStallEnable seems to work around the issue.
983 */
984 if (cmd_buffer->state.need_query_wa) {
985 cmd_buffer->state.need_query_wa = false;
986 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
987 .DepthCacheFlushEnable = true,
988 .DepthStallEnable = true);
989 }
990
991 switch (pool->type) {
992 case VK_QUERY_TYPE_OCCLUSION:
993 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
994 query * sizeof(struct anv_query_pool_slot));
995 break;
996
997 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
998 default:
999 unreachable("");
1000 }
1001 }
1002
1003 void genX(CmdEndQuery)(
1004 VkCommandBuffer commandBuffer,
1005 VkQueryPool queryPool,
1006 uint32_t query)
1007 {
1008 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1009 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
1010
1011 switch (pool->type) {
1012 case VK_QUERY_TYPE_OCCLUSION:
1013 emit_ps_depth_count(&cmd_buffer->batch, &pool->bo,
1014 query * sizeof(struct anv_query_pool_slot) + 8);
1015
1016 emit_query_availability(&cmd_buffer->batch, &pool->bo,
1017 query * sizeof(struct anv_query_pool_slot) + 16);
1018 break;
1019
1020 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1021 default:
1022 unreachable("");
1023 }
1024 }
1025
1026 #define TIMESTAMP 0x2358
1027
1028 void genX(CmdWriteTimestamp)(
1029 VkCommandBuffer commandBuffer,
1030 VkPipelineStageFlagBits pipelineStage,
1031 VkQueryPool queryPool,
1032 uint32_t query)
1033 {
1034 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1035 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
1036 uint32_t offset = query * sizeof(struct anv_query_pool_slot);
1037
1038 assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
1039
1040 switch (pipelineStage) {
1041 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
1042 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
1043 .RegisterAddress = TIMESTAMP,
1044 .MemoryAddress = { &pool->bo, offset });
1045 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM),
1046 .RegisterAddress = TIMESTAMP + 4,
1047 .MemoryAddress = { &pool->bo, offset + 4 });
1048 break;
1049
1050 default:
1051 /* Everything else is bottom-of-pipe */
1052 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1053 .DestinationAddressType = DAT_PPGTT,
1054 .PostSyncOperation = WriteTimestamp,
1055 .Address = { &pool->bo, offset });
1056 break;
1057 }
1058
1059 emit_query_availability(&cmd_buffer->batch, &pool->bo, query + 16);
1060 }
1061
1062 #define alu_opcode(v) __gen_field((v), 20, 31)
1063 #define alu_operand1(v) __gen_field((v), 10, 19)
1064 #define alu_operand2(v) __gen_field((v), 0, 9)
1065 #define alu(opcode, operand1, operand2) \
1066 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1067
1068 #define OPCODE_NOOP 0x000
1069 #define OPCODE_LOAD 0x080
1070 #define OPCODE_LOADINV 0x480
1071 #define OPCODE_LOAD0 0x081
1072 #define OPCODE_LOAD1 0x481
1073 #define OPCODE_ADD 0x100
1074 #define OPCODE_SUB 0x101
1075 #define OPCODE_AND 0x102
1076 #define OPCODE_OR 0x103
1077 #define OPCODE_XOR 0x104
1078 #define OPCODE_STORE 0x180
1079 #define OPCODE_STOREINV 0x580
1080
1081 #define OPERAND_R0 0x00
1082 #define OPERAND_R1 0x01
1083 #define OPERAND_R2 0x02
1084 #define OPERAND_R3 0x03
1085 #define OPERAND_R4 0x04
1086 #define OPERAND_SRCA 0x20
1087 #define OPERAND_SRCB 0x21
1088 #define OPERAND_ACCU 0x31
1089 #define OPERAND_ZF 0x32
1090 #define OPERAND_CF 0x33
1091
1092 #define CS_GPR(n) (0x2600 + (n) * 8)
1093
1094 static void
1095 emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
1096 struct anv_bo *bo, uint32_t offset)
1097 {
1098 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
1099 .RegisterAddress = reg,
1100 .MemoryAddress = { bo, offset });
1101 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM),
1102 .RegisterAddress = reg + 4,
1103 .MemoryAddress = { bo, offset + 4 });
1104 }
1105
1106 static void
1107 store_query_result(struct anv_batch *batch, uint32_t reg,
1108 struct anv_bo *bo, uint32_t offset, VkQueryResultFlags flags)
1109 {
1110 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
1111 .RegisterAddress = reg,
1112 .MemoryAddress = { bo, offset });
1113
1114 if (flags & VK_QUERY_RESULT_64_BIT)
1115 anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM),
1116 .RegisterAddress = reg + 4,
1117 .MemoryAddress = { bo, offset + 4 });
1118 }
1119
1120 void genX(CmdCopyQueryPoolResults)(
1121 VkCommandBuffer commandBuffer,
1122 VkQueryPool queryPool,
1123 uint32_t firstQuery,
1124 uint32_t queryCount,
1125 VkBuffer destBuffer,
1126 VkDeviceSize destOffset,
1127 VkDeviceSize destStride,
1128 VkQueryResultFlags flags)
1129 {
1130 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1131 ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
1132 ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
1133 uint32_t slot_offset, dst_offset;
1134
1135 if (flags & VK_QUERY_RESULT_WAIT_BIT)
1136 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1137 .CommandStreamerStallEnable = true,
1138 .StallAtPixelScoreboard = true);
1139
1140 dst_offset = buffer->offset + destOffset;
1141 for (uint32_t i = 0; i < queryCount; i++) {
1142
1143 slot_offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot);
1144 switch (pool->type) {
1145 case VK_QUERY_TYPE_OCCLUSION:
1146 emit_load_alu_reg_u64(&cmd_buffer->batch,
1147 CS_GPR(0), &pool->bo, slot_offset);
1148 emit_load_alu_reg_u64(&cmd_buffer->batch,
1149 CS_GPR(1), &pool->bo, slot_offset + 8);
1150
1151 /* FIXME: We need to clamp the result for 32 bit. */
1152
1153 uint32_t *dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(MI_MATH));
1154 dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
1155 dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
1156 dw[3] = alu(OPCODE_SUB, 0, 0);
1157 dw[4] = alu(OPCODE_STORE, OPERAND_R2, OPERAND_ACCU);
1158 break;
1159
1160 case VK_QUERY_TYPE_TIMESTAMP:
1161 emit_load_alu_reg_u64(&cmd_buffer->batch,
1162 CS_GPR(2), &pool->bo, slot_offset);
1163 break;
1164
1165 default:
1166 unreachable("unhandled query type");
1167 }
1168
1169 store_query_result(&cmd_buffer->batch,
1170 CS_GPR(2), buffer->bo, dst_offset, flags);
1171
1172 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1173 emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
1174 &pool->bo, slot_offset + 16);
1175 if (flags & VK_QUERY_RESULT_64_BIT)
1176 store_query_result(&cmd_buffer->batch,
1177 CS_GPR(0), buffer->bo, dst_offset + 8, flags);
1178 else
1179 store_query_result(&cmd_buffer->batch,
1180 CS_GPR(0), buffer->bo, dst_offset + 4, flags);
1181 }
1182
1183 dst_offset += destStride;
1184 }
1185 }
1186
1187 void genX(CmdSetEvent)(
1188 VkCommandBuffer commandBuffer,
1189 VkEvent _event,
1190 VkPipelineStageFlags stageMask)
1191 {
1192 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1193 ANV_FROM_HANDLE(anv_event, event, _event);
1194
1195 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1196 .DestinationAddressType = DAT_PPGTT,
1197 .PostSyncOperation = WriteImmediateData,
1198 .Address = {
1199 &cmd_buffer->device->dynamic_state_block_pool.bo,
1200 event->state.offset
1201 },
1202 .ImmediateData = VK_EVENT_SET);
1203 }
1204
1205 void genX(CmdResetEvent)(
1206 VkCommandBuffer commandBuffer,
1207 VkEvent _event,
1208 VkPipelineStageFlags stageMask)
1209 {
1210 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1211 ANV_FROM_HANDLE(anv_event, event, _event);
1212
1213 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
1214 .DestinationAddressType = DAT_PPGTT,
1215 .PostSyncOperation = WriteImmediateData,
1216 .Address = {
1217 &cmd_buffer->device->dynamic_state_block_pool.bo,
1218 event->state.offset
1219 },
1220 .ImmediateData = VK_EVENT_RESET);
1221 }
1222
1223 void genX(CmdWaitEvents)(
1224 VkCommandBuffer commandBuffer,
1225 uint32_t eventCount,
1226 const VkEvent* pEvents,
1227 VkPipelineStageFlags srcStageMask,
1228 VkPipelineStageFlags destStageMask,
1229 uint32_t memoryBarrierCount,
1230 const VkMemoryBarrier* pMemoryBarriers,
1231 uint32_t bufferMemoryBarrierCount,
1232 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
1233 uint32_t imageMemoryBarrierCount,
1234 const VkImageMemoryBarrier* pImageMemoryBarriers)
1235 {
1236 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1237 for (uint32_t i = 0; i < eventCount; i++) {
1238 ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
1239
1240 anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT),
1241 .WaitMode = PollingMode,
1242 .CompareOperation = SAD_EQUAL_SDD,
1243 .SemaphoreDataDword = VK_EVENT_SET,
1244 .SemaphoreAddress = {
1245 &cmd_buffer->device->dynamic_state_block_pool.bo,
1246 event->state.offset
1247 });
1248 }
1249
1250 genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
1251 false, /* byRegion */
1252 memoryBarrierCount, pMemoryBarriers,
1253 bufferMemoryBarrierCount, pBufferMemoryBarriers,
1254 imageMemoryBarrierCount, pImageMemoryBarriers);
1255 }