src/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "gen8_pack.h"
  33 #include "gen9_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info,
  40               const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
  43                   .PrimitiveTopologyType = pipeline->topology);
  44 }
  45
  46 static void
  47 emit_rs_state(struct anv_pipeline *pipeline,
  48               const VkPipelineRasterizationStateCreateInfo *info,
  49               const VkPipelineMultisampleStateCreateInfo *ms_info,
  50               const struct anv_graphics_pipeline_create_info *extra)
  51 {
  52    uint32_t samples = 1;
  53
  54    if (ms_info)
  55       samples = ms_info->rasterizationSamples;
  56
  57    struct GENX(3DSTATE_SF) sf = {
  58       GENX(3DSTATE_SF_header),
  59       .ViewportTransformEnable = !(extra && extra->disable_viewport),
  60       .TriangleStripListProvokingVertexSelect = 0,
  61       .LineStripListProvokingVertexSelect = 0,
  62       .TriangleFanProvokingVertexSelect = 0,
  63       .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
  64       .PointWidth = 1.0,
  65    };
  66
  67    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
  68
  69    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
  70
  71    struct GENX(3DSTATE_RASTER) raster = {
  72       GENX(3DSTATE_RASTER_header),
  73
  74       /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
  75        * "Multisample Modes State".
  76        */
  77       .DXMultisampleRasterizationEnable = samples > 1,
  78       .ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
  79       .ForceMultisampling = false,
  80
  81       .FrontWinding = vk_to_gen_front_face[info->frontFace],
  82       .CullMode = vk_to_gen_cullmode[info->cullMode],
  83       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  84       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  85       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
  86 #if ANV_GEN == 8
  87       .ViewportZClipTestEnable = true,
  88 #else
  89       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
  90       .ViewportZFarClipTestEnable = true,
  91       .ViewportZNearClipTestEnable = true,
  92 #endif
  93    };
  94
  95    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
  96 }
  97
  98 static void
  99 emit_cb_state(struct anv_pipeline *pipeline,
 100               const VkPipelineColorBlendStateCreateInfo *info,
 101               const VkPipelineMultisampleStateCreateInfo *ms_info)
 102 {
 103    struct anv_device *device = pipeline->device;
 104
 105    uint32_t num_dwords = GENX(BLEND_STATE_length);
 106    pipeline->blend_state =
 107       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 108
 109    struct GENX(BLEND_STATE) blend_state = {
 110       .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 111       .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 112    };
 113
 114    for (uint32_t i = 0; i < info->attachmentCount; i++) {
 115       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
 116
 117       if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
 118           a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
 119           a->colorBlendOp != a->alphaBlendOp) {
 120          blend_state.IndependentAlphaBlendEnable = true;
 121       }
 122
 123       blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
 124          .LogicOpEnable = info->logicOpEnable,
 125          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 126          .ColorBufferBlendEnable = a->blendEnable,
 127          .PreBlendSourceOnlyClampEnable = false,
 128          .ColorClampRange = COLORCLAMP_RTFORMAT,
 129          .PreBlendColorClampEnable = true,
 130          .PostBlendColorClampEnable = true,
 131          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 132          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 133          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 134          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 135          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 136          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 137          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 138          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 139          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 140          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 141       };
 142
 143       /* Our hardware applies the blend factor prior to the blend function
 144        * regardless of what function is used.  Technically, this means the
 145        * hardware can do MORE than GL or Vulkan specify.  However, it also
 146        * means that, for MIN and MAX, we have to stomp the blend factor to
 147        * ONE to make it a no-op.
 148        */
 149       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 150           a->colorBlendOp == VK_BLEND_OP_MAX) {
 151          blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
 152          blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
 153       }
 154       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 155           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 156          blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 157          blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 158       }
 159    }
 160
 161    GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
 162    if (!device->info.has_llc)
 163       anv_state_clflush(pipeline->blend_state);
 164
 165    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
 166                   .BlendStatePointer = pipeline->blend_state.offset,
 167                   .BlendStatePointerValid = true);
 168 }
 169
 170 static void
 171 emit_ds_state(struct anv_pipeline *pipeline,
 172               const VkPipelineDepthStencilStateCreateInfo *info)
 173 {
 174    uint32_t *dw = ANV_GEN == 8 ?
 175       pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
 176
 177    if (info == NULL) {
 178       /* We're going to OR this together with the dynamic state.  We need
 179        * to make sure it's initialized to something useful.
 180        */
 181       memset(pipeline->gen8.wm_depth_stencil, 0,
 182              sizeof(pipeline->gen8.wm_depth_stencil));
 183       memset(pipeline->gen9.wm_depth_stencil, 0,
 184              sizeof(pipeline->gen9.wm_depth_stencil));
 185       return;
 186    }
 187
 188    /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
 189
 190    struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 191       .DepthTestEnable = info->depthTestEnable,
 192       .DepthBufferWriteEnable = info->depthWriteEnable,
 193       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 194       .DoubleSidedStencilEnable = true,
 195
 196       .StencilTestEnable = info->stencilTestEnable,
 197       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 198       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 199       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 200       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 201       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 202       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 203       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
 204       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 205    };
 206
 207    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
 208 }
 209
 210 static void
 211 emit_ms_state(struct anv_pipeline *pipeline,
 212               const VkPipelineMultisampleStateCreateInfo *info)
 213 {
 214    uint32_t samples = 1;
 215    uint32_t log2_samples = 0;
 216
 217    /* From the Vulkan 1.0 spec:
 218     *    If pSampleMask is NULL, it is treated as if the mask has all bits
 219     *    enabled, i.e. no coverage is removed from fragments.
 220     *
 221     * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
 222     */
 223    uint32_t sample_mask = 0xffff;
 224
 225    if (info) {
 226       samples = info->rasterizationSamples;
 227       log2_samples = __builtin_ffs(samples) - 1;
 228    }
 229
 230    if (info && info->pSampleMask)
 231       sample_mask &= info->pSampleMask[0];
 232
 233    if (info && info->sampleShadingEnable)
 234       anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
 235
 236    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
 237
 238       /* The PRM says that this bit is valid only for DX9:
 239        *
 240        *    SW can choose to set this bit only for DX9 API. DX10/OGL API's
 241        *    should not have any effect by setting or not setting this bit.
 242        */
 243       .PixelPositionOffsetEnable = false,
 244
 245       .PixelLocation = CENTER,
 246       .NumberofMultisamples = log2_samples);
 247
 248    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
 249       .SampleMask = sample_mask);
 250 }
 251
 252 VkResult
 253 genX(graphics_pipeline_create)(
 254     VkDevice                                    _device,
 255     struct anv_pipeline_cache *                 cache,
 256     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 257     const struct anv_graphics_pipeline_create_info *extra,
 258     const VkAllocationCallbacks*                pAllocator,
 259     VkPipeline*                                 pPipeline)
 260 {
 261    ANV_FROM_HANDLE(anv_device, device, _device);
 262    struct anv_pipeline *pipeline;
 263    VkResult result;
 264    uint32_t offset, length;
 265
 266    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 267
 268    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 269                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 270    if (pipeline == NULL)
 271       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 272
 273    result = anv_pipeline_init(pipeline, device, cache,
 274                               pCreateInfo, extra, pAllocator);
 275    if (result != VK_SUCCESS) {
 276       anv_free2(&device->alloc, pAllocator, pipeline);
 277       return result;
 278    }
 279
 280    assert(pCreateInfo->pVertexInputState);
 281    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 282    assert(pCreateInfo->pInputAssemblyState);
 283    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 284    assert(pCreateInfo->pRasterizationState);
 285    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
 286                  pCreateInfo->pMultisampleState, extra);
 287    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
 288    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 289    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 290                            pCreateInfo->pMultisampleState);
 291
 292    emit_urb_setup(pipeline);
 293
 294    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
 295                   .ClipEnable = true,
 296                   .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
 297                   .MinimumPointWidth = 0.125,
 298                   .MaximumPointWidth = 255.875,
 299                   .MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
 300
 301    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 302                   .StatisticsEnable = true,
 303                   .LineEndCapAntialiasingRegionWidth = _05pixels,
 304                   .LineAntialiasingRegionWidth = _10pixels,
 305                   .EarlyDepthStencilControl = NORMAL,
 306                   .ForceThreadDispatchEnable = NORMAL,
 307                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
 308                   .BarycentricInterpolationMode =
 309                      pipeline->ps_ksp0 == NO_KERNEL ?
 310                      0 : pipeline->wm_prog_data.barycentric_interp_modes);
 311
 312    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 313    offset = 1;
 314    length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 315
 316    if (pipeline->gs_kernel == NO_KERNEL)
 317       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
 318    else
 319       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 320                      .SingleProgramFlow = false,
 321                      .KernelStartPointer = pipeline->gs_kernel,
 322                      .VectorMaskEnable = false,
 323                      .SamplerCount = 0,
 324                      .BindingTableEntryCount = 0,
 325                      .ExpectedVertexCount = gs_prog_data->vertices_in,
 326
 327                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 328                      .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
 329
 330                      .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 331                      .OutputTopology = gs_prog_data->output_topology,
 332                      .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
 333                      .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
 334                      .DispatchGRFStartRegisterForURBData =
 335                         gs_prog_data->base.base.dispatch_grf_start_reg,
 336
 337                      .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
 338                      .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
 339                      .DispatchMode = gs_prog_data->base.dispatch_mode,
 340                      .StatisticsEnable = true,
 341                      .IncludePrimitiveID = gs_prog_data->include_primitive_id,
 342                      .ReorderMode = TRAILING,
 343                      .Enable = true,
 344
 345                      .ControlDataFormat = gs_prog_data->control_data_format,
 346
 347                      .StaticOutput = gs_prog_data->static_vertex_count >= 0,
 348                      .StaticOutputVertexCount =
 349                         gs_prog_data->static_vertex_count >= 0 ?
 350                         gs_prog_data->static_vertex_count : 0,
 351
 352                      /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 353                       * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 354                       * UserClipDistanceCullTestEnableBitmask(v)
 355                       */
 356
 357                      .VertexURBEntryOutputReadOffset = offset,
 358                      .VertexURBEntryOutputLength = length);
 359
 360    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 361    /* Skip the VUE header and position slots */
 362    offset = 1;
 363    length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
 364
 365    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
 366                                                          pipeline->vs_vec4;
 367
 368    if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
 369       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 370                      .FunctionEnable = false,
 371                      /* Even if VS is disabled, SBE still gets the amount of
 372                       * vertex data to read from this field. */
 373                      .VertexURBEntryOutputReadOffset = offset,
 374                      .VertexURBEntryOutputLength = length);
 375    else
 376       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 377                      .KernelStartPointer = vs_start,
 378                      .SingleVertexDispatch = false,
 379                      .VectorMaskEnable = false,
 380                      .SamplerCount = 0,
 381                      .BindingTableEntryCount =
 382                      vue_prog_data->base.binding_table.size_bytes / 4,
 383                      .ThreadDispatchPriority = false,
 384                      .FloatingPointMode = IEEE754,
 385                      .IllegalOpcodeExceptionEnable = false,
 386                      .AccessesUAV = false,
 387                      .SoftwareExceptionEnable = false,
 388
 389                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
 390                      .PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
 391
 392                      .DispatchGRFStartRegisterForURBData =
 393                      vue_prog_data->base.dispatch_grf_start_reg,
 394                      .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
 395                      .VertexURBEntryReadOffset = 0,
 396
 397                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
 398                      .StatisticsEnable = false,
 399                      .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
 400                      .VertexCacheDisable = false,
 401                      .FunctionEnable = true,
 402
 403                      .VertexURBEntryOutputReadOffset = offset,
 404                      .VertexURBEntryOutputLength = length,
 405                      .UserClipDistanceClipTestEnableBitmask = 0,
 406                      .UserClipDistanceCullTestEnableBitmask = 0);
 407
 408    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 409
 410    const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
 411    if (pipeline->ps_ksp0 == NO_KERNEL) {
 412       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
 413       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 414                      .PixelShaderValid = false);
 415    } else {
 416       /* TODO: We should clean this up.  Among other things, this is mostly
 417        * shared with other gens.
 418        */
 419       const struct brw_vue_map *fs_input_map;
 420       if (pipeline->gs_kernel == NO_KERNEL)
 421          fs_input_map = &vue_prog_data->vue_map;
 422       else
 423          fs_input_map = &gs_prog_data->base.vue_map;
 424
 425       struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 426          GENX(3DSTATE_SBE_SWIZ_header),
 427       };
 428
 429       int max_source_attr = 0;
 430       for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 431          int input_index = wm_prog_data->urb_setup[attr];
 432
 433          if (input_index < 0)
 434             continue;
 435
 436          int source_attr = fs_input_map->varying_to_slot[attr];
 437          max_source_attr = MAX2(max_source_attr, source_attr);
 438
 439          if (input_index >= 16)
 440             continue;
 441
 442          if (source_attr == -1) {
 443             /* This attribute does not exist in the VUE--that means that the
 444              * vertex shader did not write to it.  It could be that it's a
 445              * regular varying read by the fragment shader but not written by
 446              * the vertex shader or it's gl_PrimitiveID. In the first case the
 447              * value is undefined, in the second it needs to be
 448              * gl_PrimitiveID.
 449              */
 450             swiz.Attribute[input_index].ConstantSource = PRIM_ID;
 451             swiz.Attribute[input_index].ComponentOverrideX = true;
 452             swiz.Attribute[input_index].ComponentOverrideY = true;
 453             swiz.Attribute[input_index].ComponentOverrideZ = true;
 454             swiz.Attribute[input_index].ComponentOverrideW = true;
 455          } else {
 456             /* We have to subtract two slots to accout for the URB entry output
 457              * read offset in the VS and GS stages.
 458              */
 459             swiz.Attribute[input_index].SourceAttribute = source_attr - 2;
 460          }
 461       }
 462
 463       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
 464                      .AttributeSwizzleEnable = true,
 465                      .ForceVertexURBEntryReadLength = false,
 466                      .ForceVertexURBEntryReadOffset = false,
 467                      .VertexURBEntryReadLength =
 468                         DIV_ROUND_UP(max_source_attr + 1, 2),
 469                      .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 470                      .NumberofSFOutputAttributes =
 471                      wm_prog_data->num_varying_inputs,
 472
 473 #if ANV_GEN >= 9
 474                      .Attribute0ActiveComponentFormat = ACF_XYZW,
 475                      .Attribute1ActiveComponentFormat = ACF_XYZW,
 476                      .Attribute2ActiveComponentFormat = ACF_XYZW,
 477                      .Attribute3ActiveComponentFormat = ACF_XYZW,
 478                      .Attribute4ActiveComponentFormat = ACF_XYZW,
 479                      .Attribute5ActiveComponentFormat = ACF_XYZW,
 480                      .Attribute6ActiveComponentFormat = ACF_XYZW,
 481                      .Attribute7ActiveComponentFormat = ACF_XYZW,
 482                      .Attribute8ActiveComponentFormat = ACF_XYZW,
 483                      .Attribute9ActiveComponentFormat = ACF_XYZW,
 484                      .Attribute10ActiveComponentFormat = ACF_XYZW,
 485                      .Attribute11ActiveComponentFormat = ACF_XYZW,
 486                      .Attribute12ActiveComponentFormat = ACF_XYZW,
 487                      .Attribute13ActiveComponentFormat = ACF_XYZW,
 488                      .Attribute14ActiveComponentFormat = ACF_XYZW,
 489                      .Attribute15ActiveComponentFormat = ACF_XYZW,
 490                      /* wow, much field, very attribute */
 491                      .Attribute16ActiveComponentFormat = ACF_XYZW,
 492                      .Attribute17ActiveComponentFormat = ACF_XYZW,
 493                      .Attribute18ActiveComponentFormat = ACF_XYZW,
 494                      .Attribute19ActiveComponentFormat = ACF_XYZW,
 495                      .Attribute20ActiveComponentFormat = ACF_XYZW,
 496                      .Attribute21ActiveComponentFormat = ACF_XYZW,
 497                      .Attribute22ActiveComponentFormat = ACF_XYZW,
 498                      .Attribute23ActiveComponentFormat = ACF_XYZW,
 499                      .Attribute24ActiveComponentFormat = ACF_XYZW,
 500                      .Attribute25ActiveComponentFormat = ACF_XYZW,
 501                      .Attribute26ActiveComponentFormat = ACF_XYZW,
 502                      .Attribute27ActiveComponentFormat = ACF_XYZW,
 503                      .Attribute28ActiveComponentFormat = ACF_XYZW,
 504                      .Attribute29ActiveComponentFormat = ACF_XYZW,
 505                      .Attribute28ActiveComponentFormat = ACF_XYZW,
 506                      .Attribute29ActiveComponentFormat = ACF_XYZW,
 507                      .Attribute30ActiveComponentFormat = ACF_XYZW,
 508 #endif
 509          );
 510
 511       uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 512                                            GENX(3DSTATE_SBE_SWIZ_length));
 513       GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 514
 515       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 516                      .KernelStartPointer0 = pipeline->ps_ksp0,
 517
 518                      .SingleProgramFlow = false,
 519                      .VectorMaskEnable = true,
 520                      .SamplerCount = 1,
 521
 522                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 523                      .PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
 524
 525                      .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
 526                      .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
 527                         POSOFFSET_SAMPLE: POSOFFSET_NONE,
 528                      .PushConstantEnable = wm_prog_data->base.nr_params > 0,
 529                      ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
 530                      ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
 531                      ._32PixelDispatchEnable = false,
 532
 533                      .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
 534                      .DispatchGRFStartRegisterForConstantSetupData1 = 0,
 535                      .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
 536
 537                      .KernelStartPointer1 = 0,
 538                      .KernelStartPointer2 = pipeline->ps_ksp2);
 539
 540       bool per_sample_ps = pCreateInfo->pMultisampleState &&
 541                            pCreateInfo->pMultisampleState->sampleShadingEnable;
 542
 543       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 544                      .PixelShaderValid = true,
 545                      .PixelShaderKillsPixel = wm_prog_data->uses_kill,
 546                      .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
 547                      .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
 548                      .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
 549                      .PixelShaderIsPerSample = per_sample_ps,
 550                      .PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth,
 551                      .PixelShaderUsesSourceW = wm_prog_data->uses_src_w,
 552 #if ANV_GEN >= 9
 553                      .PixelShaderPullsBary = wm_prog_data->pulls_bary,
 554                      .InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
 555                         ICMS_INNER_CONSERVATIVE : ICMS_NONE,
 556 #else
 557                      .PixelShaderUsesInputCoverageMask =
 558                         wm_prog_data->uses_sample_mask,
 559 #endif
 560          );
 561    }
 562
 563    *pPipeline = anv_pipeline_to_handle(pipeline);
 564
 565    return VK_SUCCESS;
 566 }