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vk/0.210.0: Rework color blending enums
[mesa.git] / src / vulkan / gen8_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
34
35 static void
36 emit_vertex_input(struct anv_pipeline *pipeline,
37 const VkPipelineVertexInputStateCreateInfo *info)
38 {
39 const uint32_t num_dwords = 1 + info->attributeCount * 2;
40 uint32_t *p;
41
42 static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
43
44 if (info->attributeCount > 0) {
45 p = anv_batch_emitn(&pipeline->batch, num_dwords,
46 GENX(3DSTATE_VERTEX_ELEMENTS));
47 }
48
49 for (uint32_t i = 0; i < info->attributeCount; i++) {
50 const VkVertexInputAttributeDescription *desc =
51 &info->pVertexAttributeDescriptions[i];
52 const struct anv_format *format = anv_format_for_vk_format(desc->format);
53
54 struct GENX(VERTEX_ELEMENT_STATE) element = {
55 .VertexBufferIndex = desc->binding,
56 .Valid = true,
57 .SourceElementFormat = format->surface_format,
58 .EdgeFlagEnable = false,
59 .SourceElementOffset = desc->offsetInBytes,
60 .Component0Control = VFCOMP_STORE_SRC,
61 .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
62 .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
63 .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
64 };
65 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
66
67 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
68 .InstancingEnable = pipeline->instancing_enable[desc->binding],
69 .VertexElementIndex = i,
70 /* Vulkan so far doesn't have an instance divisor, so
71 * this is always 1 (ignored if not instancing). */
72 .InstanceDataStepRate = 1);
73 }
74
75 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
76 .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
77 .VertexIDComponentNumber = 2,
78 .VertexIDElementOffset = info->bindingCount,
79 .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
80 .InstanceIDComponentNumber = 3,
81 .InstanceIDElementOffset = info->bindingCount);
82 }
83
84 static void
85 emit_ia_state(struct anv_pipeline *pipeline,
86 const VkPipelineInputAssemblyStateCreateInfo *info,
87 const struct anv_graphics_pipeline_create_info *extra)
88 {
89 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
90 .PrimitiveTopologyType = pipeline->topology);
91 }
92
93 static void
94 emit_rs_state(struct anv_pipeline *pipeline,
95 const VkPipelineRasterStateCreateInfo *info,
96 const struct anv_graphics_pipeline_create_info *extra)
97 {
98 static const uint32_t vk_to_gen_cullmode[] = {
99 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
100 [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
101 [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
102 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
103 };
104
105 static const uint32_t vk_to_gen_fillmode[] = {
106 [VK_POLYGON_MODE_FILL] = RASTER_SOLID,
107 [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME,
108 [VK_POLYGON_MODE_POINT] = RASTER_POINT,
109 };
110
111 static const uint32_t vk_to_gen_front_face[] = {
112 [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
113 [VK_FRONT_FACE_CLOCKWISE] = 0
114 };
115
116 struct GENX(3DSTATE_SF) sf = {
117 GENX(3DSTATE_SF_header),
118 .ViewportTransformEnable = !(extra && extra->disable_viewport),
119 .TriangleStripListProvokingVertexSelect = 0,
120 .LineStripListProvokingVertexSelect = 0,
121 .TriangleFanProvokingVertexSelect = 0,
122 .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
123 .PointWidth = 1.0,
124 };
125
126 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
127
128 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
129
130 struct GENX(3DSTATE_RASTER) raster = {
131 GENX(3DSTATE_RASTER_header),
132 .FrontWinding = vk_to_gen_front_face[info->frontFace],
133 .CullMode = vk_to_gen_cullmode[info->cullMode],
134 .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
135 .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
136 .ScissorRectangleEnable = !(extra && extra->disable_scissor),
137 #if ANV_GEN == 8
138 .ViewportZClipTestEnable = info->depthClipEnable
139 #else
140 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
141 .ViewportZFarClipTestEnable = info->depthClipEnable,
142 .ViewportZNearClipTestEnable = info->depthClipEnable,
143 #endif
144 };
145
146 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
147 }
148
149 static void
150 emit_cb_state(struct anv_pipeline *pipeline,
151 const VkPipelineColorBlendStateCreateInfo *info)
152 {
153 struct anv_device *device = pipeline->device;
154
155 static const uint32_t vk_to_gen_logic_op[] = {
156 [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
157 [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
158 [VK_LOGIC_OP_AND] = LOGICOP_AND,
159 [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
160 [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
161 [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
162 [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
163 [VK_LOGIC_OP_OR] = LOGICOP_OR,
164 [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
165 [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
166 [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
167 [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
168 [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
169 [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
170 [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
171 [VK_LOGIC_OP_SET] = LOGICOP_SET,
172 };
173
174 static const uint32_t vk_to_gen_blend[] = {
175 [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
176 [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
177 [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
178 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
179 [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
180 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
181 [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
182 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
183 [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
184 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
185 [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
186 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
187 [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
188 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
189 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
190 [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
191 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
192 [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
193 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
194 };
195
196 static const uint32_t vk_to_gen_blend_op[] = {
197 [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
198 [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
199 [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
200 [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
201 [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
202 };
203
204 uint32_t num_dwords = GENX(BLEND_STATE_length);
205 pipeline->blend_state =
206 anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
207
208 struct GENX(BLEND_STATE) blend_state = {
209 .AlphaToCoverageEnable = info->alphaToCoverageEnable,
210 .AlphaToOneEnable = info->alphaToOneEnable,
211 };
212
213 for (uint32_t i = 0; i < info->attachmentCount; i++) {
214 const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
215
216 if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
217 a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
218 a->colorBlendOp != a->alphaBlendOp) {
219 blend_state.IndependentAlphaBlendEnable = true;
220 }
221
222 blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
223 .LogicOpEnable = info->logicOpEnable,
224 .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
225 .ColorBufferBlendEnable = a->blendEnable,
226 .PreBlendSourceOnlyClampEnable = false,
227 .ColorClampRange = COLORCLAMP_RTFORMAT,
228 .PreBlendColorClampEnable = true,
229 .PostBlendColorClampEnable = true,
230 .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
231 .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
232 .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
233 .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
234 .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
235 .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
236 .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
237 .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
238 .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
239 .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
240 };
241
242 /* Our hardware applies the blend factor prior to the blend function
243 * regardless of what function is used. Technically, this means the
244 * hardware can do MORE than GL or Vulkan specify. However, it also
245 * means that, for MIN and MAX, we have to stomp the blend factor to
246 * ONE to make it a no-op.
247 */
248 if (a->colorBlendOp == VK_BLEND_OP_MIN ||
249 a->colorBlendOp == VK_BLEND_OP_MAX) {
250 blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
251 blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
252 }
253 if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
254 a->alphaBlendOp == VK_BLEND_OP_MAX) {
255 blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
256 blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
257 }
258 }
259
260 GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
261
262 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
263 .BlendStatePointer = pipeline->blend_state.offset,
264 .BlendStatePointerValid = true);
265 }
266
267 static const uint32_t vk_to_gen_compare_op[] = {
268 [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
269 [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
270 [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
271 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
272 [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
273 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
274 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
275 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
276 };
277
278 static const uint32_t vk_to_gen_stencil_op[] = {
279 [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
280 [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
281 [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
282 [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
283 [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
284 [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
285 [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
286 [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
287 };
288
289 static void
290 emit_ds_state(struct anv_pipeline *pipeline,
291 const VkPipelineDepthStencilStateCreateInfo *info)
292 {
293 uint32_t *dw = ANV_GEN == 8 ?
294 pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
295
296 if (info == NULL) {
297 /* We're going to OR this together with the dynamic state. We need
298 * to make sure it's initialized to something useful.
299 */
300 memset(pipeline->gen8.wm_depth_stencil, 0,
301 sizeof(pipeline->gen8.wm_depth_stencil));
302 memset(pipeline->gen9.wm_depth_stencil, 0,
303 sizeof(pipeline->gen9.wm_depth_stencil));
304 return;
305 }
306
307 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
308
309 struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
310 .DepthTestEnable = info->depthTestEnable,
311 .DepthBufferWriteEnable = info->depthWriteEnable,
312 .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
313 .DoubleSidedStencilEnable = true,
314
315 .StencilTestEnable = info->stencilTestEnable,
316 .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
317 .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
318 .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
319 .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
320 .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
321 .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
322 .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
323 .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
324 };
325
326 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
327 }
328
329 VkResult
330 genX(graphics_pipeline_create)(
331 VkDevice _device,
332 const VkGraphicsPipelineCreateInfo* pCreateInfo,
333 const struct anv_graphics_pipeline_create_info *extra,
334 VkPipeline* pPipeline)
335 {
336 ANV_FROM_HANDLE(anv_device, device, _device);
337 struct anv_pipeline *pipeline;
338 VkResult result;
339 uint32_t offset, length;
340
341 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
342
343 pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
344 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
345 if (pipeline == NULL)
346 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
347
348 result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
349 if (result != VK_SUCCESS)
350 return result;
351
352 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
353 * hard code this to num_attributes - 2. This is because the attributes
354 * include VUE header and position, which aren't counted as varying
355 * inputs. */
356 if (pipeline->vs_simd8 == NO_KERNEL) {
357 pipeline->wm_prog_data.num_varying_inputs =
358 pCreateInfo->pVertexInputState->attributeCount - 2;
359 }
360
361 assert(pCreateInfo->pVertexInputState);
362 emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
363 assert(pCreateInfo->pInputAssemblyState);
364 emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
365 assert(pCreateInfo->pRasterState);
366 emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
367 emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
368 emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
369
370 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS),
371 .StatisticsEnable = true);
372 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), .Enable = false);
373 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), .TEEnable = false);
374 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), .FunctionEnable = false);
375 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
376
377 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
378 .ConstantBufferOffset = 0,
379 .ConstantBufferSize = 4);
380 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS),
381 .ConstantBufferOffset = 4,
382 .ConstantBufferSize = 4);
383 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS),
384 .ConstantBufferOffset = 8,
385 .ConstantBufferSize = 4);
386
387 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM_CHROMAKEY),
388 .ChromaKeyKillEnable = false);
389 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
390
391 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
392 .ClipEnable = true,
393 .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
394 .MinimumPointWidth = 0.125,
395 .MaximumPointWidth = 255.875);
396
397 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
398 .StatisticsEnable = true,
399 .LineEndCapAntialiasingRegionWidth = _05pixels,
400 .LineAntialiasingRegionWidth = _10pixels,
401 .EarlyDepthStencilControl = NORMAL,
402 .ForceThreadDispatchEnable = NORMAL,
403 .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
404 .BarycentricInterpolationMode =
405 pipeline->wm_prog_data.barycentric_interp_modes);
406
407 uint32_t samples = 1;
408 uint32_t log2_samples = __builtin_ffs(samples) - 1;
409 bool enable_sampling = samples > 1 ? true : false;
410
411 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
412 .PixelPositionOffsetEnable = enable_sampling,
413 .PixelLocation = CENTER,
414 .NumberofMultisamples = log2_samples);
415
416 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
417 .SampleMask = 0xffff);
418
419 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
420 .VSURBStartingAddress = pipeline->urb.vs_start,
421 .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
422 .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
423
424 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS),
425 .GSURBStartingAddress = pipeline->urb.gs_start,
426 .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
427 .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
428
429 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS),
430 .HSURBStartingAddress = pipeline->urb.vs_start,
431 .HSURBEntryAllocationSize = 0,
432 .HSNumberofURBEntries = 0);
433
434 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS),
435 .DSURBStartingAddress = pipeline->urb.vs_start,
436 .DSURBEntryAllocationSize = 0,
437 .DSNumberofURBEntries = 0);
438
439 const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
440 offset = 1;
441 length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
442
443 if (pipeline->gs_vec4 == NO_KERNEL)
444 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
445 else
446 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
447 .SingleProgramFlow = false,
448 .KernelStartPointer = pipeline->gs_vec4,
449 .VectorMaskEnable = Dmask,
450 .SamplerCount = 0,
451 .BindingTableEntryCount = 0,
452 .ExpectedVertexCount = pipeline->gs_vertex_count,
453
454 .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
455 .PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
456
457 .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
458 .OutputTopology = gs_prog_data->output_topology,
459 .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
460 .DispatchGRFStartRegisterForURBData =
461 gs_prog_data->base.base.dispatch_grf_start_reg,
462
463 .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
464 .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
465 .DispatchMode = gs_prog_data->base.dispatch_mode,
466 .StatisticsEnable = true,
467 .IncludePrimitiveID = gs_prog_data->include_primitive_id,
468 .ReorderMode = TRAILING,
469 .Enable = true,
470
471 .ControlDataFormat = gs_prog_data->control_data_format,
472
473 .StaticOutput = gs_prog_data->static_vertex_count >= 0,
474 .StaticOutputVertexCount =
475 gs_prog_data->static_vertex_count >= 0 ?
476 gs_prog_data->static_vertex_count : 0,
477
478 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
479 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
480 * UserClipDistanceCullTestEnableBitmask(v)
481 */
482
483 .VertexURBEntryOutputReadOffset = offset,
484 .VertexURBEntryOutputLength = length);
485
486 const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
487 /* Skip the VUE header and position slots */
488 offset = 1;
489 length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
490
491 if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
492 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
493 .FunctionEnable = false,
494 /* Even if VS is disabled, SBE still gets the amount of
495 * vertex data to read from this field. */
496 .VertexURBEntryOutputReadOffset = offset,
497 .VertexURBEntryOutputLength = length);
498 else
499 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
500 .KernelStartPointer = pipeline->vs_simd8,
501 .SingleVertexDispatch = Multiple,
502 .VectorMaskEnable = Dmask,
503 .SamplerCount = 0,
504 .BindingTableEntryCount =
505 vue_prog_data->base.binding_table.size_bytes / 4,
506 .ThreadDispatchPriority = Normal,
507 .FloatingPointMode = IEEE754,
508 .IllegalOpcodeExceptionEnable = false,
509 .AccessesUAV = false,
510 .SoftwareExceptionEnable = false,
511
512 .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
513 .PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
514
515 .DispatchGRFStartRegisterForURBData =
516 vue_prog_data->base.dispatch_grf_start_reg,
517 .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
518 .VertexURBEntryReadOffset = 0,
519
520 .MaximumNumberofThreads = device->info.max_vs_threads - 1,
521 .StatisticsEnable = false,
522 .SIMD8DispatchEnable = true,
523 .VertexCacheDisable = false,
524 .FunctionEnable = true,
525
526 .VertexURBEntryOutputReadOffset = offset,
527 .VertexURBEntryOutputLength = length,
528 .UserClipDistanceClipTestEnableBitmask = 0,
529 .UserClipDistanceCullTestEnableBitmask = 0);
530
531 const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
532
533 /* TODO: We should clean this up. Among other things, this is mostly
534 * shared with other gens.
535 */
536 const struct brw_vue_map *fs_input_map;
537 if (pipeline->gs_vec4 == NO_KERNEL)
538 fs_input_map = &vue_prog_data->vue_map;
539 else
540 fs_input_map = &gs_prog_data->base.vue_map;
541
542 struct GENX(3DSTATE_SBE_SWIZ) swiz = {
543 GENX(3DSTATE_SBE_SWIZ_header),
544 };
545
546 int max_source_attr = 0;
547 for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
548 int input_index = wm_prog_data->urb_setup[attr];
549
550 if (input_index < 0)
551 continue;
552
553 /* We have to subtract two slots to accout for the URB entry output
554 * read offset in the VS and GS stages.
555 */
556 int source_attr = fs_input_map->varying_to_slot[attr] - 2;
557 max_source_attr = MAX2(max_source_attr, source_attr);
558
559 if (input_index >= 16)
560 continue;
561
562 swiz.Attribute[input_index].SourceAttribute = source_attr;
563 }
564
565 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
566 .AttributeSwizzleEnable = true,
567 .ForceVertexURBEntryReadLength = false,
568 .ForceVertexURBEntryReadOffset = false,
569 .VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2),
570 .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
571 .NumberofSFOutputAttributes =
572 wm_prog_data->num_varying_inputs,
573
574 #if ANV_GEN >= 9
575 .Attribute0ActiveComponentFormat = ACF_XYZW,
576 .Attribute1ActiveComponentFormat = ACF_XYZW,
577 .Attribute2ActiveComponentFormat = ACF_XYZW,
578 .Attribute3ActiveComponentFormat = ACF_XYZW,
579 .Attribute4ActiveComponentFormat = ACF_XYZW,
580 .Attribute5ActiveComponentFormat = ACF_XYZW,
581 .Attribute6ActiveComponentFormat = ACF_XYZW,
582 .Attribute7ActiveComponentFormat = ACF_XYZW,
583 .Attribute8ActiveComponentFormat = ACF_XYZW,
584 .Attribute9ActiveComponentFormat = ACF_XYZW,
585 .Attribute10ActiveComponentFormat = ACF_XYZW,
586 .Attribute11ActiveComponentFormat = ACF_XYZW,
587 .Attribute12ActiveComponentFormat = ACF_XYZW,
588 .Attribute13ActiveComponentFormat = ACF_XYZW,
589 .Attribute14ActiveComponentFormat = ACF_XYZW,
590 .Attribute15ActiveComponentFormat = ACF_XYZW,
591 /* wow, much field, very attribute */
592 .Attribute16ActiveComponentFormat = ACF_XYZW,
593 .Attribute17ActiveComponentFormat = ACF_XYZW,
594 .Attribute18ActiveComponentFormat = ACF_XYZW,
595 .Attribute19ActiveComponentFormat = ACF_XYZW,
596 .Attribute20ActiveComponentFormat = ACF_XYZW,
597 .Attribute21ActiveComponentFormat = ACF_XYZW,
598 .Attribute22ActiveComponentFormat = ACF_XYZW,
599 .Attribute23ActiveComponentFormat = ACF_XYZW,
600 .Attribute24ActiveComponentFormat = ACF_XYZW,
601 .Attribute25ActiveComponentFormat = ACF_XYZW,
602 .Attribute26ActiveComponentFormat = ACF_XYZW,
603 .Attribute27ActiveComponentFormat = ACF_XYZW,
604 .Attribute28ActiveComponentFormat = ACF_XYZW,
605 .Attribute29ActiveComponentFormat = ACF_XYZW,
606 .Attribute28ActiveComponentFormat = ACF_XYZW,
607 .Attribute29ActiveComponentFormat = ACF_XYZW,
608 .Attribute30ActiveComponentFormat = ACF_XYZW,
609 #endif
610 );
611
612 uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
613 GENX(3DSTATE_SBE_SWIZ_length));
614 GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
615
616 const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
617 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
618 .KernelStartPointer0 = pipeline->ps_ksp0,
619
620 .SingleProgramFlow = false,
621 .VectorMaskEnable = true,
622 .SamplerCount = 1,
623
624 .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
625 .PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
626
627 .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
628 .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
629 POSOFFSET_SAMPLE: POSOFFSET_NONE,
630 .PushConstantEnable = wm_prog_data->base.nr_params > 0,
631 ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
632 ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
633 ._32PixelDispatchEnable = false,
634
635 .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
636 .DispatchGRFStartRegisterForConstantSetupData1 = 0,
637 .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
638
639 .KernelStartPointer1 = 0,
640 .KernelStartPointer2 = pipeline->ps_ksp2);
641
642 bool per_sample_ps = false;
643 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
644 .PixelShaderValid = true,
645 .PixelShaderKillsPixel = wm_prog_data->uses_kill,
646 .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
647 .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
648 .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
649 .PixelShaderIsPerSample = per_sample_ps,
650 #if ANV_GEN >= 9
651 .PixelShaderPullsBary = wm_prog_data->pulls_bary,
652 .InputCoverageMaskState = ICMS_NONE
653 #endif
654 );
655
656 *pPipeline = anv_pipeline_to_handle(pipeline);
657
658 return VK_SUCCESS;
659 }
660
661 VkResult genX(compute_pipeline_create)(
662 VkDevice _device,
663 const VkComputePipelineCreateInfo* pCreateInfo,
664 VkPipeline* pPipeline)
665 {
666 ANV_FROM_HANDLE(anv_device, device, _device);
667 struct anv_pipeline *pipeline;
668 VkResult result;
669
670 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
671
672 pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
673 VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
674 if (pipeline == NULL)
675 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
676
677 pipeline->device = device;
678 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
679
680 pipeline->blend_state.map = NULL;
681
682 result = anv_reloc_list_init(&pipeline->batch_relocs, device);
683 if (result != VK_SUCCESS) {
684 anv_device_free(device, pipeline);
685 return result;
686 }
687 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
688 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
689 pipeline->batch.relocs = &pipeline->batch_relocs;
690
691 anv_state_stream_init(&pipeline->program_stream,
692 &device->instruction_block_pool);
693
694 /* When we free the pipeline, we detect stages based on the NULL status
695 * of various prog_data pointers. Make them NULL by default.
696 */
697 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
698 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
699
700 pipeline->vs_simd8 = NO_KERNEL;
701 pipeline->vs_vec4 = NO_KERNEL;
702 pipeline->gs_vec4 = NO_KERNEL;
703
704 pipeline->active_stages = 0;
705 pipeline->total_scratch = 0;
706
707 assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE);
708 ANV_FROM_HANDLE(anv_shader, shader, pCreateInfo->stage.shader);
709 anv_pipeline_compile_cs(pipeline, pCreateInfo, shader);
710
711 pipeline->use_repclear = false;
712
713 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
714
715 anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
716 .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_COMPUTE],
717 .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
718 .ScratchSpaceBasePointerHigh = 0,
719 .StackSize = 0,
720
721 .MaximumNumberofThreads = device->info.max_cs_threads - 1,
722 .NumberofURBEntries = 2,
723 .ResetGatewayTimer = true,
724 #if ANV_GEN == 8
725 .BypassGatewayControl = true,
726 #endif
727 .URBEntryAllocationSize = 2,
728 .CURBEAllocationSize = 0);
729
730 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
731 uint32_t group_size = prog_data->local_size[0] *
732 prog_data->local_size[1] * prog_data->local_size[2];
733 pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
734 uint32_t remainder = group_size & (prog_data->simd_size - 1);
735
736 if (remainder > 0)
737 pipeline->cs_right_mask = ~0u >> (32 - remainder);
738 else
739 pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
740
741
742 *pPipeline = anv_pipeline_to_handle(pipeline);
743
744 return VK_SUCCESS;
745 }