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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / vulkan / gen8_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "gen8_pack.h"
33 #include "gen9_pack.h"
34
35 static void
36 emit_vertex_input(struct anv_pipeline *pipeline,
37 const VkPipelineVertexInputStateCreateInfo *info)
38 {
39 const uint32_t num_dwords = 1 + info->vertexAttributeDescriptionCount * 2;
40 uint32_t *p;
41
42 static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
43
44 if (info->vertexAttributeDescriptionCount > 0) {
45 p = anv_batch_emitn(&pipeline->batch, num_dwords,
46 GENX(3DSTATE_VERTEX_ELEMENTS));
47 }
48
49 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
50 const VkVertexInputAttributeDescription *desc =
51 &info->pVertexAttributeDescriptions[i];
52 const struct anv_format *format = anv_format_for_vk_format(desc->format);
53
54 struct GENX(VERTEX_ELEMENT_STATE) element = {
55 .VertexBufferIndex = desc->binding,
56 .Valid = true,
57 .SourceElementFormat = format->surface_format,
58 .EdgeFlagEnable = false,
59 .SourceElementOffset = desc->offset,
60 .Component0Control = VFCOMP_STORE_SRC,
61 .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
62 .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
63 .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
64 };
65 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
66
67 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
68 .InstancingEnable = pipeline->instancing_enable[desc->binding],
69 .VertexElementIndex = i,
70 /* Vulkan so far doesn't have an instance divisor, so
71 * this is always 1 (ignored if not instancing). */
72 .InstanceDataStepRate = 1);
73 }
74
75 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
76 .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
77 .VertexIDComponentNumber = 2,
78 .VertexIDElementOffset = info->vertexBindingDescriptionCount,
79 .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
80 .InstanceIDComponentNumber = 3,
81 .InstanceIDElementOffset = info->vertexBindingDescriptionCount);
82 }
83
84 static void
85 emit_ia_state(struct anv_pipeline *pipeline,
86 const VkPipelineInputAssemblyStateCreateInfo *info,
87 const struct anv_graphics_pipeline_create_info *extra)
88 {
89 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
90 .PrimitiveTopologyType = pipeline->topology);
91 }
92
93 static void
94 emit_rs_state(struct anv_pipeline *pipeline,
95 const VkPipelineRasterizationStateCreateInfo *info,
96 const struct anv_graphics_pipeline_create_info *extra)
97 {
98 static const uint32_t vk_to_gen_cullmode[] = {
99 [VK_CULL_MODE_NONE] = CULLMODE_NONE,
100 [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
101 [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK,
102 [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
103 };
104
105 static const uint32_t vk_to_gen_fillmode[] = {
106 [VK_POLYGON_MODE_FILL] = RASTER_SOLID,
107 [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME,
108 [VK_POLYGON_MODE_POINT] = RASTER_POINT,
109 };
110
111 static const uint32_t vk_to_gen_front_face[] = {
112 [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1,
113 [VK_FRONT_FACE_CLOCKWISE] = 0
114 };
115
116 struct GENX(3DSTATE_SF) sf = {
117 GENX(3DSTATE_SF_header),
118 .ViewportTransformEnable = !(extra && extra->disable_viewport),
119 .TriangleStripListProvokingVertexSelect = 0,
120 .LineStripListProvokingVertexSelect = 0,
121 .TriangleFanProvokingVertexSelect = 0,
122 .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
123 .PointWidth = 1.0,
124 };
125
126 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
127
128 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
129
130 struct GENX(3DSTATE_RASTER) raster = {
131 GENX(3DSTATE_RASTER_header),
132 .FrontWinding = vk_to_gen_front_face[info->frontFace],
133 .CullMode = vk_to_gen_cullmode[info->cullMode],
134 .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
135 .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
136 .ScissorRectangleEnable = !(extra && extra->disable_scissor),
137 #if ANV_GEN == 8
138 .ViewportZClipTestEnable = true,
139 #else
140 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
141 .ViewportZFarClipTestEnable = true,
142 .ViewportZNearClipTestEnable = true,
143 #endif
144 };
145
146 GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
147 }
148
149 static void
150 emit_cb_state(struct anv_pipeline *pipeline,
151 const VkPipelineColorBlendStateCreateInfo *info,
152 const VkPipelineMultisampleStateCreateInfo *ms_info)
153 {
154 struct anv_device *device = pipeline->device;
155
156 static const uint32_t vk_to_gen_logic_op[] = {
157 [VK_LOGIC_OP_COPY] = LOGICOP_COPY,
158 [VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
159 [VK_LOGIC_OP_AND] = LOGICOP_AND,
160 [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
161 [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
162 [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP,
163 [VK_LOGIC_OP_XOR] = LOGICOP_XOR,
164 [VK_LOGIC_OP_OR] = LOGICOP_OR,
165 [VK_LOGIC_OP_NOR] = LOGICOP_NOR,
166 [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV,
167 [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
168 [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
169 [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
170 [VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
171 [VK_LOGIC_OP_NAND] = LOGICOP_NAND,
172 [VK_LOGIC_OP_SET] = LOGICOP_SET,
173 };
174
175 static const uint32_t vk_to_gen_blend[] = {
176 [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO,
177 [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE,
178 [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
179 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
180 [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR,
181 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
182 [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
183 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
184 [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA,
185 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
186 [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
187 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR]= BLENDFACTOR_INV_CONST_COLOR,
188 [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
189 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA]= BLENDFACTOR_INV_CONST_ALPHA,
190 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
191 [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
192 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
193 [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
194 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
195 };
196
197 static const uint32_t vk_to_gen_blend_op[] = {
198 [VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
199 [VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
200 [VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
201 [VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
202 [VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
203 };
204
205 uint32_t num_dwords = GENX(BLEND_STATE_length);
206 pipeline->blend_state =
207 anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
208
209 struct GENX(BLEND_STATE) blend_state = {
210 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
211 .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
212 };
213
214 for (uint32_t i = 0; i < info->attachmentCount; i++) {
215 const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
216
217 if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
218 a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
219 a->colorBlendOp != a->alphaBlendOp) {
220 blend_state.IndependentAlphaBlendEnable = true;
221 }
222
223 blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
224 .LogicOpEnable = info->logicOpEnable,
225 .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
226 .ColorBufferBlendEnable = a->blendEnable,
227 .PreBlendSourceOnlyClampEnable = false,
228 .ColorClampRange = COLORCLAMP_RTFORMAT,
229 .PreBlendColorClampEnable = true,
230 .PostBlendColorClampEnable = true,
231 .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
232 .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
233 .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
234 .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
235 .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
236 .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
237 .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
238 .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
239 .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
240 .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
241 };
242
243 /* Our hardware applies the blend factor prior to the blend function
244 * regardless of what function is used. Technically, this means the
245 * hardware can do MORE than GL or Vulkan specify. However, it also
246 * means that, for MIN and MAX, we have to stomp the blend factor to
247 * ONE to make it a no-op.
248 */
249 if (a->colorBlendOp == VK_BLEND_OP_MIN ||
250 a->colorBlendOp == VK_BLEND_OP_MAX) {
251 blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
252 blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
253 }
254 if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
255 a->alphaBlendOp == VK_BLEND_OP_MAX) {
256 blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
257 blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
258 }
259 }
260
261 GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
262 if (!device->info.has_llc)
263 anv_state_clflush(pipeline->blend_state);
264
265 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
266 .BlendStatePointer = pipeline->blend_state.offset,
267 .BlendStatePointerValid = true);
268 }
269
270 static const uint32_t vk_to_gen_compare_op[] = {
271 [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
272 [VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
273 [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
274 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL,
275 [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
276 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
277 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL,
278 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
279 };
280
281 static const uint32_t vk_to_gen_stencil_op[] = {
282 [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
283 [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
284 [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
285 [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT,
286 [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT,
287 [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
288 [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR,
289 [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR,
290 };
291
292 static void
293 emit_ds_state(struct anv_pipeline *pipeline,
294 const VkPipelineDepthStencilStateCreateInfo *info)
295 {
296 uint32_t *dw = ANV_GEN == 8 ?
297 pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
298
299 if (info == NULL) {
300 /* We're going to OR this together with the dynamic state. We need
301 * to make sure it's initialized to something useful.
302 */
303 memset(pipeline->gen8.wm_depth_stencil, 0,
304 sizeof(pipeline->gen8.wm_depth_stencil));
305 memset(pipeline->gen9.wm_depth_stencil, 0,
306 sizeof(pipeline->gen9.wm_depth_stencil));
307 return;
308 }
309
310 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
311
312 struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
313 .DepthTestEnable = info->depthTestEnable,
314 .DepthBufferWriteEnable = info->depthWriteEnable,
315 .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
316 .DoubleSidedStencilEnable = true,
317
318 .StencilTestEnable = info->stencilTestEnable,
319 .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
320 .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
321 .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
322 .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
323 .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
324 .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
325 .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
326 .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
327 };
328
329 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
330 }
331
332 VkResult
333 genX(graphics_pipeline_create)(
334 VkDevice _device,
335 const VkGraphicsPipelineCreateInfo* pCreateInfo,
336 const struct anv_graphics_pipeline_create_info *extra,
337 const VkAllocationCallbacks* pAllocator,
338 VkPipeline* pPipeline)
339 {
340 ANV_FROM_HANDLE(anv_device, device, _device);
341 struct anv_pipeline *pipeline;
342 VkResult result;
343 uint32_t offset, length;
344
345 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
346
347 pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
348 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
349 if (pipeline == NULL)
350 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
351
352 result = anv_pipeline_init(pipeline, device, pCreateInfo, extra, pAllocator);
353 if (result != VK_SUCCESS)
354 return result;
355
356 assert(pCreateInfo->pVertexInputState);
357 emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
358 assert(pCreateInfo->pInputAssemblyState);
359 emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
360 assert(pCreateInfo->pRasterizationState);
361 emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
362 emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
363 emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
364 pCreateInfo->pMultisampleState);
365
366 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_STATISTICS),
367 .StatisticsEnable = true);
368 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), .Enable = false);
369 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), .TEEnable = false);
370 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), .FunctionEnable = false);
371 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_STREAMOUT), .SOFunctionEnable = false);
372
373 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS),
374 .ConstantBufferOffset = 0,
375 .ConstantBufferSize = 4);
376 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS),
377 .ConstantBufferOffset = 4,
378 .ConstantBufferSize = 4);
379 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS),
380 .ConstantBufferOffset = 8,
381 .ConstantBufferSize = 4);
382
383 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM_CHROMAKEY),
384 .ChromaKeyKillEnable = false);
385 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_AA_LINE_PARAMETERS));
386
387 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
388 .ClipEnable = true,
389 .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
390 .MinimumPointWidth = 0.125,
391 .MaximumPointWidth = 255.875);
392
393 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
394 .StatisticsEnable = true,
395 .LineEndCapAntialiasingRegionWidth = _05pixels,
396 .LineAntialiasingRegionWidth = _10pixels,
397 .EarlyDepthStencilControl = NORMAL,
398 .ForceThreadDispatchEnable = NORMAL,
399 .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
400 .BarycentricInterpolationMode =
401 pipeline->wm_prog_data.barycentric_interp_modes);
402
403 uint32_t samples = 1;
404 uint32_t log2_samples = __builtin_ffs(samples) - 1;
405 bool enable_sampling = samples > 1 ? true : false;
406
407 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
408 .PixelPositionOffsetEnable = enable_sampling,
409 .PixelLocation = CENTER,
410 .NumberofMultisamples = log2_samples);
411
412 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
413 .SampleMask = 0xffff);
414
415 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_VS),
416 .VSURBStartingAddress = pipeline->urb.vs_start,
417 .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
418 .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
419
420 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_GS),
421 .GSURBStartingAddress = pipeline->urb.gs_start,
422 .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
423 .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
424
425 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_HS),
426 .HSURBStartingAddress = pipeline->urb.vs_start,
427 .HSURBEntryAllocationSize = 0,
428 .HSNumberofURBEntries = 0);
429
430 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_URB_DS),
431 .DSURBStartingAddress = pipeline->urb.vs_start,
432 .DSURBEntryAllocationSize = 0,
433 .DSNumberofURBEntries = 0);
434
435 const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
436 offset = 1;
437 length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
438
439 if (pipeline->gs_vec4 == NO_KERNEL)
440 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
441 else
442 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
443 .SingleProgramFlow = false,
444 .KernelStartPointer = pipeline->gs_vec4,
445 .VectorMaskEnable = Dmask,
446 .SamplerCount = 0,
447 .BindingTableEntryCount = 0,
448 .ExpectedVertexCount = pipeline->gs_vertex_count,
449
450 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
451 .PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
452
453 .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
454 .OutputTopology = gs_prog_data->output_topology,
455 .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
456 .DispatchGRFStartRegisterForURBData =
457 gs_prog_data->base.base.dispatch_grf_start_reg,
458
459 .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
460 .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
461 .DispatchMode = gs_prog_data->base.dispatch_mode,
462 .StatisticsEnable = true,
463 .IncludePrimitiveID = gs_prog_data->include_primitive_id,
464 .ReorderMode = TRAILING,
465 .Enable = true,
466
467 .ControlDataFormat = gs_prog_data->control_data_format,
468
469 .StaticOutput = gs_prog_data->static_vertex_count >= 0,
470 .StaticOutputVertexCount =
471 gs_prog_data->static_vertex_count >= 0 ?
472 gs_prog_data->static_vertex_count : 0,
473
474 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
475 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
476 * UserClipDistanceCullTestEnableBitmask(v)
477 */
478
479 .VertexURBEntryOutputReadOffset = offset,
480 .VertexURBEntryOutputLength = length);
481
482 const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
483 /* Skip the VUE header and position slots */
484 offset = 1;
485 length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
486
487 uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
488 pipeline->vs_vec4;
489
490 if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
491 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
492 .FunctionEnable = false,
493 /* Even if VS is disabled, SBE still gets the amount of
494 * vertex data to read from this field. */
495 .VertexURBEntryOutputReadOffset = offset,
496 .VertexURBEntryOutputLength = length);
497 else
498 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
499 .KernelStartPointer = vs_start,
500 .SingleVertexDispatch = Multiple,
501 .VectorMaskEnable = Dmask,
502 .SamplerCount = 0,
503 .BindingTableEntryCount =
504 vue_prog_data->base.binding_table.size_bytes / 4,
505 .ThreadDispatchPriority = Normal,
506 .FloatingPointMode = IEEE754,
507 .IllegalOpcodeExceptionEnable = false,
508 .AccessesUAV = false,
509 .SoftwareExceptionEnable = false,
510
511 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
512 .PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
513
514 .DispatchGRFStartRegisterForURBData =
515 vue_prog_data->base.dispatch_grf_start_reg,
516 .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
517 .VertexURBEntryReadOffset = 0,
518
519 .MaximumNumberofThreads = device->info.max_vs_threads - 1,
520 .StatisticsEnable = false,
521 .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
522 .VertexCacheDisable = false,
523 .FunctionEnable = true,
524
525 .VertexURBEntryOutputReadOffset = offset,
526 .VertexURBEntryOutputLength = length,
527 .UserClipDistanceClipTestEnableBitmask = 0,
528 .UserClipDistanceCullTestEnableBitmask = 0);
529
530 const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
531
532 /* TODO: We should clean this up. Among other things, this is mostly
533 * shared with other gens.
534 */
535 const struct brw_vue_map *fs_input_map;
536 if (pipeline->gs_vec4 == NO_KERNEL)
537 fs_input_map = &vue_prog_data->vue_map;
538 else
539 fs_input_map = &gs_prog_data->base.vue_map;
540
541 struct GENX(3DSTATE_SBE_SWIZ) swiz = {
542 GENX(3DSTATE_SBE_SWIZ_header),
543 };
544
545 int max_source_attr = 0;
546 for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
547 int input_index = wm_prog_data->urb_setup[attr];
548
549 if (input_index < 0)
550 continue;
551
552 /* We have to subtract two slots to accout for the URB entry output
553 * read offset in the VS and GS stages.
554 */
555 int source_attr = fs_input_map->varying_to_slot[attr] - 2;
556 max_source_attr = MAX2(max_source_attr, source_attr);
557
558 if (input_index >= 16)
559 continue;
560
561 swiz.Attribute[input_index].SourceAttribute = source_attr;
562 }
563
564 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
565 .AttributeSwizzleEnable = true,
566 .ForceVertexURBEntryReadLength = false,
567 .ForceVertexURBEntryReadOffset = false,
568 .VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2),
569 .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
570 .NumberofSFOutputAttributes =
571 wm_prog_data->num_varying_inputs,
572
573 #if ANV_GEN >= 9
574 .Attribute0ActiveComponentFormat = ACF_XYZW,
575 .Attribute1ActiveComponentFormat = ACF_XYZW,
576 .Attribute2ActiveComponentFormat = ACF_XYZW,
577 .Attribute3ActiveComponentFormat = ACF_XYZW,
578 .Attribute4ActiveComponentFormat = ACF_XYZW,
579 .Attribute5ActiveComponentFormat = ACF_XYZW,
580 .Attribute6ActiveComponentFormat = ACF_XYZW,
581 .Attribute7ActiveComponentFormat = ACF_XYZW,
582 .Attribute8ActiveComponentFormat = ACF_XYZW,
583 .Attribute9ActiveComponentFormat = ACF_XYZW,
584 .Attribute10ActiveComponentFormat = ACF_XYZW,
585 .Attribute11ActiveComponentFormat = ACF_XYZW,
586 .Attribute12ActiveComponentFormat = ACF_XYZW,
587 .Attribute13ActiveComponentFormat = ACF_XYZW,
588 .Attribute14ActiveComponentFormat = ACF_XYZW,
589 .Attribute15ActiveComponentFormat = ACF_XYZW,
590 /* wow, much field, very attribute */
591 .Attribute16ActiveComponentFormat = ACF_XYZW,
592 .Attribute17ActiveComponentFormat = ACF_XYZW,
593 .Attribute18ActiveComponentFormat = ACF_XYZW,
594 .Attribute19ActiveComponentFormat = ACF_XYZW,
595 .Attribute20ActiveComponentFormat = ACF_XYZW,
596 .Attribute21ActiveComponentFormat = ACF_XYZW,
597 .Attribute22ActiveComponentFormat = ACF_XYZW,
598 .Attribute23ActiveComponentFormat = ACF_XYZW,
599 .Attribute24ActiveComponentFormat = ACF_XYZW,
600 .Attribute25ActiveComponentFormat = ACF_XYZW,
601 .Attribute26ActiveComponentFormat = ACF_XYZW,
602 .Attribute27ActiveComponentFormat = ACF_XYZW,
603 .Attribute28ActiveComponentFormat = ACF_XYZW,
604 .Attribute29ActiveComponentFormat = ACF_XYZW,
605 .Attribute28ActiveComponentFormat = ACF_XYZW,
606 .Attribute29ActiveComponentFormat = ACF_XYZW,
607 .Attribute30ActiveComponentFormat = ACF_XYZW,
608 #endif
609 );
610
611 uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
612 GENX(3DSTATE_SBE_SWIZ_length));
613 GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
614
615 const int num_thread_bias = ANV_GEN == 8 ? 2 : 1;
616 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
617 .KernelStartPointer0 = pipeline->ps_ksp0,
618
619 .SingleProgramFlow = false,
620 .VectorMaskEnable = true,
621 .SamplerCount = 1,
622
623 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
624 .PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
625
626 .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
627 .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
628 POSOFFSET_SAMPLE: POSOFFSET_NONE,
629 .PushConstantEnable = wm_prog_data->base.nr_params > 0,
630 ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
631 ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
632 ._32PixelDispatchEnable = false,
633
634 .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
635 .DispatchGRFStartRegisterForConstantSetupData1 = 0,
636 .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
637
638 .KernelStartPointer1 = 0,
639 .KernelStartPointer2 = pipeline->ps_ksp2);
640
641 bool per_sample_ps = false;
642 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
643 .PixelShaderValid = true,
644 .PixelShaderKillsPixel = wm_prog_data->uses_kill,
645 .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
646 .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
647 .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
648 .PixelShaderIsPerSample = per_sample_ps,
649 #if ANV_GEN >= 9
650 .PixelShaderPullsBary = wm_prog_data->pulls_bary,
651 .InputCoverageMaskState = ICMS_NONE
652 #endif
653 );
654
655 *pPipeline = anv_pipeline_to_handle(pipeline);
656
657 return VK_SUCCESS;
658 }
659
660 VkResult genX(compute_pipeline_create)(
661 VkDevice _device,
662 const VkComputePipelineCreateInfo* pCreateInfo,
663 const VkAllocationCallbacks* pAllocator,
664 VkPipeline* pPipeline)
665 {
666 ANV_FROM_HANDLE(anv_device, device, _device);
667 struct anv_pipeline *pipeline;
668 VkResult result;
669
670 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
671
672 pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
673 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
674 if (pipeline == NULL)
675 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
676
677 pipeline->device = device;
678 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
679
680 pipeline->blend_state.map = NULL;
681
682 result = anv_reloc_list_init(&pipeline->batch_relocs,
683 pAllocator ? pAllocator : &device->alloc);
684 if (result != VK_SUCCESS) {
685 anv_free2(&device->alloc, pAllocator, pipeline);
686 return result;
687 }
688 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
689 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
690 pipeline->batch.relocs = &pipeline->batch_relocs;
691
692 anv_state_stream_init(&pipeline->program_stream,
693 &device->instruction_block_pool);
694
695 /* When we free the pipeline, we detect stages based on the NULL status
696 * of various prog_data pointers. Make them NULL by default.
697 */
698 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
699 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
700
701 pipeline->vs_simd8 = NO_KERNEL;
702 pipeline->vs_vec4 = NO_KERNEL;
703 pipeline->gs_vec4 = NO_KERNEL;
704
705 pipeline->active_stages = 0;
706 pipeline->total_scratch = 0;
707
708 assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
709 ANV_FROM_HANDLE(anv_shader_module, module, pCreateInfo->stage.module);
710 anv_pipeline_compile_cs(pipeline, pCreateInfo, module,
711 pCreateInfo->stage.pName);
712
713 pipeline->use_repclear = false;
714
715 const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
716
717 anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE),
718 .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_COMPUTE],
719 .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
720 .ScratchSpaceBasePointerHigh = 0,
721 .StackSize = 0,
722
723 .MaximumNumberofThreads = device->info.max_cs_threads - 1,
724 .NumberofURBEntries = 2,
725 .ResetGatewayTimer = true,
726 #if ANV_GEN == 8
727 .BypassGatewayControl = true,
728 #endif
729 .URBEntryAllocationSize = 2,
730 .CURBEAllocationSize = 0);
731
732 struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
733 uint32_t group_size = prog_data->local_size[0] *
734 prog_data->local_size[1] * prog_data->local_size[2];
735 pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
736 uint32_t remainder = group_size & (prog_data->simd_size - 1);
737
738 if (remainder > 0)
739 pipeline->cs_right_mask = ~0u >> (32 - remainder);
740 else
741 pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
742
743
744 *pPipeline = anv_pipeline_to_handle(pipeline);
745
746 return VK_SUCCESS;
747 }