src/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 static void
  33 emit_vertex_input(struct anv_pipeline *pipeline,
  34                   const VkPipelineVertexInputStateCreateInfo *info)
  35 {
  36    const uint32_t num_dwords = 1 + info->attributeCount * 2;
  37    uint32_t *p;
  38
  39    p = anv_batch_emitn(&pipeline->batch, num_dwords,
  40                        GEN8_3DSTATE_VERTEX_ELEMENTS);
  41
  42    for (uint32_t i = 0; i < info->attributeCount; i++) {
  43       const VkVertexInputAttributeDescription *desc =
  44          &info->pVertexAttributeDescriptions[i];
  45       const struct anv_format *format = anv_format_for_vk_format(desc->format);
  46
  47       struct GEN8_VERTEX_ELEMENT_STATE element = {
  48          .VertexBufferIndex = desc->binding,
  49          .Valid = true,
  50          .SourceElementFormat = format->surface_format,
  51          .EdgeFlagEnable = false,
  52          .SourceElementOffset = desc->offsetInBytes,
  53          .Component0Control = VFCOMP_STORE_SRC,
  54          .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  55          .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
  56          .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
  57       };
  58       GEN8_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
  59
  60       anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_INSTANCING,
  61                      .InstancingEnable = pipeline->instancing_enable[desc->binding],
  62                      .VertexElementIndex = i,
  63                      /* Vulkan so far doesn't have an instance divisor, so
  64                       * this is always 1 (ignored if not instancing). */
  65                      .InstanceDataStepRate = 1);
  66    }
  67
  68    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_SGVS,
  69                   .VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
  70                   .VertexIDComponentNumber = 2,
  71                   .VertexIDElementOffset = info->bindingCount,
  72                   .InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
  73                   .InstanceIDComponentNumber = 3,
  74                   .InstanceIDElementOffset = info->bindingCount);
  75 }
  76
  77 static void
  78 emit_ia_state(struct anv_pipeline *pipeline,
  79               const VkPipelineInputAssemblyStateCreateInfo *info,
  80               const struct anv_graphics_pipeline_create_info *extra)
  81 {
  82    struct GEN8_3DSTATE_VF vf = {
  83       GEN8_3DSTATE_VF_header,
  84       .IndexedDrawCutIndexEnable = pipeline->primitive_restart
  85    };
  86    GEN8_3DSTATE_VF_pack(NULL, pipeline->gen8.vf, &vf);
  87
  88    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_TOPOLOGY,
  89                   .PrimitiveTopologyType = pipeline->topology);
  90 }
  91
  92 static void
  93 emit_rs_state(struct anv_pipeline *pipeline,
  94               const VkPipelineRasterStateCreateInfo *info,
  95               const struct anv_graphics_pipeline_create_info *extra)
  96 {
  97    static const uint32_t vk_to_gen_cullmode[] = {
  98       [VK_CULL_MODE_NONE]                       = CULLMODE_NONE,
  99       [VK_CULL_MODE_FRONT]                      = CULLMODE_FRONT,
 100       [VK_CULL_MODE_BACK]                       = CULLMODE_BACK,
 101       [VK_CULL_MODE_FRONT_AND_BACK]             = CULLMODE_BOTH
 102    };
 103
 104    static const uint32_t vk_to_gen_fillmode[] = {
 105       [VK_FILL_MODE_POINTS]                     = RASTER_POINT,
 106       [VK_FILL_MODE_WIREFRAME]                  = RASTER_WIREFRAME,
 107       [VK_FILL_MODE_SOLID]                      = RASTER_SOLID
 108    };
 109
 110    static const uint32_t vk_to_gen_front_face[] = {
 111       [VK_FRONT_FACE_CCW]                       = CounterClockwise,
 112       [VK_FRONT_FACE_CW]                        = Clockwise
 113    };
 114
 115    struct GEN8_3DSTATE_SF sf = {
 116       GEN8_3DSTATE_SF_header,
 117       .ViewportTransformEnable = !(extra && extra->disable_viewport),
 118       .TriangleStripListProvokingVertexSelect = 0,
 119       .LineStripListProvokingVertexSelect = 0,
 120       .TriangleFanProvokingVertexSelect = 0,
 121       .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
 122       .PointWidth = 1.0,
 123    };
 124
 125    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
 126
 127    GEN8_3DSTATE_SF_pack(NULL, pipeline->gen8.sf, &sf);
 128
 129    struct GEN8_3DSTATE_RASTER raster = {
 130       GEN8_3DSTATE_RASTER_header,
 131       .FrontWinding = vk_to_gen_front_face[info->frontFace],
 132       .CullMode = vk_to_gen_cullmode[info->cullMode],
 133       .FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode],
 134       .BackFaceFillMode = vk_to_gen_fillmode[info->fillMode],
 135       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
 136       .ViewportZClipTestEnable = info->depthClipEnable
 137    };
 138
 139    GEN8_3DSTATE_RASTER_pack(NULL, pipeline->gen8.raster, &raster);
 140 }
 141
 142 static void
 143 emit_cb_state(struct anv_pipeline *pipeline,
 144               const VkPipelineColorBlendStateCreateInfo *info)
 145 {
 146    struct anv_device *device = pipeline->device;
 147
 148    static const uint32_t vk_to_gen_logic_op[] = {
 149       [VK_LOGIC_OP_COPY]                        = LOGICOP_COPY,
 150       [VK_LOGIC_OP_CLEAR]                       = LOGICOP_CLEAR,
 151       [VK_LOGIC_OP_AND]                         = LOGICOP_AND,
 152       [VK_LOGIC_OP_AND_REVERSE]                 = LOGICOP_AND_REVERSE,
 153       [VK_LOGIC_OP_AND_INVERTED]                = LOGICOP_AND_INVERTED,
 154       [VK_LOGIC_OP_NOOP]                        = LOGICOP_NOOP,
 155       [VK_LOGIC_OP_XOR]                         = LOGICOP_XOR,
 156       [VK_LOGIC_OP_OR]                          = LOGICOP_OR,
 157       [VK_LOGIC_OP_NOR]                         = LOGICOP_NOR,
 158       [VK_LOGIC_OP_EQUIV]                       = LOGICOP_EQUIV,
 159       [VK_LOGIC_OP_INVERT]                      = LOGICOP_INVERT,
 160       [VK_LOGIC_OP_OR_REVERSE]                  = LOGICOP_OR_REVERSE,
 161       [VK_LOGIC_OP_COPY_INVERTED]               = LOGICOP_COPY_INVERTED,
 162       [VK_LOGIC_OP_OR_INVERTED]                 = LOGICOP_OR_INVERTED,
 163       [VK_LOGIC_OP_NAND]                        = LOGICOP_NAND,
 164       [VK_LOGIC_OP_SET]                         = LOGICOP_SET,
 165    };
 166
 167    static const uint32_t vk_to_gen_blend[] = {
 168       [VK_BLEND_ZERO]                           = BLENDFACTOR_ZERO,
 169       [VK_BLEND_ONE]                            = BLENDFACTOR_ONE,
 170       [VK_BLEND_SRC_COLOR]                      = BLENDFACTOR_SRC_COLOR,
 171       [VK_BLEND_ONE_MINUS_SRC_COLOR]            = BLENDFACTOR_INV_SRC_COLOR,
 172       [VK_BLEND_DEST_COLOR]                     = BLENDFACTOR_DST_COLOR,
 173       [VK_BLEND_ONE_MINUS_DEST_COLOR]           = BLENDFACTOR_INV_DST_COLOR,
 174       [VK_BLEND_SRC_ALPHA]                      = BLENDFACTOR_SRC_ALPHA,
 175       [VK_BLEND_ONE_MINUS_SRC_ALPHA]            = BLENDFACTOR_INV_SRC_ALPHA,
 176       [VK_BLEND_DEST_ALPHA]                     = BLENDFACTOR_DST_ALPHA,
 177       [VK_BLEND_ONE_MINUS_DEST_ALPHA]           = BLENDFACTOR_INV_DST_ALPHA,
 178       [VK_BLEND_CONSTANT_COLOR]                 = BLENDFACTOR_CONST_COLOR,
 179       [VK_BLEND_ONE_MINUS_CONSTANT_COLOR]       = BLENDFACTOR_INV_CONST_COLOR,
 180       [VK_BLEND_CONSTANT_ALPHA]                 = BLENDFACTOR_CONST_ALPHA,
 181       [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA]       = BLENDFACTOR_INV_CONST_ALPHA,
 182       [VK_BLEND_SRC_ALPHA_SATURATE]             = BLENDFACTOR_SRC_ALPHA_SATURATE,
 183       [VK_BLEND_SRC1_COLOR]                     = BLENDFACTOR_SRC1_COLOR,
 184       [VK_BLEND_ONE_MINUS_SRC1_COLOR]           = BLENDFACTOR_INV_SRC1_COLOR,
 185       [VK_BLEND_SRC1_ALPHA]                     = BLENDFACTOR_SRC1_ALPHA,
 186       [VK_BLEND_ONE_MINUS_SRC1_ALPHA]           = BLENDFACTOR_INV_SRC1_ALPHA,
 187    };
 188
 189    static const uint32_t vk_to_gen_blend_op[] = {
 190       [VK_BLEND_OP_ADD]                         = BLENDFUNCTION_ADD,
 191       [VK_BLEND_OP_SUBTRACT]                    = BLENDFUNCTION_SUBTRACT,
 192       [VK_BLEND_OP_REVERSE_SUBTRACT]            = BLENDFUNCTION_REVERSE_SUBTRACT,
 193       [VK_BLEND_OP_MIN]                         = BLENDFUNCTION_MIN,
 194       [VK_BLEND_OP_MAX]                         = BLENDFUNCTION_MAX,
 195    };
 196
 197    uint32_t num_dwords = GEN8_BLEND_STATE_length;
 198    pipeline->blend_state =
 199       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 200
 201    struct GEN8_BLEND_STATE blend_state = {
 202       .AlphaToCoverageEnable = info->alphaToCoverageEnable,
 203    };
 204
 205    for (uint32_t i = 0; i < info->attachmentCount; i++) {
 206       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
 207
 208       blend_state.Entry[i] = (struct GEN8_BLEND_STATE_ENTRY) {
 209          .LogicOpEnable = info->logicOpEnable,
 210          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 211          .ColorBufferBlendEnable = a->blendEnable,
 212          .PreBlendSourceOnlyClampEnable = false,
 213          .PreBlendColorClampEnable = false,
 214          .PostBlendColorClampEnable = false,
 215          .SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
 216          .DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
 217          .ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
 218          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
 219          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
 220          .AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
 221          .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
 222          .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
 223          .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
 224          .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
 225       };
 226    }
 227
 228    GEN8_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
 229
 230    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_BLEND_STATE_POINTERS,
 231                   .BlendStatePointer = pipeline->blend_state.offset,
 232                   .BlendStatePointerValid = true);
 233 }
 234
 235 static const uint32_t vk_to_gen_compare_op[] = {
 236    [VK_COMPARE_OP_NEVER]                        = COMPAREFUNCTION_NEVER,
 237    [VK_COMPARE_OP_LESS]                         = COMPAREFUNCTION_LESS,
 238    [VK_COMPARE_OP_EQUAL]                        = COMPAREFUNCTION_EQUAL,
 239    [VK_COMPARE_OP_LESS_EQUAL]                   = COMPAREFUNCTION_LEQUAL,
 240    [VK_COMPARE_OP_GREATER]                      = COMPAREFUNCTION_GREATER,
 241    [VK_COMPARE_OP_NOT_EQUAL]                    = COMPAREFUNCTION_NOTEQUAL,
 242    [VK_COMPARE_OP_GREATER_EQUAL]                = COMPAREFUNCTION_GEQUAL,
 243    [VK_COMPARE_OP_ALWAYS]                       = COMPAREFUNCTION_ALWAYS,
 244 };
 245
 246 static const uint32_t vk_to_gen_stencil_op[] = {
 247    [VK_STENCIL_OP_KEEP]                         = 0,
 248    [VK_STENCIL_OP_ZERO]                         = 0,
 249    [VK_STENCIL_OP_REPLACE]                      = 0,
 250    [VK_STENCIL_OP_INC_CLAMP]                    = 0,
 251    [VK_STENCIL_OP_DEC_CLAMP]                    = 0,
 252    [VK_STENCIL_OP_INVERT]                       = 0,
 253    [VK_STENCIL_OP_INC_WRAP]                     = 0,
 254    [VK_STENCIL_OP_DEC_WRAP]                     = 0
 255 };
 256
 257 static void
 258 emit_ds_state(struct anv_pipeline *pipeline,
 259               const VkPipelineDepthStencilStateCreateInfo *info)
 260 {
 261    if (info == NULL) {
 262       /* We're going to OR this together with the dynamic state.  We need
 263        * to make sure it's initialized to something useful.
 264        */
 265       memset(pipeline->gen8.wm_depth_stencil, 0,
 266              sizeof(pipeline->gen8.wm_depth_stencil));
 267       return;
 268    }
 269
 270    /* VkBool32 depthBoundsEnable;          // optional (depth_bounds_test) */
 271
 272    struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 273       .DepthTestEnable = info->depthTestEnable,
 274       .DepthBufferWriteEnable = info->depthWriteEnable,
 275       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 276       .DoubleSidedStencilEnable = true,
 277
 278       .StencilTestEnable = info->stencilTestEnable,
 279       .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
 280       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
 281       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
 282       .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
 283       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
 284       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
 285       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
 286       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
 287    };
 288
 289    GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, pipeline->gen8.wm_depth_stencil, &wm_depth_stencil);
 290 }
 291
 292 VkResult
 293 gen8_graphics_pipeline_create(
 294     VkDevice                                    _device,
 295     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 296     const struct anv_graphics_pipeline_create_info *extra,
 297     VkPipeline*                                 pPipeline)
 298 {
 299    ANV_FROM_HANDLE(anv_device, device, _device);
 300    struct anv_pipeline *pipeline;
 301    VkResult result;
 302    uint32_t offset, length;
 303
 304    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 305
 306    pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
 307                                VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 308    if (pipeline == NULL)
 309       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 310
 311    result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
 312    if (result != VK_SUCCESS)
 313       return result;
 314
 315    /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
 316     * hard code this to num_attributes - 2. This is because the attributes
 317     * include VUE header and position, which aren't counted as varying
 318     * inputs. */
 319    if (pipeline->vs_simd8 == NO_KERNEL) {
 320       pipeline->wm_prog_data.num_varying_inputs =
 321          pCreateInfo->pVertexInputState->attributeCount - 2;
 322    }
 323
 324    assert(pCreateInfo->pVertexInputState);
 325    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
 326    assert(pCreateInfo->pInputAssemblyState);
 327    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 328    assert(pCreateInfo->pRasterState);
 329    emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
 330    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 331    emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
 332
 333    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VF_STATISTICS,
 334                    .StatisticsEnable = true);
 335    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_HS, .Enable = false);
 336    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_TE, .TEEnable = false);
 337    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_DS, .FunctionEnable = false);
 338    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
 339
 340    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
 341                   .ConstantBufferOffset = 0,
 342                   .ConstantBufferSize = 4);
 343    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
 344                   .ConstantBufferOffset = 4,
 345                   .ConstantBufferSize = 4);
 346    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
 347                   .ConstantBufferOffset = 8,
 348                   .ConstantBufferSize = 4);
 349
 350    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_WM_CHROMAKEY,
 351                   .ChromaKeyKillEnable = false);
 352    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_SBE_SWIZ);
 353    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_AA_LINE_PARAMETERS);
 354
 355    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_CLIP,
 356                   .ClipEnable = true,
 357                   .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
 358                   .MinimumPointWidth = 0.125,
 359                   .MaximumPointWidth = 255.875);
 360
 361    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_WM,
 362                   .StatisticsEnable = true,
 363                   .LineEndCapAntialiasingRegionWidth = _05pixels,
 364                   .LineAntialiasingRegionWidth = _10pixels,
 365                   .EarlyDepthStencilControl = NORMAL,
 366                   .ForceThreadDispatchEnable = NORMAL,
 367                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
 368                   .BarycentricInterpolationMode =
 369                      pipeline->wm_prog_data.barycentric_interp_modes);
 370
 371    uint32_t samples = 1;
 372    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 373    bool enable_sampling = samples > 1 ? true : false;
 374
 375    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_MULTISAMPLE,
 376                   .PixelPositionOffsetEnable = enable_sampling,
 377                   .PixelLocation = CENTER,
 378                   .NumberofMultisamples = log2_samples);
 379
 380    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_SAMPLE_MASK,
 381                   .SampleMask = 0xffff);
 382
 383    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_VS,
 384                   .VSURBStartingAddress = pipeline->urb.vs_start,
 385                   .VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
 386                   .VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
 387
 388    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_GS,
 389                   .GSURBStartingAddress = pipeline->urb.gs_start,
 390                   .GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
 391                   .GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
 392
 393    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_HS,
 394                   .HSURBStartingAddress = pipeline->urb.vs_start,
 395                   .HSURBEntryAllocationSize = 0,
 396                   .HSNumberofURBEntries = 0);
 397
 398    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_URB_DS,
 399                   .DSURBStartingAddress = pipeline->urb.vs_start,
 400                   .DSURBEntryAllocationSize = 0,
 401                   .DSNumberofURBEntries = 0);
 402
 403    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 404    offset = 1;
 405    length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 406
 407    if (pipeline->gs_vec4 == NO_KERNEL)
 408       anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS, .Enable = false);
 409    else
 410       anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_GS,
 411                      .SingleProgramFlow = false,
 412                      .KernelStartPointer = pipeline->gs_vec4,
 413                      .VectorMaskEnable = Vmask,
 414                      .SamplerCount = 0,
 415                      .BindingTableEntryCount = 0,
 416                      .ExpectedVertexCount = pipeline->gs_vertex_count,
 417
 418                      .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
 419                      .PerThreadScratchSpace = ffs(gs_prog_data->base.base.total_scratch / 2048),
 420
 421                      .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 422                      .OutputTopology = gs_prog_data->output_topology,
 423                      .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
 424                      .DispatchGRFStartRegisterForURBData =
 425                         gs_prog_data->base.base.dispatch_grf_start_reg,
 426
 427                      .MaximumNumberofThreads = device->info.max_gs_threads,
 428                      .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
 429                      //pipeline->gs_prog_data.dispatch_mode |
 430                      .StatisticsEnable = true,
 431                      .IncludePrimitiveID = gs_prog_data->include_primitive_id,
 432                      .ReorderMode = TRAILING,
 433                      .Enable = true,
 434
 435                      .ControlDataFormat = gs_prog_data->control_data_format,
 436
 437                      /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 438                       * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 439                       * UserClipDistanceCullTestEnableBitmask(v)
 440                       */
 441
 442                      .VertexURBEntryOutputReadOffset = offset,
 443                      .VertexURBEntryOutputLength = length);
 444
 445    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 446    /* Skip the VUE header and position slots */
 447    offset = 1;
 448    length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
 449
 450    if (pipeline->vs_simd8 == NO_KERNEL || (extra && extra->disable_vs))
 451       anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
 452                      .FunctionEnable = false,
 453                      /* Even if VS is disabled, SBE still gets the amount of
 454                       * vertex data to read from this field. */
 455                      .VertexURBEntryOutputReadOffset = offset,
 456                      .VertexURBEntryOutputLength = length);
 457    else
 458       anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_VS,
 459                      .KernelStartPointer = pipeline->vs_simd8,
 460                      .SingleVertexDispatch = Multiple,
 461                      .VectorMaskEnable = Dmask,
 462                      .SamplerCount = 0,
 463                      .BindingTableEntryCount =
 464                      vue_prog_data->base.binding_table.size_bytes / 4,
 465                      .ThreadDispatchPriority = Normal,
 466                      .FloatingPointMode = IEEE754,
 467                      .IllegalOpcodeExceptionEnable = false,
 468                      .AccessesUAV = false,
 469                      .SoftwareExceptionEnable = false,
 470
 471                      .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
 472                      .PerThreadScratchSpace = ffs(vue_prog_data->base.total_scratch / 2048),
 473
 474                      .DispatchGRFStartRegisterForURBData =
 475                      vue_prog_data->base.dispatch_grf_start_reg,
 476                      .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
 477                      .VertexURBEntryReadOffset = 0,
 478
 479                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
 480                      .StatisticsEnable = false,
 481                      .SIMD8DispatchEnable = true,
 482                      .VertexCacheDisable = false,
 483                      .FunctionEnable = true,
 484
 485                      .VertexURBEntryOutputReadOffset = offset,
 486                      .VertexURBEntryOutputLength = length,
 487                      .UserClipDistanceClipTestEnableBitmask = 0,
 488                      .UserClipDistanceCullTestEnableBitmask = 0);
 489
 490    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 491
 492    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_SBE,
 493                   .ForceVertexURBEntryReadLength = false,
 494                   .ForceVertexURBEntryReadOffset = false,
 495                   .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 496                   .NumberofSFOutputAttributes =
 497                      wm_prog_data->num_varying_inputs);
 498
 499    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS,
 500                   .KernelStartPointer0 = pipeline->ps_ksp0,
 501
 502                   .SingleProgramFlow = false,
 503                   .VectorMaskEnable = true,
 504                   .SamplerCount = 1,
 505
 506                   .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
 507                   .PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch / 2048),
 508
 509                   .MaximumNumberofThreadsPerPSD = 64 - 2,
 510                   .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
 511                      POSOFFSET_SAMPLE: POSOFFSET_NONE,
 512                   .PushConstantEnable = wm_prog_data->base.nr_params > 0,
 513                   ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
 514                   ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
 515                   ._32PixelDispatchEnable = false,
 516
 517                   .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
 518                   .DispatchGRFStartRegisterForConstantSetupData1 = 0,
 519                   .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
 520
 521                   .KernelStartPointer1 = 0,
 522                   .KernelStartPointer2 = pipeline->ps_ksp2);
 523
 524    bool per_sample_ps = false;
 525    anv_batch_emit(&pipeline->batch, GEN8_3DSTATE_PS_EXTRA,
 526                   .PixelShaderValid = true,
 527                   .PixelShaderKillsPixel = wm_prog_data->uses_kill,
 528                   .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
 529                   .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
 530                   .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
 531                   .PixelShaderIsPerSample = per_sample_ps);
 532
 533    *pPipeline = anv_pipeline_to_handle(pipeline);
 534
 535    return VK_SUCCESS;
 536 }
 537
 538 VkResult gen8_compute_pipeline_create(
 539     VkDevice                                    _device,
 540     const VkComputePipelineCreateInfo*          pCreateInfo,
 541     VkPipeline*                                 pPipeline)
 542 {
 543    ANV_FROM_HANDLE(anv_device, device, _device);
 544    struct anv_pipeline *pipeline;
 545    VkResult result;
 546
 547    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO);
 548
 549    pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
 550                                VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
 551    if (pipeline == NULL)
 552       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 553
 554    pipeline->device = device;
 555    pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
 556
 557    result = anv_reloc_list_init(&pipeline->batch_relocs, device);
 558    if (result != VK_SUCCESS) {
 559       anv_device_free(device, pipeline);
 560       return result;
 561    }
 562    pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
 563    pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
 564    pipeline->batch.relocs = &pipeline->batch_relocs;
 565
 566    anv_state_stream_init(&pipeline->program_stream,
 567                          &device->instruction_block_pool);
 568
 569    memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
 570
 571    pipeline->shaders[VK_SHADER_STAGE_COMPUTE] =
 572       anv_shader_from_handle(pCreateInfo->cs.shader);
 573
 574    pipeline->use_repclear = false;
 575
 576    anv_compiler_run(device->compiler, pipeline);
 577
 578    const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
 579
 580    anv_batch_emit(&pipeline->batch, GEN8_MEDIA_VFE_STATE,
 581                   .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
 582                   .PerThreadScratchSpace = ffs(cs_prog_data->base.total_scratch / 2048),
 583                   .ScratchSpaceBasePointerHigh = 0,
 584                   .StackSize = 0,
 585
 586                   .MaximumNumberofThreads = device->info.max_cs_threads - 1,
 587                   .NumberofURBEntries = 2,
 588                   .ResetGatewayTimer = true,
 589                   .BypassGatewayControl = true,
 590                   .URBEntryAllocationSize = 2,
 591                   .CURBEAllocationSize = 0);
 592
 593    struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
 594    uint32_t group_size = prog_data->local_size[0] *
 595       prog_data->local_size[1] * prog_data->local_size[2];
 596    pipeline->cs_thread_width_max = DIV_ROUND_UP(group_size, prog_data->simd_size);
 597    uint32_t remainder = group_size & (prog_data->simd_size - 1);
 598
 599    if (remainder > 0)
 600       pipeline->cs_right_mask = ~0u >> (32 - remainder);
 601    else
 602       pipeline->cs_right_mask = ~0u >> (32 - prog_data->simd_size);
 603
 604
 605    *pPipeline = anv_pipeline_to_handle(pipeline);
 606
 607    return VK_SUCCESS;
 608 }