2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 emit_vertex_input(struct anv_pipeline
*pipeline
,
34 const VkPipelineVertexInputStateCreateInfo
*info
)
36 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
38 bool instancing_enable
[32];
40 pipeline
->vb_used
= 0;
41 for (uint32_t i
= 0; i
< info
->bindingCount
; i
++) {
42 const VkVertexInputBindingDescription
*desc
=
43 &info
->pVertexBindingDescriptions
[i
];
45 pipeline
->vb_used
|= 1 << desc
->binding
;
46 pipeline
->binding_stride
[desc
->binding
] = desc
->strideInBytes
;
48 /* Step rate is programmed per vertex element (attribute), not
49 * binding. Set up a map of which bindings step per instance, for
50 * reference by vertex element setup. */
51 switch (desc
->stepRate
) {
53 case VK_VERTEX_INPUT_STEP_RATE_VERTEX
:
54 instancing_enable
[desc
->binding
] = false;
56 case VK_VERTEX_INPUT_STEP_RATE_INSTANCE
:
57 instancing_enable
[desc
->binding
] = true;
62 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
63 GEN8_3DSTATE_VERTEX_ELEMENTS
);
65 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
66 const VkVertexInputAttributeDescription
*desc
=
67 &info
->pVertexAttributeDescriptions
[i
];
68 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
70 struct GEN8_VERTEX_ELEMENT_STATE element
= {
71 .VertexBufferIndex
= desc
->binding
,
73 .SourceElementFormat
= format
->surface_format
,
74 .EdgeFlagEnable
= false,
75 .SourceElementOffset
= desc
->offsetInBytes
,
76 .Component0Control
= VFCOMP_STORE_SRC
,
77 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
78 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
79 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
81 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
83 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
84 .InstancingEnable
= instancing_enable
[desc
->binding
],
85 .VertexElementIndex
= i
,
86 /* Vulkan so far doesn't have an instance divisor, so
87 * this is always 1 (ignored if not instancing). */
88 .InstanceDataStepRate
= 1);
91 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
92 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
93 .VertexIDComponentNumber
= 2,
94 .VertexIDElementOffset
= info
->bindingCount
,
95 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
96 .InstanceIDComponentNumber
= 3,
97 .InstanceIDElementOffset
= info
->bindingCount
);
101 emit_ia_state(struct anv_pipeline
*pipeline
,
102 const VkPipelineInputAssemblyStateCreateInfo
*info
,
103 const struct anv_graphics_pipeline_create_info
*extra
)
105 static const uint32_t vk_to_gen_primitive_type
[] = {
106 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
107 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
108 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
109 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
110 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
111 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
112 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ
] = _3DPRIM_LINELIST_ADJ
,
113 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ
] = _3DPRIM_LINESTRIP_ADJ
,
114 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ
] = _3DPRIM_TRILIST_ADJ
,
115 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ
] = _3DPRIM_TRISTRIP_ADJ
,
116 [VK_PRIMITIVE_TOPOLOGY_PATCH
] = _3DPRIM_PATCHLIST_1
118 uint32_t topology
= vk_to_gen_primitive_type
[info
->topology
];
120 if (extra
&& extra
->use_rectlist
)
121 topology
= _3DPRIM_RECTLIST
;
123 struct GEN8_3DSTATE_VF vf
= {
124 GEN8_3DSTATE_VF_header
,
125 .IndexedDrawCutIndexEnable
= info
->primitiveRestartEnable
,
127 GEN8_3DSTATE_VF_pack(NULL
, pipeline
->gen8
.vf
, &vf
);
129 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
130 .PrimitiveTopologyType
= topology
);
134 emit_rs_state(struct anv_pipeline
*pipeline
,
135 const VkPipelineRasterStateCreateInfo
*info
,
136 const struct anv_graphics_pipeline_create_info
*extra
)
138 static const uint32_t vk_to_gen_cullmode
[] = {
139 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
140 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
141 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
142 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
145 static const uint32_t vk_to_gen_fillmode
[] = {
146 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
147 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
148 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
151 static const uint32_t vk_to_gen_front_face
[] = {
152 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
153 [VK_FRONT_FACE_CW
] = Clockwise
156 struct GEN8_3DSTATE_SF sf
= {
157 GEN8_3DSTATE_SF_header
,
158 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
159 .TriangleStripListProvokingVertexSelect
= 0,
160 .LineStripListProvokingVertexSelect
= 0,
161 .TriangleFanProvokingVertexSelect
= 0,
162 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
166 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
168 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->gen8
.sf
, &sf
);
170 struct GEN8_3DSTATE_RASTER raster
= {
171 GEN8_3DSTATE_RASTER_header
,
172 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
173 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
174 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
175 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
176 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
177 .ViewportZClipTestEnable
= info
->depthClipEnable
180 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
181 .ForceVertexURBEntryReadLength
= false,
182 .ForceVertexURBEntryReadOffset
= false,
183 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
184 .NumberofSFOutputAttributes
=
185 pipeline
->wm_prog_data
.num_varying_inputs
);
187 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->gen8
.raster
, &raster
);
191 emit_cb_state(struct anv_pipeline
*pipeline
,
192 const VkPipelineColorBlendStateCreateInfo
*info
)
194 struct anv_device
*device
= pipeline
->device
;
196 static const uint32_t vk_to_gen_logic_op
[] = {
197 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
198 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
199 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
200 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
201 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
202 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
203 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
204 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
205 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
206 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
207 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
208 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
209 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
210 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
211 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
212 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
215 static const uint32_t vk_to_gen_blend
[] = {
216 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
217 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
218 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
219 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
220 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
221 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
222 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
223 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
224 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
225 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
226 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
227 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
228 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
229 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
230 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
231 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
232 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
233 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
234 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
237 static const uint32_t vk_to_gen_blend_op
[] = {
238 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
239 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
240 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
241 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
242 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
245 uint32_t num_dwords
= GEN8_BLEND_STATE_length
;
246 pipeline
->blend_state
=
247 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
249 struct GEN8_BLEND_STATE blend_state
= {
250 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
253 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
254 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
256 blend_state
.Entry
[i
] = (struct GEN8_BLEND_STATE_ENTRY
) {
257 .LogicOpEnable
= info
->logicOpEnable
,
258 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
259 .ColorBufferBlendEnable
= a
->blendEnable
,
260 .PreBlendSourceOnlyClampEnable
= false,
261 .PreBlendColorClampEnable
= false,
262 .PostBlendColorClampEnable
= false,
263 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
264 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
265 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
266 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
267 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
268 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
269 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
270 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
271 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
272 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
276 GEN8_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
278 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
279 .BlendStatePointer
= pipeline
->blend_state
.offset
,
280 .BlendStatePointerValid
= true);
283 static const uint32_t vk_to_gen_compare_op
[] = {
284 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
285 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
286 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
287 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
288 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
289 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
290 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
291 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
294 static const uint32_t vk_to_gen_stencil_op
[] = {
295 [VK_STENCIL_OP_KEEP
] = 0,
296 [VK_STENCIL_OP_ZERO
] = 0,
297 [VK_STENCIL_OP_REPLACE
] = 0,
298 [VK_STENCIL_OP_INC_CLAMP
] = 0,
299 [VK_STENCIL_OP_DEC_CLAMP
] = 0,
300 [VK_STENCIL_OP_INVERT
] = 0,
301 [VK_STENCIL_OP_INC_WRAP
] = 0,
302 [VK_STENCIL_OP_DEC_WRAP
] = 0
306 emit_ds_state(struct anv_pipeline
*pipeline
,
307 const VkPipelineDepthStencilStateCreateInfo
*info
)
310 /* We're going to OR this together with the dynamic state. We need
311 * to make sure it's initialized to something useful.
313 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
314 sizeof(pipeline
->gen8
.wm_depth_stencil
));
318 /* VkBool32 depthBoundsEnable; // optional (depth_bounds_test) */
320 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
321 .DepthTestEnable
= info
->depthTestEnable
,
322 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
323 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
324 .DoubleSidedStencilEnable
= true,
326 .StencilTestEnable
= info
->stencilTestEnable
,
327 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
328 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
329 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
330 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
331 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
332 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
333 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
334 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
337 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->gen8
.wm_depth_stencil
, &wm_depth_stencil
);
341 gen8_graphics_pipeline_create(
343 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
344 const struct anv_graphics_pipeline_create_info
*extra
,
345 VkPipeline
* pPipeline
)
347 ANV_FROM_HANDLE(anv_device
, device
, _device
);
348 struct anv_pipeline
*pipeline
;
350 uint32_t offset
, length
;
352 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
354 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
355 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
356 if (pipeline
== NULL
)
357 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
359 pipeline
->device
= device
;
360 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
361 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
363 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
364 if (result
!= VK_SUCCESS
) {
365 anv_device_free(device
, pipeline
);
368 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
369 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
370 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
372 anv_state_stream_init(&pipeline
->program_stream
,
373 &device
->instruction_block_pool
);
375 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
376 pipeline
->shaders
[pCreateInfo
->pStages
[i
].stage
] =
377 anv_shader_from_handle(pCreateInfo
->pStages
[i
].shader
);
380 if (pCreateInfo
->pTessellationState
)
381 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
382 if (pCreateInfo
->pViewportState
)
383 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO");
384 if (pCreateInfo
->pMultisampleState
)
385 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
387 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
389 anv_compiler_run(device
->compiler
, pipeline
);
391 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
392 * hard code this to num_attributes - 2. This is because the attributes
393 * include VUE header and position, which aren't counted as varying
395 if (pipeline
->vs_simd8
== NO_KERNEL
) {
396 pipeline
->wm_prog_data
.num_varying_inputs
=
397 pCreateInfo
->pVertexInputState
->attributeCount
- 2;
400 assert(pCreateInfo
->pVertexInputState
);
401 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
402 assert(pCreateInfo
->pInputAssemblyState
);
403 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
404 assert(pCreateInfo
->pRasterState
);
405 emit_rs_state(pipeline
, pCreateInfo
->pRasterState
, extra
);
406 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
407 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
);
409 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
410 .StatisticsEnable
= true);
411 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
412 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
413 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
414 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
416 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
417 .ConstantBufferOffset
= 0,
418 .ConstantBufferSize
= 4);
419 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
420 .ConstantBufferOffset
= 4,
421 .ConstantBufferSize
= 4);
422 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
423 .ConstantBufferOffset
= 8,
424 .ConstantBufferSize
= 4);
426 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
427 .ChromaKeyKillEnable
= false);
428 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE_SWIZ
);
429 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
431 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
433 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
434 .MinimumPointWidth
= 0.125,
435 .MaximumPointWidth
= 255.875);
437 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
438 .StatisticsEnable
= true,
439 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
440 .LineAntialiasingRegionWidth
= _10pixels
,
441 .EarlyDepthStencilControl
= NORMAL
,
442 .ForceThreadDispatchEnable
= NORMAL
,
443 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
444 .BarycentricInterpolationMode
=
445 pipeline
->wm_prog_data
.barycentric_interp_modes
);
447 uint32_t samples
= 1;
448 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
449 bool enable_sampling
= samples
> 1 ? true : false;
451 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
452 .PixelPositionOffsetEnable
= enable_sampling
,
453 .PixelLocation
= CENTER
,
454 .NumberofMultisamples
= log2_samples
);
456 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SAMPLE_MASK
,
457 .SampleMask
= 0xffff);
459 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
460 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
461 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
462 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
464 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
465 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
466 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
467 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
469 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
470 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
471 .HSURBEntryAllocationSize
= 0,
472 .HSNumberofURBEntries
= 0);
474 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
475 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
476 .DSURBEntryAllocationSize
= 0,
477 .DSNumberofURBEntries
= 0);
479 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
481 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
483 if (pipeline
->gs_vec4
== NO_KERNEL
)
484 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
486 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
487 .SingleProgramFlow
= false,
488 .KernelStartPointer
= pipeline
->gs_vec4
,
489 .VectorMaskEnable
= Vmask
,
491 .BindingTableEntryCount
= 0,
492 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
494 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
495 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
497 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
498 .OutputTopology
= gs_prog_data
->output_topology
,
499 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
500 .DispatchGRFStartRegisterForURBData
=
501 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
503 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
504 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
505 //pipeline->gs_prog_data.dispatch_mode |
506 .StatisticsEnable
= true,
507 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
508 .ReorderMode
= TRAILING
,
511 .ControlDataFormat
= gs_prog_data
->control_data_format
,
513 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
514 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
515 * UserClipDistanceCullTestEnableBitmask(v)
518 .VertexURBEntryOutputReadOffset
= offset
,
519 .VertexURBEntryOutputLength
= length
);
521 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
522 /* Skip the VUE header and position slots */
524 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
526 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
527 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
528 .FunctionEnable
= false,
529 /* Even if VS is disabled, SBE still gets the amount of
530 * vertex data to read from this field. */
531 .VertexURBEntryOutputReadOffset
= offset
,
532 .VertexURBEntryOutputLength
= length
);
534 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
535 .KernelStartPointer
= pipeline
->vs_simd8
,
536 .SingleVertexDispatch
= Multiple
,
537 .VectorMaskEnable
= Dmask
,
539 .BindingTableEntryCount
=
540 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
541 .ThreadDispatchPriority
= Normal
,
542 .FloatingPointMode
= IEEE754
,
543 .IllegalOpcodeExceptionEnable
= false,
544 .AccessesUAV
= false,
545 .SoftwareExceptionEnable
= false,
547 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
548 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
550 .DispatchGRFStartRegisterForURBData
=
551 vue_prog_data
->base
.dispatch_grf_start_reg
,
552 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
553 .VertexURBEntryReadOffset
= 0,
555 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
556 .StatisticsEnable
= false,
557 .SIMD8DispatchEnable
= true,
558 .VertexCacheDisable
= false,
559 .FunctionEnable
= true,
561 .VertexURBEntryOutputReadOffset
= offset
,
562 .VertexURBEntryOutputLength
= length
,
563 .UserClipDistanceClipTestEnableBitmask
= 0,
564 .UserClipDistanceCullTestEnableBitmask
= 0);
566 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
567 uint32_t ksp0
, ksp2
, grf_start0
, grf_start2
;
571 if (pipeline
->ps_simd8
!= NO_KERNEL
) {
572 ksp0
= pipeline
->ps_simd8
;
573 grf_start0
= wm_prog_data
->base
.dispatch_grf_start_reg
;
574 if (pipeline
->ps_simd16
!= NO_KERNEL
) {
575 ksp2
= pipeline
->ps_simd16
;
576 grf_start2
= wm_prog_data
->dispatch_grf_start_reg_16
;
578 } else if (pipeline
->ps_simd16
!= NO_KERNEL
) {
579 ksp0
= pipeline
->ps_simd16
;
580 grf_start0
= wm_prog_data
->dispatch_grf_start_reg_16
;
582 unreachable("no ps shader");
585 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
586 .KernelStartPointer0
= ksp0
,
588 .SingleProgramFlow
= false,
589 .VectorMaskEnable
= true,
592 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
593 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
595 .MaximumNumberofThreadsPerPSD
= 64 - 2,
596 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
597 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
598 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
599 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
600 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
601 ._32PixelDispatchEnable
= false,
603 .DispatchGRFStartRegisterForConstantSetupData0
= grf_start0
,
604 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
605 .DispatchGRFStartRegisterForConstantSetupData2
= grf_start2
,
607 .KernelStartPointer1
= 0,
608 .KernelStartPointer2
= ksp2
);
610 bool per_sample_ps
= false;
611 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
612 .PixelShaderValid
= true,
613 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
614 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
615 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
616 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
617 .PixelShaderIsPerSample
= per_sample_ps
);
619 *pPipeline
= anv_pipeline_to_handle(pipeline
);
624 VkResult
gen8_compute_pipeline_create(
626 const VkComputePipelineCreateInfo
* pCreateInfo
,
627 VkPipeline
* pPipeline
)
629 ANV_FROM_HANDLE(anv_device
, device
, _device
);
630 struct anv_pipeline
*pipeline
;
633 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
635 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
636 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
637 if (pipeline
== NULL
)
638 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
640 pipeline
->device
= device
;
641 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
643 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
644 if (result
!= VK_SUCCESS
) {
645 anv_device_free(device
, pipeline
);
648 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
649 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
650 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
652 anv_state_stream_init(&pipeline
->program_stream
,
653 &device
->instruction_block_pool
);
655 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
657 pipeline
->shaders
[VK_SHADER_STAGE_COMPUTE
] =
658 anv_shader_from_handle(pCreateInfo
->cs
.shader
);
660 pipeline
->use_repclear
= false;
662 anv_compiler_run(device
->compiler
, pipeline
);
664 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
666 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
667 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
668 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
669 .ScratchSpaceBasePointerHigh
= 0,
672 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
673 .NumberofURBEntries
= 2,
674 .ResetGatewayTimer
= true,
675 .BypassGatewayControl
= true,
676 .URBEntryAllocationSize
= 2,
677 .CURBEAllocationSize
= 0);
679 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
680 uint32_t group_size
= prog_data
->local_size
[0] *
681 prog_data
->local_size
[1] * prog_data
->local_size
[2];
682 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
683 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
686 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
688 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
691 *pPipeline
= anv_pipeline_to_handle(pipeline
);