2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 emit_vertex_input(struct anv_pipeline
*pipeline
,
34 const VkPipelineVertexInputStateCreateInfo
*info
)
36 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
39 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
40 GEN8_3DSTATE_VERTEX_ELEMENTS
);
42 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
43 const VkVertexInputAttributeDescription
*desc
=
44 &info
->pVertexAttributeDescriptions
[i
];
45 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
47 struct GEN8_VERTEX_ELEMENT_STATE element
= {
48 .VertexBufferIndex
= desc
->binding
,
50 .SourceElementFormat
= format
->surface_format
,
51 .EdgeFlagEnable
= false,
52 .SourceElementOffset
= desc
->offsetInBytes
,
53 .Component0Control
= VFCOMP_STORE_SRC
,
54 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
55 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
56 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
58 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
60 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
61 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
62 .VertexElementIndex
= i
,
63 /* Vulkan so far doesn't have an instance divisor, so
64 * this is always 1 (ignored if not instancing). */
65 .InstanceDataStepRate
= 1);
68 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
69 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
70 .VertexIDComponentNumber
= 2,
71 .VertexIDElementOffset
= info
->bindingCount
,
72 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
73 .InstanceIDComponentNumber
= 3,
74 .InstanceIDElementOffset
= info
->bindingCount
);
78 emit_ia_state(struct anv_pipeline
*pipeline
,
79 const VkPipelineInputAssemblyStateCreateInfo
*info
,
80 const struct anv_graphics_pipeline_create_info
*extra
)
82 struct GEN8_3DSTATE_VF vf
= {
83 GEN8_3DSTATE_VF_header
,
84 .IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
86 GEN8_3DSTATE_VF_pack(NULL
, pipeline
->gen8
.vf
, &vf
);
88 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
89 .PrimitiveTopologyType
= pipeline
->topology
);
93 emit_rs_state(struct anv_pipeline
*pipeline
,
94 const VkPipelineRasterStateCreateInfo
*info
,
95 const struct anv_graphics_pipeline_create_info
*extra
)
97 static const uint32_t vk_to_gen_cullmode
[] = {
98 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
99 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
100 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
101 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
104 static const uint32_t vk_to_gen_fillmode
[] = {
105 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
106 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
107 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
110 static const uint32_t vk_to_gen_front_face
[] = {
111 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
112 [VK_FRONT_FACE_CW
] = Clockwise
115 struct GEN8_3DSTATE_SF sf
= {
116 GEN8_3DSTATE_SF_header
,
117 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
118 .TriangleStripListProvokingVertexSelect
= 0,
119 .LineStripListProvokingVertexSelect
= 0,
120 .TriangleFanProvokingVertexSelect
= 0,
121 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
125 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
127 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->gen8
.sf
, &sf
);
129 struct GEN8_3DSTATE_RASTER raster
= {
130 GEN8_3DSTATE_RASTER_header
,
131 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
132 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
133 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
134 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
135 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
136 .ViewportZClipTestEnable
= info
->depthClipEnable
139 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->gen8
.raster
, &raster
);
143 emit_cb_state(struct anv_pipeline
*pipeline
,
144 const VkPipelineColorBlendStateCreateInfo
*info
)
146 struct anv_device
*device
= pipeline
->device
;
148 static const uint32_t vk_to_gen_logic_op
[] = {
149 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
150 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
151 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
152 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
153 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
154 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
155 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
156 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
157 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
158 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
159 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
160 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
161 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
162 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
163 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
164 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
167 static const uint32_t vk_to_gen_blend
[] = {
168 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
169 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
170 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
171 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
172 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
173 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
174 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
175 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
176 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
177 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
178 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
179 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
180 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
181 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
182 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
183 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
184 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
185 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
186 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
189 static const uint32_t vk_to_gen_blend_op
[] = {
190 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
191 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
192 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
193 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
194 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
197 uint32_t num_dwords
= GEN8_BLEND_STATE_length
;
198 pipeline
->blend_state
=
199 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
201 struct GEN8_BLEND_STATE blend_state
= {
202 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
205 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
206 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
208 blend_state
.Entry
[i
] = (struct GEN8_BLEND_STATE_ENTRY
) {
209 .LogicOpEnable
= info
->logicOpEnable
,
210 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
211 .ColorBufferBlendEnable
= a
->blendEnable
,
212 .PreBlendSourceOnlyClampEnable
= false,
213 .PreBlendColorClampEnable
= false,
214 .PostBlendColorClampEnable
= false,
215 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
216 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
217 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
218 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
219 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
220 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
221 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
222 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
223 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
224 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
228 GEN8_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
230 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
231 .BlendStatePointer
= pipeline
->blend_state
.offset
,
232 .BlendStatePointerValid
= true);
235 static const uint32_t vk_to_gen_compare_op
[] = {
236 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
237 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
238 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
239 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
240 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
241 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
242 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
243 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
246 static const uint32_t vk_to_gen_stencil_op
[] = {
247 [VK_STENCIL_OP_KEEP
] = 0,
248 [VK_STENCIL_OP_ZERO
] = 0,
249 [VK_STENCIL_OP_REPLACE
] = 0,
250 [VK_STENCIL_OP_INC_CLAMP
] = 0,
251 [VK_STENCIL_OP_DEC_CLAMP
] = 0,
252 [VK_STENCIL_OP_INVERT
] = 0,
253 [VK_STENCIL_OP_INC_WRAP
] = 0,
254 [VK_STENCIL_OP_DEC_WRAP
] = 0
258 emit_ds_state(struct anv_pipeline
*pipeline
,
259 const VkPipelineDepthStencilStateCreateInfo
*info
)
262 /* We're going to OR this together with the dynamic state. We need
263 * to make sure it's initialized to something useful.
265 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
266 sizeof(pipeline
->gen8
.wm_depth_stencil
));
270 /* VkBool32 depthBoundsEnable; // optional (depth_bounds_test) */
272 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
273 .DepthTestEnable
= info
->depthTestEnable
,
274 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
275 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
276 .DoubleSidedStencilEnable
= true,
278 .StencilTestEnable
= info
->stencilTestEnable
,
279 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
280 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
281 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
282 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
283 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
284 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
285 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
286 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
289 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->gen8
.wm_depth_stencil
, &wm_depth_stencil
);
293 gen8_graphics_pipeline_create(
295 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
296 const struct anv_graphics_pipeline_create_info
*extra
,
297 VkPipeline
* pPipeline
)
299 ANV_FROM_HANDLE(anv_device
, device
, _device
);
300 struct anv_pipeline
*pipeline
;
302 uint32_t offset
, length
;
304 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
306 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
307 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
308 if (pipeline
== NULL
)
309 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
311 result
= anv_pipeline_init(pipeline
, device
, pCreateInfo
, extra
);
312 if (result
!= VK_SUCCESS
)
315 pipeline
->device
= device
;
316 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
317 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
319 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
320 if (result
!= VK_SUCCESS
) {
321 anv_device_free(device
, pipeline
);
324 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
325 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
326 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
328 anv_state_stream_init(&pipeline
->program_stream
,
329 &device
->instruction_block_pool
);
331 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
332 pipeline
->shaders
[pCreateInfo
->pStages
[i
].stage
] =
333 anv_shader_from_handle(pCreateInfo
->pStages
[i
].shader
);
336 if (pCreateInfo
->pTessellationState
)
337 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
338 if (pCreateInfo
->pViewportState
)
339 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO");
340 if (pCreateInfo
->pMultisampleState
)
341 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
343 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
345 anv_compiler_run(device
->compiler
, pipeline
);
347 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
348 * hard code this to num_attributes - 2. This is because the attributes
349 * include VUE header and position, which aren't counted as varying
351 if (pipeline
->vs_simd8
== NO_KERNEL
) {
352 pipeline
->wm_prog_data
.num_varying_inputs
=
353 pCreateInfo
->pVertexInputState
->attributeCount
- 2;
356 assert(pCreateInfo
->pVertexInputState
);
357 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
358 assert(pCreateInfo
->pInputAssemblyState
);
359 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
360 assert(pCreateInfo
->pRasterState
);
361 emit_rs_state(pipeline
, pCreateInfo
->pRasterState
, extra
);
362 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
363 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
);
365 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
366 .StatisticsEnable
= true);
367 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
368 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
369 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
370 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
372 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
373 .ConstantBufferOffset
= 0,
374 .ConstantBufferSize
= 4);
375 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
376 .ConstantBufferOffset
= 4,
377 .ConstantBufferSize
= 4);
378 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
379 .ConstantBufferOffset
= 8,
380 .ConstantBufferSize
= 4);
382 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
383 .ChromaKeyKillEnable
= false);
384 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE_SWIZ
);
385 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
387 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
389 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
390 .MinimumPointWidth
= 0.125,
391 .MaximumPointWidth
= 255.875);
393 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
394 .StatisticsEnable
= true,
395 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
396 .LineAntialiasingRegionWidth
= _10pixels
,
397 .EarlyDepthStencilControl
= NORMAL
,
398 .ForceThreadDispatchEnable
= NORMAL
,
399 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
400 .BarycentricInterpolationMode
=
401 pipeline
->wm_prog_data
.barycentric_interp_modes
);
403 uint32_t samples
= 1;
404 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
405 bool enable_sampling
= samples
> 1 ? true : false;
407 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
408 .PixelPositionOffsetEnable
= enable_sampling
,
409 .PixelLocation
= CENTER
,
410 .NumberofMultisamples
= log2_samples
);
412 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SAMPLE_MASK
,
413 .SampleMask
= 0xffff);
415 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
416 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
417 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
418 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
420 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
421 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
422 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
423 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
425 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
426 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
427 .HSURBEntryAllocationSize
= 0,
428 .HSNumberofURBEntries
= 0);
430 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
431 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
432 .DSURBEntryAllocationSize
= 0,
433 .DSNumberofURBEntries
= 0);
435 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
437 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
439 if (pipeline
->gs_vec4
== NO_KERNEL
)
440 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
442 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
443 .SingleProgramFlow
= false,
444 .KernelStartPointer
= pipeline
->gs_vec4
,
445 .VectorMaskEnable
= Vmask
,
447 .BindingTableEntryCount
= 0,
448 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
450 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
451 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
453 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
454 .OutputTopology
= gs_prog_data
->output_topology
,
455 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
456 .DispatchGRFStartRegisterForURBData
=
457 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
459 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
460 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
461 //pipeline->gs_prog_data.dispatch_mode |
462 .StatisticsEnable
= true,
463 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
464 .ReorderMode
= TRAILING
,
467 .ControlDataFormat
= gs_prog_data
->control_data_format
,
469 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
470 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
471 * UserClipDistanceCullTestEnableBitmask(v)
474 .VertexURBEntryOutputReadOffset
= offset
,
475 .VertexURBEntryOutputLength
= length
);
477 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
478 /* Skip the VUE header and position slots */
480 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
482 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
483 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
484 .FunctionEnable
= false,
485 /* Even if VS is disabled, SBE still gets the amount of
486 * vertex data to read from this field. */
487 .VertexURBEntryOutputReadOffset
= offset
,
488 .VertexURBEntryOutputLength
= length
);
490 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
491 .KernelStartPointer
= pipeline
->vs_simd8
,
492 .SingleVertexDispatch
= Multiple
,
493 .VectorMaskEnable
= Dmask
,
495 .BindingTableEntryCount
=
496 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
497 .ThreadDispatchPriority
= Normal
,
498 .FloatingPointMode
= IEEE754
,
499 .IllegalOpcodeExceptionEnable
= false,
500 .AccessesUAV
= false,
501 .SoftwareExceptionEnable
= false,
503 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
504 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
506 .DispatchGRFStartRegisterForURBData
=
507 vue_prog_data
->base
.dispatch_grf_start_reg
,
508 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
509 .VertexURBEntryReadOffset
= 0,
511 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
512 .StatisticsEnable
= false,
513 .SIMD8DispatchEnable
= true,
514 .VertexCacheDisable
= false,
515 .FunctionEnable
= true,
517 .VertexURBEntryOutputReadOffset
= offset
,
518 .VertexURBEntryOutputLength
= length
,
519 .UserClipDistanceClipTestEnableBitmask
= 0,
520 .UserClipDistanceCullTestEnableBitmask
= 0);
522 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
524 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
525 .ForceVertexURBEntryReadLength
= false,
526 .ForceVertexURBEntryReadOffset
= false,
527 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
528 .NumberofSFOutputAttributes
=
529 wm_prog_data
->num_varying_inputs
);
531 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
532 .KernelStartPointer0
= pipeline
->ps_ksp0
,
534 .SingleProgramFlow
= false,
535 .VectorMaskEnable
= true,
538 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
539 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
541 .MaximumNumberofThreadsPerPSD
= 64 - 2,
542 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
543 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
544 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
545 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
546 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
547 ._32PixelDispatchEnable
= false,
549 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
550 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
551 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
553 .KernelStartPointer1
= 0,
554 .KernelStartPointer2
= pipeline
->ps_ksp2
);
556 bool per_sample_ps
= false;
557 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
558 .PixelShaderValid
= true,
559 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
560 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
561 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
562 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
563 .PixelShaderIsPerSample
= per_sample_ps
);
565 *pPipeline
= anv_pipeline_to_handle(pipeline
);
570 VkResult
gen8_compute_pipeline_create(
572 const VkComputePipelineCreateInfo
* pCreateInfo
,
573 VkPipeline
* pPipeline
)
575 ANV_FROM_HANDLE(anv_device
, device
, _device
);
576 struct anv_pipeline
*pipeline
;
579 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
581 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
582 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
583 if (pipeline
== NULL
)
584 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
586 pipeline
->device
= device
;
587 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
589 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
590 if (result
!= VK_SUCCESS
) {
591 anv_device_free(device
, pipeline
);
594 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
595 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
596 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
598 anv_state_stream_init(&pipeline
->program_stream
,
599 &device
->instruction_block_pool
);
601 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
603 pipeline
->shaders
[VK_SHADER_STAGE_COMPUTE
] =
604 anv_shader_from_handle(pCreateInfo
->cs
.shader
);
606 pipeline
->use_repclear
= false;
608 anv_compiler_run(device
->compiler
, pipeline
);
610 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
612 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
613 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
614 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
615 .ScratchSpaceBasePointerHigh
= 0,
618 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
619 .NumberofURBEntries
= 2,
620 .ResetGatewayTimer
= true,
621 .BypassGatewayControl
= true,
622 .URBEntryAllocationSize
= 2,
623 .CURBEAllocationSize
= 0);
625 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
626 uint32_t group_size
= prog_data
->local_size
[0] *
627 prog_data
->local_size
[1] * prog_data
->local_size
[2];
628 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
629 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
632 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
634 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
637 *pPipeline
= anv_pipeline_to_handle(pipeline
);