2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
33 emit_vertex_input(struct anv_pipeline
*pipeline
,
34 const VkPipelineVertexInputStateCreateInfo
*info
)
36 const uint32_t num_dwords
= 1 + info
->attributeCount
* 2;
39 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
40 GEN8_3DSTATE_VERTEX_ELEMENTS
);
42 for (uint32_t i
= 0; i
< info
->attributeCount
; i
++) {
43 const VkVertexInputAttributeDescription
*desc
=
44 &info
->pVertexAttributeDescriptions
[i
];
45 const struct anv_format
*format
= anv_format_for_vk_format(desc
->format
);
47 struct GEN8_VERTEX_ELEMENT_STATE element
= {
48 .VertexBufferIndex
= desc
->binding
,
50 .SourceElementFormat
= format
->surface_format
,
51 .EdgeFlagEnable
= false,
52 .SourceElementOffset
= desc
->offsetInBytes
,
53 .Component0Control
= VFCOMP_STORE_SRC
,
54 .Component1Control
= format
->num_channels
>= 2 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
55 .Component2Control
= format
->num_channels
>= 3 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_0
,
56 .Component3Control
= format
->num_channels
>= 4 ? VFCOMP_STORE_SRC
: VFCOMP_STORE_1_FP
58 GEN8_VERTEX_ELEMENT_STATE_pack(NULL
, &p
[1 + i
* 2], &element
);
60 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_INSTANCING
,
61 .InstancingEnable
= pipeline
->instancing_enable
[desc
->binding
],
62 .VertexElementIndex
= i
,
63 /* Vulkan so far doesn't have an instance divisor, so
64 * this is always 1 (ignored if not instancing). */
65 .InstanceDataStepRate
= 1);
68 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_SGVS
,
69 .VertexIDEnable
= pipeline
->vs_prog_data
.uses_vertexid
,
70 .VertexIDComponentNumber
= 2,
71 .VertexIDElementOffset
= info
->bindingCount
,
72 .InstanceIDEnable
= pipeline
->vs_prog_data
.uses_instanceid
,
73 .InstanceIDComponentNumber
= 3,
74 .InstanceIDElementOffset
= info
->bindingCount
);
78 emit_ia_state(struct anv_pipeline
*pipeline
,
79 const VkPipelineInputAssemblyStateCreateInfo
*info
,
80 const struct anv_graphics_pipeline_create_info
*extra
)
82 struct GEN8_3DSTATE_VF vf
= {
83 GEN8_3DSTATE_VF_header
,
84 .IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
86 GEN8_3DSTATE_VF_pack(NULL
, pipeline
->gen8
.vf
, &vf
);
88 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_TOPOLOGY
,
89 .PrimitiveTopologyType
= pipeline
->topology
);
93 emit_rs_state(struct anv_pipeline
*pipeline
,
94 const VkPipelineRasterStateCreateInfo
*info
,
95 const struct anv_graphics_pipeline_create_info
*extra
)
97 static const uint32_t vk_to_gen_cullmode
[] = {
98 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
99 [VK_CULL_MODE_FRONT
] = CULLMODE_FRONT
,
100 [VK_CULL_MODE_BACK
] = CULLMODE_BACK
,
101 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
104 static const uint32_t vk_to_gen_fillmode
[] = {
105 [VK_FILL_MODE_POINTS
] = RASTER_POINT
,
106 [VK_FILL_MODE_WIREFRAME
] = RASTER_WIREFRAME
,
107 [VK_FILL_MODE_SOLID
] = RASTER_SOLID
110 static const uint32_t vk_to_gen_front_face
[] = {
111 [VK_FRONT_FACE_CCW
] = CounterClockwise
,
112 [VK_FRONT_FACE_CW
] = Clockwise
115 struct GEN8_3DSTATE_SF sf
= {
116 GEN8_3DSTATE_SF_header
,
117 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
118 .TriangleStripListProvokingVertexSelect
= 0,
119 .LineStripListProvokingVertexSelect
= 0,
120 .TriangleFanProvokingVertexSelect
= 0,
121 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
125 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
127 GEN8_3DSTATE_SF_pack(NULL
, pipeline
->gen8
.sf
, &sf
);
129 struct GEN8_3DSTATE_RASTER raster
= {
130 GEN8_3DSTATE_RASTER_header
,
131 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
132 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
133 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
134 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->fillMode
],
135 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
136 .ViewportZClipTestEnable
= info
->depthClipEnable
139 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE
,
140 .ForceVertexURBEntryReadLength
= false,
141 .ForceVertexURBEntryReadOffset
= false,
142 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
143 .NumberofSFOutputAttributes
=
144 pipeline
->wm_prog_data
.num_varying_inputs
);
146 GEN8_3DSTATE_RASTER_pack(NULL
, pipeline
->gen8
.raster
, &raster
);
150 emit_cb_state(struct anv_pipeline
*pipeline
,
151 const VkPipelineColorBlendStateCreateInfo
*info
)
153 struct anv_device
*device
= pipeline
->device
;
155 static const uint32_t vk_to_gen_logic_op
[] = {
156 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
157 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
158 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
159 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
160 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
161 [VK_LOGIC_OP_NOOP
] = LOGICOP_NOOP
,
162 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
163 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
164 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
165 [VK_LOGIC_OP_EQUIV
] = LOGICOP_EQUIV
,
166 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
167 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
168 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
169 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
170 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
171 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
174 static const uint32_t vk_to_gen_blend
[] = {
175 [VK_BLEND_ZERO
] = BLENDFACTOR_ZERO
,
176 [VK_BLEND_ONE
] = BLENDFACTOR_ONE
,
177 [VK_BLEND_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
178 [VK_BLEND_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
179 [VK_BLEND_DEST_COLOR
] = BLENDFACTOR_DST_COLOR
,
180 [VK_BLEND_ONE_MINUS_DEST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
181 [VK_BLEND_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
182 [VK_BLEND_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
183 [VK_BLEND_DEST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
184 [VK_BLEND_ONE_MINUS_DEST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
185 [VK_BLEND_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
186 [VK_BLEND_ONE_MINUS_CONSTANT_COLOR
] = BLENDFACTOR_INV_CONST_COLOR
,
187 [VK_BLEND_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
188 [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA
] = BLENDFACTOR_INV_CONST_ALPHA
,
189 [VK_BLEND_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
190 [VK_BLEND_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
191 [VK_BLEND_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
192 [VK_BLEND_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
193 [VK_BLEND_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
196 static const uint32_t vk_to_gen_blend_op
[] = {
197 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
198 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
199 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
200 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
201 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
204 uint32_t num_dwords
= GEN8_BLEND_STATE_length
;
205 pipeline
->blend_state
=
206 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
208 struct GEN8_BLEND_STATE blend_state
= {
209 .AlphaToCoverageEnable
= info
->alphaToCoverageEnable
,
212 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
213 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
215 blend_state
.Entry
[i
] = (struct GEN8_BLEND_STATE_ENTRY
) {
216 .LogicOpEnable
= info
->logicOpEnable
,
217 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
218 .ColorBufferBlendEnable
= a
->blendEnable
,
219 .PreBlendSourceOnlyClampEnable
= false,
220 .PreBlendColorClampEnable
= false,
221 .PostBlendColorClampEnable
= false,
222 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcBlendColor
],
223 .DestinationBlendFactor
= vk_to_gen_blend
[a
->destBlendColor
],
224 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->blendOpColor
],
225 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcBlendAlpha
],
226 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->destBlendAlpha
],
227 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->blendOpAlpha
],
228 .WriteDisableAlpha
= !(a
->channelWriteMask
& VK_CHANNEL_A_BIT
),
229 .WriteDisableRed
= !(a
->channelWriteMask
& VK_CHANNEL_R_BIT
),
230 .WriteDisableGreen
= !(a
->channelWriteMask
& VK_CHANNEL_G_BIT
),
231 .WriteDisableBlue
= !(a
->channelWriteMask
& VK_CHANNEL_B_BIT
),
235 GEN8_BLEND_STATE_pack(NULL
, pipeline
->blend_state
.map
, &blend_state
);
237 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_BLEND_STATE_POINTERS
,
238 .BlendStatePointer
= pipeline
->blend_state
.offset
,
239 .BlendStatePointerValid
= true);
242 static const uint32_t vk_to_gen_compare_op
[] = {
243 [VK_COMPARE_OP_NEVER
] = COMPAREFUNCTION_NEVER
,
244 [VK_COMPARE_OP_LESS
] = COMPAREFUNCTION_LESS
,
245 [VK_COMPARE_OP_EQUAL
] = COMPAREFUNCTION_EQUAL
,
246 [VK_COMPARE_OP_LESS_EQUAL
] = COMPAREFUNCTION_LEQUAL
,
247 [VK_COMPARE_OP_GREATER
] = COMPAREFUNCTION_GREATER
,
248 [VK_COMPARE_OP_NOT_EQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
249 [VK_COMPARE_OP_GREATER_EQUAL
] = COMPAREFUNCTION_GEQUAL
,
250 [VK_COMPARE_OP_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
253 static const uint32_t vk_to_gen_stencil_op
[] = {
254 [VK_STENCIL_OP_KEEP
] = 0,
255 [VK_STENCIL_OP_ZERO
] = 0,
256 [VK_STENCIL_OP_REPLACE
] = 0,
257 [VK_STENCIL_OP_INC_CLAMP
] = 0,
258 [VK_STENCIL_OP_DEC_CLAMP
] = 0,
259 [VK_STENCIL_OP_INVERT
] = 0,
260 [VK_STENCIL_OP_INC_WRAP
] = 0,
261 [VK_STENCIL_OP_DEC_WRAP
] = 0
265 emit_ds_state(struct anv_pipeline
*pipeline
,
266 const VkPipelineDepthStencilStateCreateInfo
*info
)
269 /* We're going to OR this together with the dynamic state. We need
270 * to make sure it's initialized to something useful.
272 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
273 sizeof(pipeline
->gen8
.wm_depth_stencil
));
277 /* VkBool32 depthBoundsEnable; // optional (depth_bounds_test) */
279 struct GEN8_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
280 .DepthTestEnable
= info
->depthTestEnable
,
281 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
282 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
283 .DoubleSidedStencilEnable
= true,
285 .StencilTestEnable
= info
->stencilTestEnable
,
286 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilFailOp
],
287 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.stencilPassOp
],
288 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.stencilDepthFailOp
],
289 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.stencilCompareOp
],
290 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.stencilFailOp
],
291 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.stencilPassOp
],
292 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.stencilDepthFailOp
],
293 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.stencilCompareOp
],
296 GEN8_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, pipeline
->gen8
.wm_depth_stencil
, &wm_depth_stencil
);
300 gen8_graphics_pipeline_create(
302 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
303 const struct anv_graphics_pipeline_create_info
*extra
,
304 VkPipeline
* pPipeline
)
306 ANV_FROM_HANDLE(anv_device
, device
, _device
);
307 struct anv_pipeline
*pipeline
;
309 uint32_t offset
, length
;
311 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
313 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
314 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
315 if (pipeline
== NULL
)
316 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
318 result
= anv_pipeline_init(pipeline
, device
, pCreateInfo
, extra
);
319 if (result
!= VK_SUCCESS
)
322 pipeline
->device
= device
;
323 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
324 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
326 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
327 if (result
!= VK_SUCCESS
) {
328 anv_device_free(device
, pipeline
);
331 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
332 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
333 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
335 anv_state_stream_init(&pipeline
->program_stream
,
336 &device
->instruction_block_pool
);
338 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
339 pipeline
->shaders
[pCreateInfo
->pStages
[i
].stage
] =
340 anv_shader_from_handle(pCreateInfo
->pStages
[i
].shader
);
343 if (pCreateInfo
->pTessellationState
)
344 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO");
345 if (pCreateInfo
->pViewportState
)
346 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO");
347 if (pCreateInfo
->pMultisampleState
)
348 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
350 pipeline
->use_repclear
= extra
&& extra
->use_repclear
;
352 anv_compiler_run(device
->compiler
, pipeline
);
354 /* FIXME: The compiler dead-codes FS inputs when we don't have a VS, so we
355 * hard code this to num_attributes - 2. This is because the attributes
356 * include VUE header and position, which aren't counted as varying
358 if (pipeline
->vs_simd8
== NO_KERNEL
) {
359 pipeline
->wm_prog_data
.num_varying_inputs
=
360 pCreateInfo
->pVertexInputState
->attributeCount
- 2;
363 assert(pCreateInfo
->pVertexInputState
);
364 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
365 assert(pCreateInfo
->pInputAssemblyState
);
366 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
367 assert(pCreateInfo
->pRasterState
);
368 emit_rs_state(pipeline
, pCreateInfo
->pRasterState
, extra
);
369 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
370 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
);
372 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VF_STATISTICS
,
373 .StatisticsEnable
= true);
374 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_HS
, .Enable
= false);
375 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_TE
, .TEEnable
= false);
376 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_DS
, .FunctionEnable
= false);
377 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_STREAMOUT
, .SOFunctionEnable
= false);
379 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS
,
380 .ConstantBufferOffset
= 0,
381 .ConstantBufferSize
= 4);
382 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS
,
383 .ConstantBufferOffset
= 4,
384 .ConstantBufferSize
= 4);
385 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS
,
386 .ConstantBufferOffset
= 8,
387 .ConstantBufferSize
= 4);
389 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM_CHROMAKEY
,
390 .ChromaKeyKillEnable
= false);
391 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SBE_SWIZ
);
392 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_AA_LINE_PARAMETERS
);
394 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_CLIP
,
396 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
397 .MinimumPointWidth
= 0.125,
398 .MaximumPointWidth
= 255.875);
400 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_WM
,
401 .StatisticsEnable
= true,
402 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
403 .LineAntialiasingRegionWidth
= _10pixels
,
404 .EarlyDepthStencilControl
= NORMAL
,
405 .ForceThreadDispatchEnable
= NORMAL
,
406 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
407 .BarycentricInterpolationMode
=
408 pipeline
->wm_prog_data
.barycentric_interp_modes
);
410 uint32_t samples
= 1;
411 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
412 bool enable_sampling
= samples
> 1 ? true : false;
414 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_MULTISAMPLE
,
415 .PixelPositionOffsetEnable
= enable_sampling
,
416 .PixelLocation
= CENTER
,
417 .NumberofMultisamples
= log2_samples
);
419 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_SAMPLE_MASK
,
420 .SampleMask
= 0xffff);
422 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_VS
,
423 .VSURBStartingAddress
= pipeline
->urb
.vs_start
,
424 .VSURBEntryAllocationSize
= pipeline
->urb
.vs_size
- 1,
425 .VSNumberofURBEntries
= pipeline
->urb
.nr_vs_entries
);
427 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_GS
,
428 .GSURBStartingAddress
= pipeline
->urb
.gs_start
,
429 .GSURBEntryAllocationSize
= pipeline
->urb
.gs_size
- 1,
430 .GSNumberofURBEntries
= pipeline
->urb
.nr_gs_entries
);
432 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_HS
,
433 .HSURBStartingAddress
= pipeline
->urb
.vs_start
,
434 .HSURBEntryAllocationSize
= 0,
435 .HSNumberofURBEntries
= 0);
437 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_URB_DS
,
438 .DSURBStartingAddress
= pipeline
->urb
.vs_start
,
439 .DSURBEntryAllocationSize
= 0,
440 .DSNumberofURBEntries
= 0);
442 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
444 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
446 if (pipeline
->gs_vec4
== NO_KERNEL
)
447 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
, .Enable
= false);
449 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_GS
,
450 .SingleProgramFlow
= false,
451 .KernelStartPointer
= pipeline
->gs_vec4
,
452 .VectorMaskEnable
= Vmask
,
454 .BindingTableEntryCount
= 0,
455 .ExpectedVertexCount
= pipeline
->gs_vertex_count
,
457 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_GEOMETRY
],
458 .PerThreadScratchSpace
= ffs(gs_prog_data
->base
.base
.total_scratch
/ 2048),
460 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
461 .OutputTopology
= gs_prog_data
->output_topology
,
462 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
463 .DispatchGRFStartRegisterForURBData
=
464 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
466 .MaximumNumberofThreads
= device
->info
.max_gs_threads
,
467 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
468 //pipeline->gs_prog_data.dispatch_mode |
469 .StatisticsEnable
= true,
470 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
471 .ReorderMode
= TRAILING
,
474 .ControlDataFormat
= gs_prog_data
->control_data_format
,
476 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
477 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
478 * UserClipDistanceCullTestEnableBitmask(v)
481 .VertexURBEntryOutputReadOffset
= offset
,
482 .VertexURBEntryOutputLength
= length
);
484 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
485 /* Skip the VUE header and position slots */
487 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
489 if (pipeline
->vs_simd8
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
490 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
491 .FunctionEnable
= false,
492 /* Even if VS is disabled, SBE still gets the amount of
493 * vertex data to read from this field. */
494 .VertexURBEntryOutputReadOffset
= offset
,
495 .VertexURBEntryOutputLength
= length
);
497 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_VS
,
498 .KernelStartPointer
= pipeline
->vs_simd8
,
499 .SingleVertexDispatch
= Multiple
,
500 .VectorMaskEnable
= Dmask
,
502 .BindingTableEntryCount
=
503 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
504 .ThreadDispatchPriority
= Normal
,
505 .FloatingPointMode
= IEEE754
,
506 .IllegalOpcodeExceptionEnable
= false,
507 .AccessesUAV
= false,
508 .SoftwareExceptionEnable
= false,
510 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_VERTEX
],
511 .PerThreadScratchSpace
= ffs(vue_prog_data
->base
.total_scratch
/ 2048),
513 .DispatchGRFStartRegisterForURBData
=
514 vue_prog_data
->base
.dispatch_grf_start_reg
,
515 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
516 .VertexURBEntryReadOffset
= 0,
518 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
519 .StatisticsEnable
= false,
520 .SIMD8DispatchEnable
= true,
521 .VertexCacheDisable
= false,
522 .FunctionEnable
= true,
524 .VertexURBEntryOutputReadOffset
= offset
,
525 .VertexURBEntryOutputLength
= length
,
526 .UserClipDistanceClipTestEnableBitmask
= 0,
527 .UserClipDistanceCullTestEnableBitmask
= 0);
529 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
531 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS
,
532 .KernelStartPointer0
= pipeline
->ps_ksp0
,
534 .SingleProgramFlow
= false,
535 .VectorMaskEnable
= true,
538 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
539 .PerThreadScratchSpace
= ffs(wm_prog_data
->base
.total_scratch
/ 2048),
541 .MaximumNumberofThreadsPerPSD
= 64 - 2,
542 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
543 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
544 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
545 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
546 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
547 ._32PixelDispatchEnable
= false,
549 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
550 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
551 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
553 .KernelStartPointer1
= 0,
554 .KernelStartPointer2
= pipeline
->ps_ksp2
);
556 bool per_sample_ps
= false;
557 anv_batch_emit(&pipeline
->batch
, GEN8_3DSTATE_PS_EXTRA
,
558 .PixelShaderValid
= true,
559 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
560 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
561 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
562 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
563 .PixelShaderIsPerSample
= per_sample_ps
);
565 *pPipeline
= anv_pipeline_to_handle(pipeline
);
570 VkResult
gen8_compute_pipeline_create(
572 const VkComputePipelineCreateInfo
* pCreateInfo
,
573 VkPipeline
* pPipeline
)
575 ANV_FROM_HANDLE(anv_device
, device
, _device
);
576 struct anv_pipeline
*pipeline
;
579 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
581 pipeline
= anv_device_alloc(device
, sizeof(*pipeline
), 8,
582 VK_SYSTEM_ALLOC_TYPE_API_OBJECT
);
583 if (pipeline
== NULL
)
584 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
586 pipeline
->device
= device
;
587 pipeline
->layout
= anv_pipeline_layout_from_handle(pCreateInfo
->layout
);
589 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, device
);
590 if (result
!= VK_SUCCESS
) {
591 anv_device_free(device
, pipeline
);
594 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
595 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
596 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
598 anv_state_stream_init(&pipeline
->program_stream
,
599 &device
->instruction_block_pool
);
601 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
603 pipeline
->shaders
[VK_SHADER_STAGE_COMPUTE
] =
604 anv_shader_from_handle(pCreateInfo
->cs
.shader
);
606 pipeline
->use_repclear
= false;
608 anv_compiler_run(device
->compiler
, pipeline
);
610 const struct brw_cs_prog_data
*cs_prog_data
= &pipeline
->cs_prog_data
;
612 anv_batch_emit(&pipeline
->batch
, GEN8_MEDIA_VFE_STATE
,
613 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[VK_SHADER_STAGE_FRAGMENT
],
614 .PerThreadScratchSpace
= ffs(cs_prog_data
->base
.total_scratch
/ 2048),
615 .ScratchSpaceBasePointerHigh
= 0,
618 .MaximumNumberofThreads
= device
->info
.max_cs_threads
- 1,
619 .NumberofURBEntries
= 2,
620 .ResetGatewayTimer
= true,
621 .BypassGatewayControl
= true,
622 .URBEntryAllocationSize
= 2,
623 .CURBEAllocationSize
= 0);
625 struct brw_cs_prog_data
*prog_data
= &pipeline
->cs_prog_data
;
626 uint32_t group_size
= prog_data
->local_size
[0] *
627 prog_data
->local_size
[1] * prog_data
->local_size
[2];
628 pipeline
->cs_thread_width_max
= DIV_ROUND_UP(group_size
, prog_data
->simd_size
);
629 uint32_t remainder
= group_size
& (prog_data
->simd_size
- 1);
632 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
634 pipeline
->cs_right_mask
= ~0u >> (32 - prog_data
->simd_size
);
637 *pPipeline
= anv_pipeline_to_handle(pipeline
);